1 /* $NetBSD: identcpu.c,v 1.141 2026/07/11 03:26:26 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.141 2026/07/11 03:26:26 riastradh Exp $"); 34 35 #include "opt_xen.h" 36 37 #include <sys/param.h> 38 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 43 #include <crypto/aes/aes_impl.h> 44 #include <crypto/aes/arch/x86/aes_ni.h> 45 #include <crypto/aes/arch/x86/aes_sse2_4x32.h> 46 #include <crypto/aes/arch/x86/aes_ssse3.h> 47 #include <crypto/aes/arch/x86/aes_via.h> 48 #include <crypto/chacha/arch/x86/chacha_sse2.h> 49 #include <crypto/chacha/chacha_impl.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/cpu.h> 54 #include <machine/frame.h> 55 #include <machine/pio.h> 56 #include <machine/specialreg.h> 57 58 #include <x86/cacheinfo.h> 59 #include <x86/cputypes.h> 60 #include <x86/cpuvar.h> 61 #include <x86/fpu.h> 62 63 #include <dev/vmt/vmtreg.h> /* for vmt_hvcall() */ 64 #include <dev/vmt/vmtvar.h> /* for vmt_hvcall() */ 65 66 #ifndef XENPV 67 #include "hyperv.h" 68 #if NHYPERV > 0 69 #include <x86/x86/hypervvar.h> 70 #endif 71 #endif 72 73 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 74 75 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 76 AMD_L2L3CACHE_INFO; 77 78 int cpu_vendor; 79 char cpu_brand_string[49]; 80 81 int x86_fpu_save __read_mostly; 82 unsigned int x86_fpu_save_size __read_mostly = sizeof(struct save87); 83 uint64_t x86_xsave_features __read_mostly = 0; 84 size_t x86_xsave_offsets[XSAVE_MAX_COMPONENT+1] __read_mostly; 85 size_t x86_xsave_sizes[XSAVE_MAX_COMPONENT+1] __read_mostly; 86 u_int cpu_max_hypervisor_cpuid = 0; 87 88 /* 89 * Note: these are just the ones that may not have a cpuid instruction. 90 * We deal with the rest in a different way. 91 */ 92 const int i386_nocpuid_cpus[] = { 93 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386SX */ 94 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386 */ 95 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486SX */ 96 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486 */ 97 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_486DLC */ 98 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_6x86 */ 99 CPUVENDOR_NEXGEN, CPUCLASS_386, /* CPU_NX586 */ 100 }; 101 102 static const char cpu_vendor_names[][10] = { 103 "Unknown", "Intel", "NS/Cyrix", "NexGen", "AMD", "IDT/VIA", "Transmeta", 104 "Vortex86" 105 }; 106 107 static void 108 cpu_probe_intel_cache(struct cpu_info *ci) 109 { 110 const struct x86_cache_info *cai; 111 u_int descs[4]; 112 int iterations, i, j; 113 uint8_t desc; 114 115 if (cpuid_level >= 2) { 116 /* Parse the cache info from `cpuid leaf 2', if we have it. */ 117 x86_cpuid(2, descs); 118 iterations = descs[0] & 0xff; 119 while (iterations-- > 0) { 120 for (i = 0; i < 4; i++) { 121 if (descs[i] & 0x80000000) 122 continue; 123 for (j = 0; j < 4; j++) { 124 if (i == 0 && j == 0) 125 continue; 126 desc = (descs[i] >> (j * 8)) & 0xff; 127 if (desc == 0) 128 continue; 129 cai = cpu_cacheinfo_lookup( 130 intel_cpuid_cache_info, desc); 131 if (cai != NULL) { 132 ci->ci_cinfo[cai->cai_index] = 133 *cai; 134 } 135 } 136 } 137 } 138 } 139 140 if (cpuid_level < 4) 141 return; 142 143 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 144 cpu_dcp_cacheinfo(ci, 4); 145 } 146 147 static void 148 cpu_probe_intel_errata(struct cpu_info *ci) 149 { 150 u_int family, model; 151 152 family = CPUID_TO_FAMILY(ci->ci_signature); 153 model = CPUID_TO_MODEL(ci->ci_signature); 154 155 /* 156 * For details, refer to the Intel Pentium and Celeron Processor 157 * N- and J- Series Specification Update (Document number: 334820-010), 158 * August 2022, Revision 010. See page 28, Section 5.30: "APL30 A Store 159 * Instruction May Not Wake Up MWAIT." 160 * https://cdrdv2-public.intel.com/334820/334820-APL_Spec_Update_rev010.pdf 161 * https://web.archive.org/web/20250114072355/https://cdrdv2-public.intel.com/334820/334820-APL_Spec_Update_rev010.pdf 162 * 163 * Disable MWAIT/MONITOR on Apollo Lake CPUs to address the 164 * APL30 erratum. When using the MONITOR/MWAIT instruction 165 * pair, stores to the armed address range may fail to trigger 166 * MWAIT to resume execution. When these instructions are used 167 * to hatch secondary CPUs, this erratum causes SMP boot 168 * failures. 169 */ 170 if (family == 0x6 && model == 0x5C) { 171 wrmsr(MSR_MISC_ENABLE, 172 rdmsr(MSR_MISC_ENABLE) & ~IA32_MISC_MWAIT_EN); 173 174 cpu_feature[1] &= ~CPUID2_MONITOR; 175 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 176 } 177 } 178 179 static void 180 cpu_probe_intel(struct cpu_info *ci) 181 { 182 183 if (cpu_vendor != CPUVENDOR_INTEL) 184 return; 185 186 cpu_probe_intel_cache(ci); 187 cpu_probe_intel_errata(ci); 188 } 189 190 static void 191 cpu_probe_amd_cache(struct cpu_info *ci) 192 { 193 const struct x86_cache_info *cp; 194 struct x86_cache_info *cai; 195 int family, model; 196 u_int descs[4]; 197 u_int lfunc; 198 199 family = CPUID_TO_FAMILY(ci->ci_signature); 200 model = CPUID_TO_MODEL(ci->ci_signature); 201 202 /* K5 model 0 has none of this info. */ 203 if (family == 5 && model == 0) 204 return; 205 206 /* Determine the largest extended function value. */ 207 x86_cpuid(0x80000000, descs); 208 lfunc = descs[0]; 209 210 if (lfunc < 0x80000005) 211 return; 212 213 /* Determine L1 cache/TLB info. */ 214 x86_cpuid(0x80000005, descs); 215 216 /* K6-III and higher have large page TLBs. */ 217 if ((family == 5 && model >= 9) || family >= 6) { 218 cai = &ci->ci_cinfo[CAI_ITLB2]; 219 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 220 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 221 cai->cai_linesize = (4 * 1024 * 1024); 222 223 cai = &ci->ci_cinfo[CAI_DTLB2]; 224 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 225 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 226 cai->cai_linesize = (4 * 1024 * 1024); 227 } 228 229 cai = &ci->ci_cinfo[CAI_ITLB]; 230 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 231 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 232 cai->cai_linesize = (4 * 1024); 233 234 cai = &ci->ci_cinfo[CAI_DTLB]; 235 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 236 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 237 cai->cai_linesize = (4 * 1024); 238 239 cai = &ci->ci_cinfo[CAI_DCACHE]; 240 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 241 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 242 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 243 244 cai = &ci->ci_cinfo[CAI_ICACHE]; 245 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 246 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 247 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 248 249 if (lfunc < 0x80000006) 250 return; 251 252 /* Determine L2 cache/TLB info. */ 253 x86_cpuid(0x80000006, descs); 254 255 cai = &ci->ci_cinfo[CAI_L2CACHE]; 256 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 257 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 258 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 259 260 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 261 cai->cai_associativity); 262 if (cp != NULL) 263 cai->cai_associativity = cp->cai_associativity; 264 else 265 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 266 267 if (family < 0xf) 268 return; 269 270 /* Determine L3 cache info on AMD Family 10h and newer processors */ 271 cai = &ci->ci_cinfo[CAI_L3CACHE]; 272 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 273 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 274 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 275 276 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 277 cai->cai_associativity); 278 if (cp != NULL) 279 cai->cai_associativity = cp->cai_associativity; 280 else 281 cai->cai_associativity = 0; /* XXX Unknown reserved */ 282 283 if (lfunc < 0x80000019) 284 return; 285 286 /* Determine 1GB TLB info. */ 287 x86_cpuid(0x80000019, descs); 288 289 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 290 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[1]); 291 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[1]); 292 cai->cai_linesize = (1 * 1024); 293 294 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 295 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 296 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 297 cai->cai_linesize = (1 * 1024); 298 299 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 300 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 301 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 302 cai->cai_linesize = (1 * 1024); 303 304 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 305 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[0]); 306 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[0]); 307 cai->cai_linesize = (1 * 1024); 308 309 if (lfunc < 0x8000001d) 310 return; 311 312 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 313 cpu_dcp_cacheinfo(ci, 0x8000001d); 314 } 315 316 static void 317 cpu_probe_amd_errata(struct cpu_info *ci) 318 { 319 u_int model; 320 uint64_t val; 321 int flag; 322 323 model = CPUID_TO_MODEL(ci->ci_signature); 324 325 switch (CPUID_TO_FAMILY(ci->ci_signature)) { 326 case 0x05: /* K5 */ 327 if (model == 0) { 328 /* 329 * According to the AMD Processor Recognition App Note, 330 * the AMD-K5 Model 0 uses the wrong bit to indicate 331 * support for global PTEs, instead using bit 9 (APIC) 332 * rather than bit 13 (i.e. "0x200" vs. 0x2000"). 333 */ 334 flag = ci->ci_feat_val[0]; 335 if ((flag & CPUID_APIC) != 0) 336 flag = (flag & ~CPUID_APIC) | CPUID_PGE; 337 ci->ci_feat_val[0] = flag; 338 } 339 break; 340 341 case 0x10: /* Family 10h */ 342 /* 343 * On Family 10h, certain BIOSes do not enable WC+ support. 344 * This causes WC+ to become CD, and degrades guest 345 * performance at the NPT level. 346 * 347 * Explicitly enable WC+ if we're not a guest. 348 */ 349 if (!ISSET(ci->ci_feat_val[1], CPUID2_RAZ)) { 350 val = rdmsr(MSR_BU_CFG2); 351 val &= ~BU_CFG2_CWPLUS_DIS; 352 wrmsr(MSR_BU_CFG2, val); 353 } 354 break; 355 356 case 0x17: 357 /* 358 * "Revision Guide for AMD Family 17h Models 00h-0Fh 359 * Processors" revision 1.12: 360 * 361 * 1057 MWAIT or MWAITX Instructions May Fail to Correctly 362 * Exit From the Monitor Event Pending State 363 * 364 * 1109 MWAIT Instruction May Hang a Thread 365 */ 366 if (model == 0x01) { 367 cpu_feature[1] &= ~CPUID2_MONITOR; 368 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 369 } 370 break; 371 } 372 } 373 374 static void 375 cpu_probe_amd(struct cpu_info *ci) 376 { 377 378 if (cpu_vendor != CPUVENDOR_AMD) 379 return; 380 381 cpu_probe_amd_cache(ci); 382 cpu_probe_amd_errata(ci); 383 } 384 385 static inline uint8_t 386 cyrix_read_reg(uint8_t reg) 387 { 388 389 outb(0x22, reg); 390 return inb(0x23); 391 } 392 393 static inline void 394 cyrix_write_reg(uint8_t reg, uint8_t data) 395 { 396 397 outb(0x22, reg); 398 outb(0x23, data); 399 } 400 401 static void 402 cpu_probe_cyrix_cmn(struct cpu_info *ci) 403 { 404 /* 405 * i8254 latch check routine: 406 * National Geode (formerly Cyrix MediaGX) has a serious bug in 407 * its built-in i8254-compatible clock module (cs5510 cs5520). 408 * Set the variable 'clock_broken_latch' to indicate it. 409 * 410 * This bug is not present in the cs5530, and the flag 411 * is disabled again in sys/arch/i386/pci/pcib.c if this later 412 * model device is detected. Ideally, this work-around should not 413 * even be in here, it should be in there. XXX 414 */ 415 uint8_t c3; 416 #ifndef XENPV 417 extern int clock_broken_latch; 418 419 switch (ci->ci_signature) { 420 case 0x440: /* Cyrix MediaGX */ 421 case 0x540: /* GXm */ 422 clock_broken_latch = 1; 423 break; 424 } 425 #endif 426 427 /* set up various cyrix registers */ 428 /* 429 * Enable suspend on halt (powersave mode). 430 * When powersave mode is enabled, the TSC stops counting 431 * while the CPU is halted in idle() waiting for an interrupt. 432 * This means we can't use the TSC for interval time in 433 * microtime(9), and thus it is disabled here. 434 * 435 * It still makes a perfectly good cycle counter 436 * for program profiling, so long as you remember you're 437 * counting cycles, and not time. Further, if you don't 438 * mind not using powersave mode, the TSC works just fine, 439 * so this should really be optional. XXX 440 */ 441 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 442 443 /* 444 * Do not disable the TSC on the Geode GX, it's reported to 445 * work fine. 446 */ 447 if (ci->ci_signature != 0x552) 448 ci->ci_feat_val[0] &= ~CPUID_TSC; 449 450 /* enable access to ccr4/ccr5 */ 451 c3 = cyrix_read_reg(0xC3); 452 cyrix_write_reg(0xC3, c3 | 0x10); 453 /* cyrix's workaround for the "coma bug" */ 454 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 455 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 456 cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xffu); 457 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 458 /* disable access to ccr4/ccr5 */ 459 cyrix_write_reg(0xC3, c3); 460 } 461 462 static void 463 cpu_probe_cyrix(struct cpu_info *ci) 464 { 465 466 if (cpu_vendor != CPUVENDOR_CYRIX || 467 CPUID_TO_FAMILY(ci->ci_signature) < 4 || 468 CPUID_TO_FAMILY(ci->ci_signature) > 6) 469 return; 470 471 cpu_probe_cyrix_cmn(ci); 472 } 473 474 static void 475 cpu_probe_winchip(struct cpu_info *ci) 476 { 477 478 if (cpu_vendor != CPUVENDOR_IDT || 479 CPUID_TO_FAMILY(ci->ci_signature) != 5) 480 return; 481 482 /* WinChip C6 */ 483 if (CPUID_TO_MODEL(ci->ci_signature) == 4) 484 ci->ci_feat_val[0] &= ~CPUID_TSC; 485 } 486 487 static void 488 cpu_probe_c3(struct cpu_info *ci) 489 { 490 u_int family, model, stepping, descs[4], lfunc, msr; 491 struct x86_cache_info *cai; 492 493 if (cpu_vendor != CPUVENDOR_IDT || 494 CPUID_TO_FAMILY(ci->ci_signature) < 6) 495 return; 496 497 family = CPUID_TO_FAMILY(ci->ci_signature); 498 model = CPUID_TO_MODEL(ci->ci_signature); 499 stepping = CPUID_TO_STEPPING(ci->ci_signature); 500 501 if (family == 6) { 502 /* 503 * VIA Eden ESP. 504 * 505 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet" 506 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf 507 * 508 * 1. The CMPXCHG8B instruction is provided and always enabled, 509 * however, it appears disabled in the corresponding CPUID 510 * function bit 0 to avoid a bug in an early version of 511 * Windows NT. However, this default can be changed via a 512 * bit in the FCR MSR. 513 */ 514 ci->ci_feat_val[0] |= CPUID_CX8; 515 wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_FCR_CX8_REPORT); 516 517 /* 518 * For reference on VIA Alternate Instructions, see the VIA C3 519 * Processor Alternate Instruction Set Application Note, 2002. 520 * http://www.bitsavers.org/components/viaTechnologies/C3-ais-appnote.pdf 521 * 522 * Disable unsafe ALTINST mode for VIA C3 processors, if necessary. 523 * 524 * This is done for the security reasons, as some CPUs were 525 * found with ALTINST enabled by default. This functionality 526 * has ability to bypass many x86 architecture memory 527 * protections and privilege checks, exposing a possibility 528 * for backdoors and should not be enabled unintentionally. 529 */ 530 if (model > 0x5 && model < 0xA) { 531 int disable_ais = 0; 532 x86_cpuid(0xc0000000, descs); 533 lfunc = descs[0]; 534 /* Check AIS flags first if supported ("Nehemiah"). */ 535 if (lfunc >= 0xc0000001) { 536 x86_cpuid(0xc0000001, descs); 537 lfunc = descs[3]; 538 if ((lfunc & CPUID_VIA_HAS_AIS) 539 && (lfunc & CPUID_VIA_DO_AIS)) { 540 disable_ais = 1; 541 } 542 } else /* Explicitly disable AIS for pre-CX5L CPUs. */ 543 disable_ais = 1; 544 545 if (disable_ais) { 546 msr = rdmsr(MSR_VIA_FCR); 547 wrmsr(MSR_VIA_FCR, msr & ~VIA_FCR_ALTINST_ENABLE); 548 } 549 } 550 } 551 552 if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) { 553 /* VIA Nehemiah or later. */ 554 x86_cpuid(0xc0000000, descs); 555 lfunc = descs[0]; 556 if (lfunc >= 0xc0000001) { /* has ACE, RNG */ 557 int rng_enable = 0, ace_enable = 0; 558 x86_cpuid(0xc0000001, descs); 559 lfunc = descs[3]; 560 ci->ci_feat_val[4] = lfunc; 561 /* Check for and enable RNG */ 562 if (lfunc & CPUID_VIA_HAS_RNG) { 563 if (!(lfunc & CPUID_VIA_DO_RNG)) { 564 rng_enable++; 565 ci->ci_feat_val[4] |= CPUID_VIA_DO_RNG; 566 } 567 } 568 /* Check for and enable ACE (AES-CBC) */ 569 if (lfunc & CPUID_VIA_HAS_ACE) { 570 if (!(lfunc & CPUID_VIA_DO_ACE)) { 571 ace_enable++; 572 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE; 573 } 574 } 575 /* Check for and enable SHA */ 576 if (lfunc & CPUID_VIA_HAS_PHE) { 577 if (!(lfunc & CPUID_VIA_DO_PHE)) { 578 ace_enable++; 579 ci->ci_feat_val[4] |= CPUID_VIA_DO_PHE; 580 } 581 } 582 /* Check for and enable ACE2 (AES-CTR) */ 583 if (lfunc & CPUID_VIA_HAS_ACE2) { 584 if (!(lfunc & CPUID_VIA_DO_ACE2)) { 585 ace_enable++; 586 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE2; 587 } 588 } 589 /* Check for and enable PMM (modmult engine) */ 590 if (lfunc & CPUID_VIA_HAS_PMM) { 591 if (!(lfunc & CPUID_VIA_DO_PMM)) { 592 ace_enable++; 593 ci->ci_feat_val[4] |= CPUID_VIA_DO_PMM; 594 } 595 } 596 597 /* 598 * Actually do the enables. It's a little gross, 599 * but per the PadLock programming guide, "Enabling 600 * PadLock", condition 3, we must enable SSE too or 601 * else the first use of RNG or ACE instructions 602 * will generate a trap. 603 * 604 * We must do this early because of kernel RNG 605 * initialization but it is safe without the full 606 * FPU-detect as all these CPUs have SSE. 607 */ 608 lcr4(rcr4() | CR4_OSFXSR); 609 610 if (rng_enable) { 611 msr = rdmsr(MSR_VIA_RNG); 612 msr |= MSR_VIA_RNG_ENABLE; 613 /* C7 stepping 8 and subsequent CPUs have dual RNG */ 614 if (model > 0xA || (model == 0xA && stepping > 0x7)) { 615 msr |= MSR_VIA_RNG_2NOISE; 616 } 617 wrmsr(MSR_VIA_RNG, msr); 618 } 619 620 if (ace_enable) { 621 msr = rdmsr(MSR_VIA_FCR); 622 wrmsr(MSR_VIA_FCR, msr | VIA_FCR_ACE_ENABLE); 623 } 624 } 625 } 626 627 /* Determine the largest extended function value. */ 628 x86_cpuid(0x80000000, descs); 629 lfunc = descs[0]; 630 631 /* 632 * Determine L1 cache/TLB info. 633 */ 634 if (lfunc < 0x80000005) { 635 /* No L1 cache info available. */ 636 return; 637 } 638 639 x86_cpuid(0x80000005, descs); 640 641 cai = &ci->ci_cinfo[CAI_ITLB]; 642 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 643 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 644 cai->cai_linesize = (4 * 1024); 645 646 cai = &ci->ci_cinfo[CAI_DTLB]; 647 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 648 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 649 cai->cai_linesize = (4 * 1024); 650 651 cai = &ci->ci_cinfo[CAI_DCACHE]; 652 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 653 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 654 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 655 if (family == 6 && model == 9 && stepping == 8) { 656 /* Erratum: stepping 8 reports 4 when it should be 2 */ 657 cai->cai_associativity = 2; 658 } 659 660 cai = &ci->ci_cinfo[CAI_ICACHE]; 661 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 662 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 663 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 664 if (family == 6 && model == 9 && stepping == 8) { 665 /* Erratum: stepping 8 reports 4 when it should be 2 */ 666 cai->cai_associativity = 2; 667 } 668 669 /* 670 * Determine L2 cache/TLB info. 671 */ 672 if (lfunc < 0x80000006) { 673 /* No L2 cache info available. */ 674 return; 675 } 676 677 x86_cpuid(0x80000006, descs); 678 679 cai = &ci->ci_cinfo[CAI_L2CACHE]; 680 if (family > 6 || model >= 9) { 681 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 682 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 683 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 684 } else { 685 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 686 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 687 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 688 } 689 } 690 691 static void 692 cpu_probe_geode(struct cpu_info *ci) 693 { 694 695 if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 || 696 CPUID_TO_FAMILY(ci->ci_signature) != 5) 697 return; 698 699 cpu_probe_cyrix_cmn(ci); 700 cpu_probe_amd_cache(ci); 701 } 702 703 static void 704 cpu_probe_vortex86(struct cpu_info *ci) 705 { 706 #define PCI_MODE1_ADDRESS_REG 0x0cf8 707 #define PCI_MODE1_DATA_REG 0x0cfc 708 #define PCI_MODE1_ENABLE 0x80000000UL 709 710 uint32_t reg, idx; 711 712 if (cpu_vendor != CPUVENDOR_VORTEX86) 713 return; 714 /* 715 * CPU model available from "Customer ID register" in 716 * North Bridge Function 0 PCI space 717 * we can't use pci_conf_read() because the PCI subsystem is not 718 * not initialised early enough 719 */ 720 721 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE | 0x90); 722 reg = inl(PCI_MODE1_DATA_REG); 723 724 if ((reg & 0xf0ffffff) != 0x30504d44) { 725 idx = 0; 726 } else { 727 idx = (reg >> 24) & 0xf; 728 } 729 730 static const char *cpu_vortex86_flavor[] = { 731 "??", "SX", "DX", "MX", "DX2", "MX+", "DX3", "EX", "EX2", 732 }; 733 idx = idx < __arraycount(cpu_vortex86_flavor) ? idx : 0; 734 snprintf(cpu_brand_string, sizeof(cpu_brand_string), "Vortex86%s", 735 cpu_vortex86_flavor[idx]); 736 737 #undef PCI_MODE1_ENABLE 738 #undef PCI_MODE1_ADDRESS_REG 739 #undef PCI_MODE1_DATA_REG 740 } 741 742 static void 743 cpu_probe_fpu_old(struct cpu_info *ci) 744 { 745 #if defined(__i386__) && !defined(XENPV) 746 747 clts(); 748 fninit(); 749 750 /* Check for 'FDIV' bug on the original Pentium */ 751 if (npx586bug1(4195835, 3145727) != 0) 752 /* NB 120+MHz cpus are not affected */ 753 i386_fpu_fdivbug = 1; 754 755 stts(); 756 #endif 757 } 758 759 static void 760 cpu_probe_fpu(struct cpu_info *ci) 761 { 762 u_int descs[4]; 763 int i; 764 765 x86_fpu_save = FPU_SAVE_FSAVE; 766 767 #ifdef i386 768 /* If we have FXSAVE/FXRESTOR, use them. */ 769 if ((ci->ci_feat_val[0] & CPUID_FXSR) == 0) { 770 i386_use_fxsave = 0; 771 cpu_probe_fpu_old(ci); 772 return; 773 } 774 775 i386_use_fxsave = 1; 776 /* 777 * If we have SSE/SSE2, enable XMM exceptions, and 778 * notify userland. 779 */ 780 if (ci->ci_feat_val[0] & CPUID_SSE) 781 i386_has_sse = 1; 782 if (ci->ci_feat_val[0] & CPUID_SSE2) 783 i386_has_sse2 = 1; 784 #else 785 /* 786 * For amd64 i386_use_fxsave, i386_has_sse and i386_has_sse2 are 787 * #defined to 1, because fxsave/sse/sse2 are always present. 788 */ 789 #endif 790 791 x86_fpu_save = FPU_SAVE_FXSAVE; 792 x86_fpu_save_size = sizeof(struct fxsave); 793 794 /* See if XSAVE is supported */ 795 if ((ci->ci_feat_val[1] & CPUID2_XSAVE) == 0) 796 return; 797 798 #ifdef XENPV 799 /* 800 * Xen kernel can disable XSAVE via "no-xsave" option, in that case 801 * the XSAVE/XRSTOR instructions become privileged and trigger 802 * supervisor trap. OSXSAVE flag seems to be reliably set according 803 * to whether XSAVE is actually available. 804 */ 805 if ((ci->ci_feat_val[1] & CPUID2_OSXSAVE) == 0) 806 return; 807 #endif 808 809 x86_fpu_save = FPU_SAVE_XSAVE; 810 811 x86_cpuid2(0x0d, 1, descs); 812 if (descs[0] & CPUID_PES1_XSAVEOPT) 813 x86_fpu_save = FPU_SAVE_XSAVEOPT; 814 815 /* 816 * Get the hardware-supported features with CPUID. 817 */ 818 x86_cpuid2(0x0d, 0, descs); 819 x86_xsave_features = (uint64_t)descs[3] << 32 | descs[0]; 820 821 /* 822 * Turn on XSAVE in CR4 so we can write to XCR0, and write to 823 * XCR0 enable only those features that NetBSD software 824 * supports. 825 * 826 * CR4_OSXSAVE support and and XCR0 access are both allowed 827 * because we tested ci->ci_feat_val[1] & CPUID2_XSAVE above. 828 * 829 * (This is redundant with cpu_init when it runs on the primary 830 * CPU, but it's harmless.) 831 */ 832 lcr4(rcr4() | CR4_OSXSAVE); 833 wrxcr(0, x86_xsave_features & XCR0_FPU); 834 835 /* 836 * Get the size of the save area with those features enabled 837 * with the second CPUID. 838 * 839 * Verify the save area requires no userland ABI change. If 840 * this panic fires, then either 841 * 842 * (a) the CPU is inconsistent with the architectural 843 * documentation of the XSAVE state sizes, or 844 * 845 * (b) NetBSD's requested features XCR0_FPU have been extended 846 * to require more state than will fit in the current value 847 * of MINSIGSTKSZ, which will need to be raised with a 848 * compatibility mechanism so that old programs compiled 849 * with the old value will continue to work (just without 850 * access to the new extended CPU state). 851 */ 852 x86_cpuid2(0x0d, 0, descs); 853 if (descs[1] > x86_fpu_save_size) { 854 if (descs[1] > XSAVE_MAX_BYTES) { 855 panic("XSAVE size >=%"PRIx32 856 " exceeds ABI maximum %zu", 857 descs[1], (size_t)XSAVE_MAX_BYTES); 858 } 859 x86_fpu_save_size = descs[1]; 860 } 861 862 /* Get component offsets and sizes for the save area */ 863 for (i = XSAVE_YMM_Hi128; i < __arraycount(x86_xsave_offsets); i++) { 864 if (x86_xsave_features & __BIT(i)) { 865 x86_cpuid2(0x0d, i, descs); 866 x86_xsave_offsets[i] = descs[1]; 867 x86_xsave_sizes[i] = descs[0]; 868 } 869 } 870 } 871 872 void 873 cpu_probe(struct cpu_info *ci) 874 { 875 u_int descs[4]; 876 int i; 877 uint32_t miscbytes; 878 uint32_t brand[12]; 879 880 if (ci == &cpu_info_primary) { 881 cpu_vendor = i386_nocpuid_cpus[cputype << 1]; 882 cpu_class = i386_nocpuid_cpus[(cputype << 1) + 1]; 883 } 884 885 if (cpuid_level < 0) { 886 /* cpuid instruction not supported */ 887 cpu_probe_fpu_old(ci); 888 return; 889 } 890 891 for (i = 0; i < __arraycount(ci->ci_feat_val); i++) { 892 ci->ci_feat_val[i] = 0; 893 } 894 895 x86_cpuid(0, descs); 896 cpuid_level = descs[0]; 897 ci->ci_max_cpuid = descs[0]; 898 899 ci->ci_vendor[0] = descs[1]; 900 ci->ci_vendor[2] = descs[2]; 901 ci->ci_vendor[1] = descs[3]; 902 ci->ci_vendor[3] = 0; 903 904 if (ci == &cpu_info_primary) { 905 if (memcmp(ci->ci_vendor, "GenuineIntel", 12) == 0) 906 cpu_vendor = CPUVENDOR_INTEL; 907 else if (memcmp(ci->ci_vendor, "AuthenticAMD", 12) == 0) 908 cpu_vendor = CPUVENDOR_AMD; 909 else if (memcmp(ci->ci_vendor, "CyrixInstead", 12) == 0) 910 cpu_vendor = CPUVENDOR_CYRIX; 911 else if (memcmp(ci->ci_vendor, "Geode by NSC", 12) == 0) 912 cpu_vendor = CPUVENDOR_CYRIX; 913 else if (memcmp(ci->ci_vendor, "CentaurHauls", 12) == 0) 914 cpu_vendor = CPUVENDOR_IDT; 915 else if (memcmp(ci->ci_vendor, "GenuineTMx86", 12) == 0) 916 cpu_vendor = CPUVENDOR_TRANSMETA; 917 else if (memcmp(ci->ci_vendor, "Vortex86 SoC", 12) == 0) 918 cpu_vendor = CPUVENDOR_VORTEX86; 919 else 920 cpu_vendor = CPUVENDOR_UNKNOWN; 921 } 922 923 if (cpuid_level >= 1) { 924 x86_cpuid(1, descs); 925 ci->ci_signature = descs[0]; 926 miscbytes = descs[1]; 927 ci->ci_feat_val[1] = descs[2]; 928 ci->ci_feat_val[0] = descs[3]; 929 930 if (ci == &cpu_info_primary) { 931 /* Determine family + class. */ 932 cpu_class = CPUID_TO_FAMILY(ci->ci_signature) 933 + (CPUCLASS_386 - 3); 934 if (cpu_class > CPUCLASS_686) 935 cpu_class = CPUCLASS_686; 936 } 937 938 /* CLFLUSH line size is next 8 bits */ 939 if (ci->ci_feat_val[0] & CPUID_CLFSH) 940 ci->ci_cflush_lsize 941 = __SHIFTOUT(miscbytes, CPUID_CLFLUSH_SIZE) << 3; 942 ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID); 943 } 944 945 /* 946 * Get the basic information from the extended cpuid leafs. 947 * These were first implemented by amd, but most of the values 948 * match with those generated by modern intel cpus. 949 */ 950 x86_cpuid(0x80000000, descs); 951 if (descs[0] >= 0x80000000) 952 ci->ci_max_ext_cpuid = descs[0]; 953 else 954 ci->ci_max_ext_cpuid = 0; 955 956 if (ci->ci_max_ext_cpuid >= 0x80000001) { 957 /* Determine the extended feature flags. */ 958 x86_cpuid(0x80000001, descs); 959 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 960 ci->ci_feat_val[2] = descs[3]; /* %edx */ 961 } 962 963 if (ci->ci_max_ext_cpuid >= 0x80000004) { 964 x86_cpuid(0x80000002, brand); 965 x86_cpuid(0x80000003, brand + 4); 966 x86_cpuid(0x80000004, brand + 8); 967 /* Skip leading spaces on brand */ 968 for (i = 0; i < 48; i++) { 969 if (((char *) brand)[i] != ' ') 970 break; 971 } 972 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 973 } 974 975 /* 976 * Get the structured extended features. 977 */ 978 if (cpuid_level >= 7) { 979 x86_cpuid(7, descs); 980 ci->ci_feat_val[5] = descs[1]; /* %ebx */ 981 ci->ci_feat_val[6] = descs[2]; /* %ecx */ 982 ci->ci_feat_val[7] = descs[3]; /* %edx */ 983 } 984 985 cpu_probe_intel(ci); 986 cpu_probe_amd(ci); 987 cpu_probe_cyrix(ci); 988 cpu_probe_winchip(ci); 989 cpu_probe_c3(ci); 990 cpu_probe_geode(ci); 991 cpu_probe_vortex86(ci); 992 993 if (ci == &cpu_info_primary) { 994 cpu_probe_fpu(ci); 995 } 996 997 #ifndef XENPV 998 x86_cpu_topology(ci); 999 #endif 1000 1001 if (cpu_vendor != CPUVENDOR_AMD && (ci->ci_feat_val[0] & CPUID_TM) && 1002 (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) { 1003 /* Enable thermal monitor 1. */ 1004 wrmsr(MSR_MISC_ENABLE, rdmsr(MSR_MISC_ENABLE) | (1<<3)); 1005 } 1006 1007 ci->ci_feat_val[0] &= ~CPUID_FEAT_BLACKLIST; 1008 if (ci == &cpu_info_primary) { 1009 /* If first. Boot Processor is the cpu_feature reference. */ 1010 for (i = 0; i < __arraycount(cpu_feature); i++) { 1011 cpu_feature[i] = ci->ci_feat_val[i]; 1012 } 1013 identify_hypervisor(); 1014 #ifndef XENPV 1015 /* Early patch of text segment. */ 1016 x86_patch(true); 1017 #endif 1018 1019 /* AES */ 1020 #ifdef __x86_64__ /* not yet implemented on i386 */ 1021 if (cpu_feature[1] & CPUID2_AESNI) 1022 aes_md_init(&aes_ni_impl); 1023 else 1024 #endif 1025 if (cpu_feature[4] & CPUID_VIA_HAS_ACE) 1026 aes_md_init(&aes_via_impl); 1027 else if (i386_has_sse && i386_has_sse2 && 1028 (cpu_feature[1] & CPUID2_SSE3) && 1029 (cpu_feature[1] & CPUID2_SSSE3)) 1030 aes_md_init(&aes_ssse3_impl); 1031 else if (i386_has_sse && i386_has_sse2) 1032 aes_md_init(&aes_sse2_4x32_impl); 1033 1034 /* ChaCha */ 1035 if (i386_has_sse && i386_has_sse2) 1036 chacha_md_init(&chacha_sse2_impl); 1037 } else { 1038 /* 1039 * If not first. Warn about cpu_feature mismatch for 1040 * secondary CPUs. 1041 */ 1042 for (i = 0; i < __arraycount(cpu_feature); i++) { 1043 if (cpu_feature[i] != ci->ci_feat_val[i]) 1044 aprint_error_dev(ci->ci_dev, 1045 "feature mismatch: cpu_feature[%d] is " 1046 "%#x, but CPU reported %#x\n", 1047 i, cpu_feature[i], ci->ci_feat_val[i]); 1048 } 1049 } 1050 } 1051 1052 /* Write what we know about the cpu to the console... */ 1053 void 1054 cpu_identify(struct cpu_info *ci) 1055 { 1056 1057 cpu_setmodel("%s %d86-class", 1058 cpu_vendor_names[cpu_vendor], cpu_class + 3); 1059 if (cpu_brand_string[0] != '\0') { 1060 aprint_normal_dev(ci->ci_dev, "%s", cpu_brand_string); 1061 } else { 1062 aprint_normal_dev(ci->ci_dev, "%s", cpu_getmodel()); 1063 if (ci->ci_data.cpu_cc_freq != 0) 1064 aprint_normal(", %dMHz", 1065 (int)(ci->ci_data.cpu_cc_freq / 1000000)); 1066 } 1067 if (ci->ci_signature != 0) 1068 aprint_normal(", id 0x%x", ci->ci_signature); 1069 aprint_normal("\n"); 1070 aprint_normal_dev(ci->ci_dev, "node %u, package %u, core %u, smt %u\n", 1071 ci->ci_numa_id, ci->ci_package_id, ci->ci_core_id, ci->ci_smt_id); 1072 if (cpu_brand_string[0] == '\0') { 1073 strlcpy(cpu_brand_string, cpu_getmodel(), 1074 sizeof(cpu_brand_string)); 1075 } 1076 if (cpu_class == CPUCLASS_386) { 1077 panic("NetBSD requires an 80486DX or later processor"); 1078 } 1079 if (cputype == CPU_486DLC) { 1080 aprint_error("WARNING: BUGGY CYRIX CACHE\n"); 1081 } 1082 1083 #if !defined(XENPV) || defined(DOM0OPS) /* on Xen PV rdmsr is for Dom0 only */ 1084 if (cpu_vendor == CPUVENDOR_AMD /* check enablement of an */ 1085 && device_unit(ci->ci_dev) == 0 /* AMD feature only once */ 1086 && ((cpu_feature[3] & CPUID_SVM) == CPUID_SVM)) { 1087 uint64_t val; 1088 1089 val = rdmsr(MSR_VMCR); 1090 if (((val & VMCR_SVMED) == VMCR_SVMED) 1091 && ((val & VMCR_LOCK) == VMCR_LOCK)) { 1092 aprint_normal_dev(ci->ci_dev, 1093 "SVM disabled by the BIOS\n"); 1094 } 1095 } 1096 #endif 1097 1098 #ifdef i386 1099 if (i386_fpu_fdivbug == 1) 1100 aprint_normal_dev(ci->ci_dev, 1101 "WARNING: Pentium FDIV bug detected!\n"); 1102 1103 if (cpu_vendor == CPUVENDOR_TRANSMETA) { 1104 u_int descs[4]; 1105 x86_cpuid(0x80860000, descs); 1106 if (descs[0] >= 0x80860007) 1107 /* Create longrun sysctls */ 1108 tmx86_init_longrun(); 1109 } 1110 #endif /* i386 */ 1111 1112 } 1113 1114 /* 1115 * Hypervisor 1116 */ 1117 vm_guest_t vm_guest = VM_GUEST_NO; 1118 1119 struct vm_name_guest { 1120 const char *name; 1121 vm_guest_t guest; 1122 }; 1123 1124 static const struct vm_name_guest vm_bios_vendors[] = { 1125 { "QEMU", VM_GUEST_VM }, /* QEMU */ 1126 { "Plex86", VM_GUEST_VM }, /* Plex86 */ 1127 { "Bochs", VM_GUEST_VM }, /* Bochs */ 1128 { "Xen", VM_GUEST_VM }, /* Xen */ 1129 { "BHYVE", VM_GUEST_VM }, /* bhyve */ 1130 { "Seabios", VM_GUEST_VM }, /* KVM */ 1131 { "innotek GmbH", VM_GUEST_VIRTUALBOX }, /* Oracle VirtualBox */ 1132 { "Generic PVH", VM_GUEST_GENPVH}, /* Generic PVH */ 1133 }; 1134 1135 static const struct vm_name_guest vm_system_products[] = { 1136 { "VMware Virtual Platform", VM_GUEST_VM }, /* VMWare VM */ 1137 { "Virtual Machine", VM_GUEST_VM }, /* Microsoft VirtualPC */ 1138 { "VirtualBox", VM_GUEST_VIRTUALBOX }, /* Sun xVM VirtualBox */ 1139 { "Parallels Virtual Platform", VM_GUEST_VM }, /* Parallels VM */ 1140 { "KVM", VM_GUEST_KVM }, /* KVM */ 1141 { "NVMM", VM_GUEST_NVMM }, /* NVMM */ 1142 }; 1143 1144 void 1145 identify_hypervisor(void) 1146 { 1147 u_int regs[6]; 1148 char hv_vendor[12]; 1149 const char *p; 1150 int i; 1151 1152 switch (vm_guest) { 1153 /* guest type already known, no bios info */ 1154 case VM_GUEST_XENPV: 1155 case VM_GUEST_XENPVH: 1156 /* The following are known from first pass */ 1157 case VM_GUEST_VMWARE: 1158 case VM_GUEST_HV: 1159 case VM_GUEST_XENHVM: 1160 case VM_GUEST_KVM: 1161 case VM_GUEST_NVMM: 1162 return; 1163 default: 1164 break; 1165 } 1166 1167 /* 1168 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1169 * http://lkml.org/lkml/2008/10/1/246 1170 * 1171 * KB1009458: Mechanisms to determine if software is running in 1172 * a VMware virtual machine 1173 * http://kb.vmware.com/kb/1009458 1174 */ 1175 if (ISSET(cpu_feature[1], CPUID2_RAZ)) { 1176 /* 1177 * don't override if vm_guest is unknown but has booted in PVH 1178 * mode, so it can attach to pv(4) in (amd64|i386)_mainbus.c 1179 */ 1180 if (vm_guest != VM_GUEST_GENPVH) 1181 vm_guest = VM_GUEST_VM; 1182 x86_cpuid(0x40000000, regs); 1183 if (regs[0] >= 0x40000000) { 1184 cpu_max_hypervisor_cpuid = regs[0]; 1185 memcpy(&hv_vendor[0], ®s[1], sizeof(*regs)); 1186 memcpy(&hv_vendor[4], ®s[2], sizeof(*regs)); 1187 memcpy(&hv_vendor[8], ®s[3], sizeof(*regs)); 1188 if (memcmp(hv_vendor, "VMwareVMware", 12) == 0) 1189 vm_guest = VM_GUEST_VMWARE; 1190 else if (memcmp(hv_vendor, "Microsoft Hv", 12) == 0) { 1191 vm_guest = VM_GUEST_HV; 1192 #if NHYPERV > 0 1193 hyperv_early_init(); 1194 #endif 1195 } else if (memcmp(hv_vendor, "KVMKVMKVM\0\0\0", 12) == 0) 1196 vm_guest = VM_GUEST_KVM; 1197 else if (memcmp(hv_vendor, "XenVMMXenVMM", 12) == 0) 1198 vm_guest = VM_GUEST_XENHVM; 1199 else if (memcmp(hv_vendor, "___ NVMM ___", 12) == 0) 1200 vm_guest = VM_GUEST_NVMM; 1201 /* FreeBSD bhyve: "bhyve bhyve " */ 1202 /* OpenBSD vmm: "OpenBSDVMM58" */ 1203 } 1204 // VirtualBox returns KVM, so keep going. 1205 if (vm_guest != VM_GUEST_KVM) 1206 return; 1207 } 1208 1209 /* 1210 * Examine SMBIOS strings for older hypervisors. 1211 */ 1212 p = pmf_get_platform("system-serial"); 1213 if (p != NULL) { 1214 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1215 vmt_hvcall(VM_CMD_GET_VERSION, regs); 1216 if (regs[1] == VM_MAGIC) { 1217 vm_guest = VM_GUEST_VMWARE; 1218 return; 1219 } 1220 } 1221 } 1222 p = pmf_get_platform("bios-vendor"); 1223 if (p != NULL) { 1224 for (i = 0; i < __arraycount(vm_bios_vendors); i++) { 1225 if (strcmp(p, vm_bios_vendors[i].name) == 0) { 1226 vm_guest = vm_bios_vendors[i].guest; 1227 return; 1228 } 1229 } 1230 } 1231 p = pmf_get_platform("system-product"); 1232 if (p != NULL) { 1233 for (i = 0; i < __arraycount(vm_system_products); i++) { 1234 if (strcmp(p, vm_system_products[i].name) == 0) { 1235 vm_guest = vm_system_products[i].guest; 1236 return; 1237 } 1238 } 1239 } 1240 } 1241
Indexes created Sat Aug 15 00:25:12 UTC 2026