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      1 /*	$NetBSD: ifpga_pcivar.h,v 1.3 2012/09/07 04:32:03 matt Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2001 ARM Ltd
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the company may not be used to endorse or promote
     16  *    products derived from this software without specific prior written
     17  *    permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _EVBARM_IFPGA_PCIVAR_H_
     33 #define _EVBARM_IFPGA_PCIVAR_H_
     34 
     35 struct ifpga_pci_softc {
     36 	bus_space_tag_t		sc_iot;
     37 	bus_space_handle_t	sc_io_ioh;
     38 	bus_space_handle_t	sc_conf_ioh;
     39 
     40 	bus_space_tag_t		sc_memt;
     41 	bus_space_handle_t	sc_app0_ioh;
     42 	bus_space_handle_t	sc_app1_ioh;
     43 	bus_space_handle_t	sc_reg_ioh;
     44 };
     45 
     46 /* Apperture 0, 256MB normal cycles.  */
     47 #define IFPGA_PCI_APP0_256MB_BASE	0x40000081
     48 #define IFPGA_PCI_APP0_512MB_BASE	0x40000091
     49 #define IFPGA_PCI_APP0_256MB_MAP	0x4006
     50 
     51 /* Apperture 1, 256MB normal cycles, prefetchable.  */
     52 #define IFPGA_PCI_APP1_256MB_BASE	0x50000081
     53 #define IFPGA_PCI_APP1_256MB_MAP	0x5006
     54 
     55 /* Apperture 1, 16MB configuration cycles.  */
     56 #define IFPGA_PCI_APP1_CONF_BASE	0x61000041
     57 #define IFPGA_PCI_APP1_CONF_T0_MAP	0x000a		/* Type 0 cycle */
     58 #define IFPGA_PCI_APP1_CONF_T1_MAP	0x000b		/* Type 1 cycle */
     59 
     60 void	ifpga_pci_conf_interrupt(void *, int, int, int, int, int *);
     61 
     62 #endif /* !_EVBARM_IFPGA_PCIVAR_H_ */
     63