1 /* $NetBSD: igc_evcnt.h,v 1.1 2023/10/04 07:35:27 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2023 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Rin Okuyama <rin (at) iij.ad.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IGC_EVCNT_H_ 33 34 #include <sys/param.h> 35 #include <sys/types.h> 36 #include <sys/atomic.h> 37 #include <sys/evcnt.h> 38 39 #include <dev/pci/igc/if_igc.h> 40 41 #ifndef IGC_EVENT_COUNTERS 42 43 #define IGC_GLOBAL_EVENT(sc, event, delta) ((void)(sc)) 44 #define IGC_DRIVER_EVENT(q, event, delta) ((void)(q)) 45 #define IGC_QUEUE_EVENT(q, event, delta) ((void)(q)) 46 47 #else 48 49 struct igc_counter { 50 int type; 51 const char *name; 52 }; 53 54 /* 55 * Global counters: 56 * 57 * Events outside queue context. 58 */ 59 60 enum igc_global_event { 61 igcge_watchdog, 62 igcge_link, 63 igcge_count, 64 }; 65 66 static const struct igc_counter igc_global_counters[] = { 67 [igcge_watchdog] = { EVCNT_TYPE_MISC, "Watchdog Timeout" }, 68 [igcge_link] = { EVCNT_TYPE_INTR, "Link Event" }, 69 }; 70 71 #define IGC_GLOBAL_COUNTERS __arraycount(igc_global_counters) 72 CTASSERT(IGC_GLOBAL_COUNTERS == igcge_count); 73 74 /* 75 * Driver counters: 76 * 77 * Events in queue context, but summed up over queues. 78 */ 79 80 enum igc_driver_event { 81 igcde_txdma_efbig, 82 igcde_txdma_defrag, 83 igcde_txdma_enomem, 84 igcde_txdma_einval, 85 igcde_txdma_eagain, 86 igcde_txdma_other, 87 igcde_rx_ipcs, 88 igcde_rx_tcpcs, 89 igcde_rx_udpcs, 90 igcde_rx_ipcs_bad, 91 igcde_rx_l4cs_bad, 92 igcde_count, 93 }; 94 95 static const struct igc_counter igc_driver_counters[] = { 96 [igcde_txdma_efbig] = { EVCNT_TYPE_MISC, "Tx DMA Soft Fail EFBIG" }, 97 #ifdef notyet 98 [igcde_txdma_efbig2] = { EVCNT_TYPE_MISC, "Tx DMA Hard Fail EFBIG" }, 99 #endif 100 [igcde_txdma_defrag] = { EVCNT_TYPE_MISC, "Tx DMA Fail Defrag" }, 101 [igcde_txdma_enomem] = { EVCNT_TYPE_MISC, "Tx DMA Fail ENOMEM" }, 102 [igcde_txdma_einval] = { EVCNT_TYPE_MISC, "Tx DMA Fail EINVAL" }, 103 [igcde_txdma_eagain] = { EVCNT_TYPE_MISC, "Tx DMA Fail EAGAIN" }, 104 [igcde_txdma_other] = { EVCNT_TYPE_MISC, "Tx DMA Fail Other" }, 105 [igcde_rx_ipcs] = { EVCNT_TYPE_MISC, "Rx Csum Offload IPv4" }, 106 [igcde_rx_tcpcs] = { EVCNT_TYPE_MISC, "Rx Csum Offload TCP" }, 107 [igcde_rx_udpcs] = { EVCNT_TYPE_MISC, "Rx Csum Offload UDP" }, 108 [igcde_rx_ipcs_bad] = { EVCNT_TYPE_MISC, "Rx Csum Offload IPv4 Bad" }, 109 [igcde_rx_l4cs_bad] = { EVCNT_TYPE_MISC, "Rx Csum Offload L4 Bad" }, 110 }; 111 112 #define IGC_DRIVER_COUNTERS __arraycount(igc_driver_counters) 113 CTASSERT(IGC_DRIVER_COUNTERS == igcde_count); 114 115 /* 116 * Queue counters: 117 * 118 * Per queue events. 119 */ 120 121 enum igc_queue_event { 122 igcqe_irqs, 123 igcqe_handleq, 124 igcqe_req, 125 igcqe_tx_bytes, 126 igcqe_tx_packets, 127 igcqe_tx_pcq_drop, 128 igcqe_tx_no_desc, 129 igcqe_tx_ctx, 130 igcqe_rx_bytes, 131 igcqe_rx_packets, 132 igcqe_rx_no_mbuf, 133 igcqe_rx_discard, 134 igcqe_count, 135 }; 136 137 static const struct igc_counter igc_queue_counters[] = { 138 [igcqe_irqs] = { EVCNT_TYPE_INTR, "Interrupts" }, 139 [igcqe_handleq] = { EVCNT_TYPE_MISC, "Handled in softint" }, 140 [igcqe_req] = { EVCNT_TYPE_MISC, "Requeued in softint" }, 141 [igcqe_tx_bytes] = { EVCNT_TYPE_MISC, "Tx Bytes" }, 142 [igcqe_tx_packets] = { EVCNT_TYPE_MISC, "Tx Packets" }, 143 [igcqe_tx_pcq_drop] = { EVCNT_TYPE_MISC, "Tx pcq Dropped" }, 144 [igcqe_tx_no_desc] = { EVCNT_TYPE_MISC, "Tx No Descriptor Available" }, 145 [igcqe_tx_ctx] = { EVCNT_TYPE_MISC, "Tx Advanced CTX Used" }, 146 [igcqe_rx_bytes] = { EVCNT_TYPE_MISC, "Rx Bytes" }, 147 [igcqe_rx_packets] = { EVCNT_TYPE_MISC, "Rx Packets" }, 148 [igcqe_rx_no_mbuf] = { EVCNT_TYPE_MISC, "Rx No mbuf Available" }, 149 [igcqe_rx_discard] = { EVCNT_TYPE_MISC, "Rx Discarded" }, 150 #ifdef notyet 151 [igcqe_rx_copy] = { EVCNT_TYPE_MISC, "Rx Copied Frames" }, 152 #endif 153 }; 154 155 #define IGC_QUEUE_COUNTERS __arraycount(igc_queue_counters) 156 CTASSERT(IGC_QUEUE_COUNTERS == igcqe_count); 157 158 /* 159 * MAC counters: 160 * 161 * Events obtained from MAC Statistics registers. 162 */ 163 164 static const struct igc_mac_counter { 165 bus_size_t reg; 166 bool is64; 167 const char *name; 168 } igc_mac_counters[] = { 169 /* Interrupts */ 170 { IGC_IAC, false, "Interrupt Assertion" }, 171 172 /* TX errors */ 173 { IGC_COLC, false, "Collision" }, 174 { IGC_SCC, false, "Single Collision" }, 175 { IGC_MCC, false, "Multiple Collision" }, 176 { IGC_ECOL, false, "Excessive Collision" }, 177 { IGC_LATECOL, false, "Late Collision" }, 178 { IGC_TNCRS, false, "Tx-No CRS" }, 179 180 /* RX errors */ 181 { IGC_CRCERRS, false, "CRC Error" }, 182 { IGC_MPC, false, "Missed Packet" }, 183 { IGC_RLEC, false, "Receive Length Error" }, 184 { IGC_LENERRS, false, "Length Errors" }, 185 { IGC_ALGNERRC, false, "Alignment Error" }, 186 { IGC_RERC, false, "Receive Error" }, 187 188 /* flow control events */ 189 { IGC_XOFFTXC, false, "XOFF Tx" }, 190 { IGC_XONTXC, false, "XON Tx" }, 191 { IGC_XOFFRXC, false, "XOFF Rx" }, 192 { IGC_XONRXC, false, "XON Rx" }, 193 { IGC_FCRUC, false, "Flow Control Rx Unsupported" }, 194 195 /* TX statistics */ 196 { IGC_TOTL, true, "Total Octets Tx" }, 197 { IGC_GOTCL, true, "Good Octets Tx" }, 198 { IGC_HGOTCL, true, "Host Good Octets Transmit" }, 199 { IGC_TPT, false, "Total Packets Tx" }, 200 { IGC_GPTC, false, "Good Packets Tx" }, 201 { IGC_MPTC, false, "Multicast Packets Tx" }, 202 { IGC_BPTC, false, "Broadcast Packets Tx" }, 203 { IGC_MGTPTC, false, "Management Packets Tx" }, 204 { IGC_HTDPMC, false, "Host Transmit Discarded by MAC" }, 205 { IGC_DC, false, "Defer" }, 206 { IGC_TSCTC, false, "TCP Segmentation Context Tx" }, 207 { IGC_PTC64, false, "Packets Tx (64 bytes)" }, 208 { IGC_PTC127, false, "Packets Tx (65-127 bytes)" }, 209 { IGC_PTC255, false, "Packets Tx (128-255 bytes)" }, 210 { IGC_PTC511, false, "Packets Tx (256-511 bytes)" }, 211 { IGC_PTC1023, false, "Packets Tx (512-1023 bytes)" }, 212 { IGC_PTC1522, false, "Packets Tx (1024-1522 bytes)" }, 213 214 /* RX statistics */ 215 { IGC_TORL, true, "Total Octets Rx" }, 216 { IGC_GORCL, true, "Good Octets Rx" }, 217 { IGC_HGORCL, true, "Host Good Octets Received" }, 218 { IGC_TPR, false, "Total Packets Rx" }, 219 { IGC_GPRC, false, "Good Packets Rx" }, 220 { IGC_BPRC, false, "Broadcast Packets Rx" }, 221 { IGC_MPRC, false, "Multicast Packets Rx" }, 222 { IGC_MGTPRC, false, "Management Packets Rx" }, 223 { IGC_MGTPDC, false, "Management Packets Dropped" }, 224 { IGC_RNBC, false, "Rx No Buffers" }, 225 { IGC_RUC, false, "Rx Undersize" }, 226 { IGC_RFC, false, "Rx Fragment" }, 227 { IGC_ROC, false, "Rx Oversize" }, 228 { IGC_RJC, false, "Rx Jabber" }, 229 { IGC_RXDMTC, false, "Rx Descriptor Minimum Threshold" }, 230 { IGC_PRC64, false, "Packets Rx (64 bytes)" }, 231 { IGC_PRC127, false, "Packets Rx (65-127 bytes)" }, 232 { IGC_PRC255, false, "Packets Rx (128-255 bytes)" }, 233 { IGC_PRC511, false, "Packets Rx (256-511 bytes)" }, 234 { IGC_PRC1023, false, "Packets Rx (512-1023 bytes)" }, 235 { IGC_PRC1522, false, "Packets Rx (1024-1522 bytes)" }, 236 237 /* EEE */ 238 { IGC_TLPIC, false, "EEE Tx LPI" }, 239 { IGC_RLPIC, false, "EEE Rx LPI" }, 240 }; 241 242 #define IGC_MAC_COUNTERS __arraycount(igc_mac_counters) 243 244 #define IGC_ATOMIC_ADD(p, delta) \ 245 atomic_store_relaxed(p, atomic_load_relaxed(p) + (delta)) 246 #define IGC_ATOMIC_STORE(p, val) \ 247 atomic_store_relaxed(p, val) 248 #define IGC_ATOMIC_LOAD(p) \ 249 atomic_load_relaxed(p) 250 251 #define IGC_GLOBAL_COUNTER(sc, cnt) \ 252 ((sc)->sc_global_evcnts[cnt].ev_count) 253 #define IGC_GLOBAL_COUNTER_ADD(sc, cnt, delta) \ 254 IGC_ATOMIC_ADD(&IGC_GLOBAL_COUNTER(sc, cnt), delta) 255 #define IGC_GLOBAL_COUNTER_STORE(sc, cnt, val) \ 256 IGC_ATOMIC_STORE(&IGC_GLOBAL_COUNTER(sc, cnt), val) 257 258 #define IGC_DRIVER_COUNTER(sc, cnt) \ 259 ((sc)->sc_driver_evcnts[cnt].ev_count) 260 #define IGC_DRIVER_COUNTER_ADD(sc, cnt, delta) \ 261 IGC_ATOMIC_ADD(&IGC_DRIVER_COUNTER(sc, cnt), delta) 262 #define IGC_DRIVER_COUNTER_STORE(sc, cnt, val) \ 263 IGC_ATOMIC_STORE(&IGC_DRIVER_COUNTER(sc, cnt), val) 264 265 #define IGC_QUEUE_DRIVER_COUNTER(q, cnt) \ 266 ((q)->igcq_driver_counters[cnt]) 267 #define IGC_QUEUE_DRIVER_COUNTER_VAL(q, cnt) \ 268 IGC_ATOMIC_LOAD(&IGC_QUEUE_DRIVER_COUNTER(q, cnt)) 269 #define IGC_QUEUE_DRIVER_COUNTER_ADD(q, cnt, delta) \ 270 IGC_ATOMIC_ADD(&IGC_QUEUE_DRIVER_COUNTER(q, cnt), delta) 271 #define IGC_QUEUE_DRIVER_COUNTER_STORE(q, cnt, val) \ 272 IGC_ATOMIC_STORE(&IGC_QUEUE_DRIVER_COUNTER(q, cnt), val) 273 274 #define IGC_QUEUE_COUNTER(q, cnt) \ 275 ((q)->igcq_queue_evcnts[cnt].ev_count) 276 #define IGC_QUEUE_COUNTER_ADD(q, cnt, delta) \ 277 IGC_ATOMIC_ADD(&IGC_QUEUE_COUNTER(q, cnt), delta) 278 #define IGC_QUEUE_COUNTER_STORE(q, cnt, val) \ 279 IGC_ATOMIC_STORE(&IGC_QUEUE_COUNTER(q, cnt), val) 280 281 #define IGC_MAC_COUNTER(sc, cnt) \ 282 ((sc)->sc_mac_evcnts[cnt].ev_count) 283 #define IGC_MAC_COUNTER_ADD(sc, cnt, delta) \ 284 IGC_ATOMIC_ADD(&IGC_MAC_COUNTER(sc, cnt), delta) 285 #define IGC_MAC_COUNTER_STORE(sc, cnt, val) \ 286 IGC_ATOMIC_STORE(&IGC_MAC_COUNTER(sc, cnt), val) 287 288 #define IGC_GLOBAL_EVENT(sc, event, delta) \ 289 IGC_GLOBAL_COUNTER_ADD(sc, igcge_ ## event, delta) 290 #define IGC_DRIVER_EVENT(q, event, delta) \ 291 IGC_QUEUE_DRIVER_COUNTER_ADD(q, igcde_ ## event, delta) 292 #define IGC_QUEUE_EVENT(q, event, delta) \ 293 IGC_QUEUE_COUNTER_ADD(q, igcqe_ ## event, delta) 294 295 #endif /* IGC_EVENT_COUNTERS */ 296 297 #endif /* _IGC_EVCNT_ */ 298
Indexes created Sun Sep 21 14:09:52 GMT 2025