1 /* $NetBSD: igc_hw.h,v 1.2 2023/10/04 07:35:27 rin Exp $ */ 2 /* $OpenBSD: igc_hw.h,v 1.2 2022/05/11 06:14:15 kevlo Exp $ */ 3 /*- 4 * Copyright 2021 Intel Corp 5 * Copyright 2021 Rubicon Communications, LLC (Netgate) 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 * $FreeBSD$ 9 */ 10 11 #ifndef _IGC_HW_H_ 12 #define _IGC_HW_H_ 13 14 #ifdef _KERNEL_OPT 15 #include "vlan.h" 16 #endif 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/bus.h> 21 #include <sys/mbuf.h> 22 #include <sys/kernel.h> 23 #include <sys/kmem.h> 24 #include <sys/socket.h> 25 #include <sys/device.h> 26 #include <sys/endian.h> 27 28 #include <net/bpf.h> 29 #include <net/if.h> 30 #include <net/if_media.h> 31 #include <net/if_ether.h> 32 33 #include <netinet/in.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcidevs.h> 38 39 #include <dev/pci/igc/igc_base.h> 40 #include <dev/pci/igc/igc_defines.h> 41 #include <dev/pci/igc/igc_i225.h> 42 #include <dev/pci/igc/igc_mac.h> 43 #include <dev/pci/igc/igc_nvm.h> 44 #include <dev/pci/igc/igc_phy.h> 45 #include <dev/pci/igc/igc_regs.h> 46 47 struct igc_hw; 48 49 #define IGC_FUNC_1 1 50 51 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0 52 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3 53 54 #define IGC_MAX_NQUEUES 4 55 56 enum igc_mac_type { 57 igc_undefined = 0, 58 igc_i225, 59 igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 60 }; 61 62 enum igc_media_type { 63 igc_media_type_unknown = 0, 64 igc_media_type_copper = 1, 65 igc_num_media_types 66 }; 67 68 enum igc_nvm_type { 69 igc_nvm_unknown = 0, 70 igc_nvm_eeprom_spi, 71 igc_nvm_flash_hw, 72 igc_nvm_invm 73 }; 74 75 enum igc_phy_type { 76 igc_phy_unknown = 0, 77 igc_phy_none, 78 igc_phy_i225 79 }; 80 81 enum igc_bus_type { 82 igc_bus_type_unknown = 0, 83 igc_bus_type_pci, 84 igc_bus_type_pcix, 85 igc_bus_type_pci_express, 86 igc_bus_type_reserved 87 }; 88 89 enum igc_bus_speed { 90 igc_bus_speed_unknown = 0, 91 igc_bus_speed_33, 92 igc_bus_speed_66, 93 igc_bus_speed_100, 94 igc_bus_speed_120, 95 igc_bus_speed_133, 96 igc_bus_speed_2500, 97 igc_bus_speed_5000, 98 igc_bus_speed_reserved 99 }; 100 101 enum igc_bus_width { 102 igc_bus_width_unknown = 0, 103 igc_bus_width_pcie_x1, 104 igc_bus_width_pcie_x2, 105 igc_bus_width_pcie_x4 = 4, 106 igc_bus_width_pcie_x8 = 8, 107 igc_bus_width_32, 108 igc_bus_width_64, 109 igc_bus_width_reserved 110 }; 111 112 enum igc_fc_mode { 113 igc_fc_none = 0, 114 igc_fc_rx_pause, 115 igc_fc_tx_pause, 116 igc_fc_full, 117 igc_fc_default = 0xFF 118 }; 119 120 enum igc_ms_type { 121 igc_ms_hw_default = 0, 122 igc_ms_force_master, 123 igc_ms_force_slave, 124 igc_ms_auto 125 }; 126 127 enum igc_smart_speed { 128 igc_smart_speed_default = 0, 129 igc_smart_speed_on, 130 igc_smart_speed_off 131 }; 132 133 /* Receive Descriptor */ 134 struct igc_rx_desc { 135 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 136 uint16_t length; /* Length of data DMAed into data buffer */ 137 uint16_t csum; /* Packet checksum */ 138 uint8_t status; /* Descriptor status */ 139 uint8_t errors; /* Descriptor errors */ 140 uint16_t special; 141 }; 142 143 /* Receive Descriptor - Extended */ 144 union igc_rx_desc_extended { 145 struct { 146 uint64_t buffer_addr; 147 uint64_t reserved; 148 } read; 149 struct { 150 struct { 151 uint32_t mrq; /* Multiple Rx queues */ 152 union { 153 uint32_t rss; /* RSS hash */ 154 struct { 155 uint16_t ip_id; /* IP id */ 156 uint16_t csum; /* Packet checksum */ 157 } csum_ip; 158 } hi_dword; 159 } lower; 160 struct { 161 uint32_t status_error; /* ext status/error */ 162 uint16_t length; 163 uint16_t vlan; /* VLAN tag */ 164 } upper; 165 } wb; /* writeback */ 166 }; 167 168 /* Transmit Descriptor */ 169 struct igc_tx_desc { 170 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 171 union { 172 uint32_t data; 173 struct { 174 uint16_t length; /* Data buffer length */ 175 uint8_t cso; /* Checksum offset */ 176 uint8_t cmd; /* Descriptor control */ 177 } flags; 178 } lower; 179 union { 180 uint32_t data; 181 struct { 182 uint8_t status; /* Descriptor status */ 183 uint8_t css; /* Checksum start */ 184 uint16_t special; 185 } fields; 186 } upper; 187 }; 188 189 /* Function pointers for the MAC. */ 190 struct igc_mac_operations { 191 int (*init_params)(struct igc_hw *); 192 int (*check_for_link)(struct igc_hw *); 193 void (*clear_hw_cntrs)(struct igc_hw *); 194 void (*clear_vfta)(struct igc_hw *); 195 int (*get_bus_info)(struct igc_hw *); 196 void (*set_lan_id)(struct igc_hw *); 197 int (*get_link_up_info)(struct igc_hw *, uint16_t *, uint16_t *); 198 void (*update_mc_addr_list)(struct igc_hw *, uint8_t *, uint32_t); 199 int (*reset_hw)(struct igc_hw *); 200 int (*init_hw)(struct igc_hw *); 201 int (*setup_link)(struct igc_hw *); 202 int (*setup_physical_interface)(struct igc_hw *); 203 void (*write_vfta)(struct igc_hw *, uint32_t, uint32_t); 204 void (*config_collision_dist)(struct igc_hw *); 205 int (*rar_set)(struct igc_hw *, uint8_t *, uint32_t); 206 int (*read_mac_addr)(struct igc_hw *); 207 int (*validate_mdi_setting)(struct igc_hw *); 208 int (*acquire_swfw_sync)(struct igc_hw *, uint16_t); 209 void (*release_swfw_sync)(struct igc_hw *, uint16_t); 210 }; 211 212 /* When to use various PHY register access functions: 213 * 214 * Func Caller 215 * Function Does Does When to use 216 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 217 * X_reg L,P,A n/a for simple PHY reg accesses 218 * X_reg_locked P,A L for multiple accesses of different regs 219 * on different pages 220 * X_reg_page A L,P for multiple accesses of different regs 221 * on the same page 222 * 223 * Where X=[read|write], L=locking, P=sets page, A=register access 224 * 225 */ 226 struct igc_phy_operations { 227 int (*init_params)(struct igc_hw *); 228 int (*acquire)(struct igc_hw *); 229 int (*check_reset_block)(struct igc_hw *); 230 int (*force_speed_duplex)(struct igc_hw *); 231 int (*get_info)(struct igc_hw *); 232 int (*set_page)(struct igc_hw *, uint16_t); 233 int (*read_reg)(struct igc_hw *, uint32_t, uint16_t *); 234 int (*read_reg_locked)(struct igc_hw *, uint32_t, uint16_t *); 235 int (*read_reg_page)(struct igc_hw *, uint32_t, uint16_t *); 236 void (*release)(struct igc_hw *); 237 int (*reset)(struct igc_hw *); 238 int (*set_d0_lplu_state)(struct igc_hw *, bool); 239 int (*set_d3_lplu_state)(struct igc_hw *, bool); 240 int (*write_reg)(struct igc_hw *, uint32_t, uint16_t); 241 int (*write_reg_locked)(struct igc_hw *, uint32_t, uint16_t); 242 int (*write_reg_page)(struct igc_hw *, uint32_t, uint16_t); 243 void (*power_up)(struct igc_hw *); 244 void (*power_down)(struct igc_hw *); 245 }; 246 247 /* Function pointers for the NVM. */ 248 struct igc_nvm_operations { 249 int (*init_params)(struct igc_hw *); 250 int (*acquire)(struct igc_hw *); 251 int (*read)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 252 void (*release)(struct igc_hw *); 253 void (*reload)(struct igc_hw *); 254 int (*update)(struct igc_hw *); 255 int (*validate)(struct igc_hw *); 256 int (*write)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 257 }; 258 259 struct igc_info { 260 int (*get_invariants)(struct igc_hw *hw); 261 struct igc_mac_operations *mac_ops; 262 const struct igc_phy_operations *phy_ops; 263 struct igc_nvm_operations *nvm_ops; 264 }; 265 266 extern const struct igc_info igc_i225_info; 267 268 struct igc_mac_info { 269 struct igc_mac_operations ops; 270 uint8_t addr[ETHER_ADDR_LEN]; 271 uint8_t perm_addr[ETHER_ADDR_LEN]; 272 273 enum igc_mac_type type; 274 275 uint32_t mc_filter_type; 276 277 uint16_t current_ifs_val; 278 uint16_t ifs_max_val; 279 uint16_t ifs_min_val; 280 uint16_t ifs_ratio; 281 uint16_t ifs_step_size; 282 uint16_t mta_reg_count; 283 uint16_t uta_reg_count; 284 285 /* Maximum size of the MTA register table in all supported adapters */ 286 #define MAX_MTA_REG 128 287 uint32_t mta_shadow[MAX_MTA_REG]; 288 uint16_t rar_entry_count; 289 290 uint8_t forced_speed_duplex; 291 292 bool asf_firmware_present; 293 bool autoneg; 294 bool get_link_status; 295 uint32_t max_frame_size; 296 }; 297 298 struct igc_phy_info { 299 struct igc_phy_operations ops; 300 enum igc_phy_type type; 301 302 enum igc_smart_speed smart_speed; 303 304 uint32_t addr; 305 uint32_t id; 306 uint32_t reset_delay_us; /* in usec */ 307 uint32_t revision; 308 309 enum igc_media_type media_type; 310 311 uint16_t autoneg_advertised; 312 uint16_t autoneg_mask; 313 314 uint8_t mdix; 315 316 bool polarity_correction; 317 bool speed_downgraded; 318 bool autoneg_wait_to_complete; 319 }; 320 321 struct igc_nvm_info { 322 struct igc_nvm_operations ops; 323 enum igc_nvm_type type; 324 325 uint16_t word_size; 326 uint16_t delay_usec; 327 uint16_t address_bits; 328 uint16_t opcode_bits; 329 uint16_t page_size; 330 }; 331 332 struct igc_bus_info { 333 enum igc_bus_type type; 334 enum igc_bus_speed speed; 335 enum igc_bus_width width; 336 337 uint16_t func; 338 uint16_t pci_cmd_word; 339 }; 340 341 struct igc_fc_info { 342 uint32_t high_water; 343 uint32_t low_water; 344 uint16_t pause_time; 345 uint16_t refresh_time; 346 bool send_xon; 347 bool strict_ieee; 348 enum igc_fc_mode current_mode; 349 enum igc_fc_mode requested_mode; 350 }; 351 352 struct igc_dev_spec_i225 { 353 bool eee_disable; 354 bool clear_semaphore_once; 355 uint32_t mtu; 356 }; 357 358 struct igc_hw { 359 void *back; 360 361 bus_addr_t hw_addr; 362 363 struct igc_mac_info mac; 364 struct igc_fc_info fc; 365 struct igc_phy_info phy; 366 struct igc_nvm_info nvm; 367 struct igc_bus_info bus; 368 369 union { 370 struct igc_dev_spec_i225 _i225; 371 } dev_spec; 372 373 uint16_t device_id; 374 }; 375 376 #endif /* _IGC_HW_H_ */ 377
Indexes created Sun Sep 21 14:09:52 GMT 2025