1 /* $NetBSD: igc_phy.c,v 1.2 2023/10/04 07:35:27 rin Exp $ */ 2 /* $OpenBSD: igc_phy.c,v 1.3 2023/02/03 11:31:52 mbuhl Exp $ */ 3 /*- 4 * Copyright 2021 Intel Corp 5 * Copyright 2021 Rubicon Communications, LLC (Netgate) 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <sys/cdefs.h> 10 __KERNEL_RCSID(0, "$NetBSD: igc_phy.c,v 1.2 2023/10/04 07:35:27 rin Exp $"); 11 12 #include <dev/pci/igc/igc_api.h> 13 #include <dev/mii/mii.h> 14 15 /** 16 * igc_init_phy_ops_generic - Initialize PHY function pointers 17 * @hw: pointer to the HW structure 18 * 19 * Setups up the function pointers to no-op functions 20 **/ 21 void 22 igc_init_phy_ops_generic(struct igc_hw *hw) 23 { 24 struct igc_phy_info *phy = &hw->phy; 25 DEBUGFUNC("igc_init_phy_ops_generic"); 26 27 /* Initialize function pointers */ 28 phy->ops.init_params = igc_null_ops_generic; 29 phy->ops.acquire = igc_null_ops_generic; 30 phy->ops.check_reset_block = igc_null_ops_generic; 31 phy->ops.force_speed_duplex = igc_null_ops_generic; 32 phy->ops.get_info = igc_null_ops_generic; 33 phy->ops.set_page = igc_null_set_page; 34 phy->ops.read_reg = igc_null_read_reg; 35 phy->ops.read_reg_locked = igc_null_read_reg; 36 phy->ops.read_reg_page = igc_null_read_reg; 37 phy->ops.release = igc_null_phy_generic; 38 phy->ops.reset = igc_null_ops_generic; 39 phy->ops.set_d0_lplu_state = igc_null_lplu_state; 40 phy->ops.set_d3_lplu_state = igc_null_lplu_state; 41 phy->ops.write_reg = igc_null_write_reg; 42 phy->ops.write_reg_locked = igc_null_write_reg; 43 phy->ops.write_reg_page = igc_null_write_reg; 44 phy->ops.power_up = igc_null_phy_generic; 45 phy->ops.power_down = igc_null_phy_generic; 46 } 47 48 /** 49 * igc_null_set_page - No-op function, return 0 50 * @hw: pointer to the HW structure 51 * @data: dummy variable 52 **/ 53 int 54 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw, uint16_t IGC_UNUSEDARG data) 55 { 56 DEBUGFUNC("igc_null_set_page"); 57 return IGC_SUCCESS; 58 } 59 60 /** 61 * igc_null_read_reg - No-op function, return 0 62 * @hw: pointer to the HW structure 63 * @offset: dummy variable 64 * @data: dummy variable 65 **/ 66 int 67 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw, 68 uint32_t IGC_UNUSEDARG offset, uint16_t IGC_UNUSEDARG *data) 69 { 70 DEBUGFUNC("igc_null_read_reg"); 71 return IGC_SUCCESS; 72 } 73 74 /** 75 * igc_null_phy_generic - No-op function, return void 76 * @hw: pointer to the HW structure 77 **/ 78 void 79 igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw) 80 { 81 DEBUGFUNC("igc_null_phy_generic"); 82 return; 83 } 84 85 /** 86 * igc_null_lplu_state - No-op function, return 0 87 * @hw: pointer to the HW structure 88 * @active: dummy variable 89 **/ 90 int 91 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw, bool IGC_UNUSEDARG active) 92 { 93 DEBUGFUNC("igc_null_lplu_state"); 94 return IGC_SUCCESS; 95 } 96 97 /** 98 * igc_null_write_reg - No-op function, return 0 99 * @hw: pointer to the HW structure 100 * @offset: dummy variable 101 * @data: dummy variable 102 **/ 103 int 104 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw, 105 uint32_t IGC_UNUSEDARG offset, uint16_t IGC_UNUSEDARG data) 106 { 107 DEBUGFUNC("igc_null_write_reg"); 108 return IGC_SUCCESS; 109 } 110 111 /** 112 * igc_check_reset_block_generic - Check if PHY reset is blocked 113 * @hw: pointer to the HW structure 114 * 115 * Read the PHY management control register and check whether a PHY reset 116 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise 117 * return IGC_BLK_PHY_RESET (12). 118 **/ 119 int 120 igc_check_reset_block_generic(struct igc_hw *hw) 121 { 122 uint32_t manc; 123 124 DEBUGFUNC("igc_check_reset_block"); 125 126 manc = IGC_READ_REG(hw, IGC_MANC); 127 128 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ? 129 IGC_BLK_PHY_RESET : IGC_SUCCESS; 130 } 131 132 /** 133 * igc_get_phy_id - Retrieve the PHY ID and revision 134 * @hw: pointer to the HW structure 135 * 136 * Reads the PHY registers and stores the PHY ID and possibly the PHY 137 * revision in the hardware structure. 138 **/ 139 int 140 igc_get_phy_id(struct igc_hw *hw) 141 { 142 struct igc_phy_info *phy = &hw->phy; 143 uint16_t phy_id; 144 int ret_val = IGC_SUCCESS; 145 146 DEBUGFUNC("igc_get_phy_id"); 147 148 if (!phy->ops.read_reg) 149 return IGC_SUCCESS; 150 151 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 152 if (ret_val) 153 return ret_val; 154 155 phy->id = (uint32_t)(phy_id << 16); 156 DELAY(200); 157 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 158 if (ret_val) 159 return ret_val; 160 161 phy->id |= (uint32_t)(phy_id & PHY_REVISION_MASK); 162 phy->revision = (uint32_t)(phy_id & ~PHY_REVISION_MASK); 163 164 return IGC_SUCCESS; 165 } 166 167 /** 168 * igc_read_phy_reg_mdic - Read MDI control register 169 * @hw: pointer to the HW structure 170 * @offset: register offset to be read 171 * @data: pointer to the read data 172 * 173 * Reads the MDI control register in the PHY at offset and stores the 174 * information read to data. 175 **/ 176 int 177 igc_read_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t *data) 178 { 179 struct igc_phy_info *phy = &hw->phy; 180 uint32_t i, mdic = 0; 181 182 DEBUGFUNC("igc_read_phy_reg_mdic"); 183 184 if (offset > MAX_PHY_REG_ADDRESS) { 185 DEBUGOUT1("PHY Address %d is out of range\n", offset); 186 return -IGC_ERR_PARAM; 187 } 188 189 /* Set up Op-code, Phy Address, and register offset in the MDI 190 * Control register. The MAC will take care of interfacing with the 191 * PHY to retrieve the desired data. 192 */ 193 mdic = ((offset << IGC_MDIC_REG_SHIFT) | 194 (phy->addr << IGC_MDIC_PHY_SHIFT) | (IGC_MDIC_OP_READ)); 195 196 IGC_WRITE_REG(hw, IGC_MDIC, mdic); 197 198 /* Poll the ready bit to see if the MDI read completed 199 * Increasing the time out as testing showed failures with 200 * the lower time out 201 */ 202 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) { 203 DELAY(50); 204 mdic = IGC_READ_REG(hw, IGC_MDIC); 205 if (mdic & IGC_MDIC_READY) 206 break; 207 } 208 if (!(mdic & IGC_MDIC_READY)) { 209 DEBUGOUT("MDI Read did not complete\n"); 210 return -IGC_ERR_PHY; 211 } 212 if (mdic & IGC_MDIC_ERROR) { 213 DEBUGOUT("MDI Error\n"); 214 return -IGC_ERR_PHY; 215 } 216 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) { 217 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 218 offset, (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT); 219 return -IGC_ERR_PHY; 220 } 221 *data = (uint16_t)mdic; 222 223 return IGC_SUCCESS; 224 } 225 226 /** 227 * igc_write_phy_reg_mdic - Write MDI control register 228 * @hw: pointer to the HW structure 229 * @offset: register offset to write to 230 * @data: data to write to register at offset 231 * 232 * Writes data to MDI control register in the PHY at offset. 233 **/ 234 int 235 igc_write_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t data) 236 { 237 struct igc_phy_info *phy = &hw->phy; 238 uint32_t i, mdic = 0; 239 240 DEBUGFUNC("igc_write_phy_reg_mdic"); 241 242 if (offset > MAX_PHY_REG_ADDRESS) { 243 DEBUGOUT1("PHY Address %d is out of range\n", offset); 244 return -IGC_ERR_PARAM; 245 } 246 247 /* Set up Op-code, Phy Address, and register offset in the MDI 248 * Control register. The MAC will take care of interfacing with the 249 * PHY to retrieve the desired data. 250 */ 251 mdic = (((uint32_t)data) | (offset << IGC_MDIC_REG_SHIFT) | 252 (phy->addr << IGC_MDIC_PHY_SHIFT) | (IGC_MDIC_OP_WRITE)); 253 254 IGC_WRITE_REG(hw, IGC_MDIC, mdic); 255 256 /* Poll the ready bit to see if the MDI read completed 257 * Increasing the time out as testing showed failures with 258 * the lower time out 259 */ 260 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) { 261 DELAY(50); 262 mdic = IGC_READ_REG(hw, IGC_MDIC); 263 if (mdic & IGC_MDIC_READY) 264 break; 265 } 266 if (!(mdic & IGC_MDIC_READY)) { 267 DEBUGOUT("MDI Write did not complete\n"); 268 return -IGC_ERR_PHY; 269 } 270 if (mdic & IGC_MDIC_ERROR) { 271 DEBUGOUT("MDI Error\n"); 272 return -IGC_ERR_PHY; 273 } 274 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) 275 return -IGC_ERR_PHY; 276 277 return IGC_SUCCESS; 278 } 279 280 /** 281 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation 282 * @hw: pointer to the HW structure 283 * 284 * Reads the MII auto-neg advertisement register and/or the 1000T control 285 * register and if the PHY is already setup for auto-negotiation, then 286 * return successful. Otherwise, setup advertisement and flow control to 287 * the appropriate values for the wanted auto-negotiation. 288 **/ 289 static int 290 igc_phy_setup_autoneg(struct igc_hw *hw) 291 { 292 struct igc_phy_info *phy = &hw->phy; 293 uint16_t mii_autoneg_adv_reg; 294 uint16_t mii_1000t_ctrl_reg = 0; 295 uint16_t aneg_multigbt_an_ctrl = 0; 296 int ret_val; 297 298 DEBUGFUNC("igc_phy_setup_autoneg"); 299 300 phy->autoneg_advertised &= phy->autoneg_mask; 301 302 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 303 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 304 if (ret_val) 305 return ret_val; 306 307 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 308 /* Read the MII 1000Base-T Control Register (Address 9). */ 309 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 310 &mii_1000t_ctrl_reg); 311 if (ret_val) 312 return ret_val; 313 } 314 315 if (phy->autoneg_mask & ADVERTISE_2500_FULL) { 316 /* Read the MULTI GBT AN Control Register - reg 7.32 */ 317 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << 318 MMD_DEVADDR_SHIFT) | ANEG_MULTIGBT_AN_CTRL, 319 &aneg_multigbt_an_ctrl); 320 if (ret_val) 321 return ret_val; 322 } 323 324 /* Need to parse both autoneg_advertised and fc and set up 325 * the appropriate PHY registers. First we will parse for 326 * autoneg_advertised software override. Since we can advertise 327 * a plethora of combinations, we need to check each bit 328 * individually. 329 */ 330 331 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 332 * Advertisement Register (Address 4) and the 1000 mb speed bits in 333 * the 1000Base-T Control Register (Address 9). 334 */ 335 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | NWAY_AR_100TX_HD_CAPS | 336 NWAY_AR_10T_FD_CAPS | NWAY_AR_10T_HD_CAPS); 337 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 338 339 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 340 341 /* Do we want to advertise 10 Mb Half Duplex? */ 342 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 343 DEBUGOUT("Advertise 10mb Half duplex\n"); 344 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 345 } 346 347 /* Do we want to advertise 10 Mb Full Duplex? */ 348 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 349 DEBUGOUT("Advertise 10mb Full duplex\n"); 350 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 351 } 352 353 /* Do we want to advertise 100 Mb Half Duplex? */ 354 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 355 DEBUGOUT("Advertise 100mb Half duplex\n"); 356 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 357 } 358 359 /* Do we want to advertise 100 Mb Full Duplex? */ 360 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 361 DEBUGOUT("Advertise 100mb Full duplex\n"); 362 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 363 } 364 365 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 366 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 367 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 368 369 /* Do we want to advertise 1000 Mb Full Duplex? */ 370 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 371 DEBUGOUT("Advertise 1000mb Full duplex\n"); 372 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 373 } 374 375 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ 376 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) 377 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n"); 378 379 /* Do we want to advertise 2500 Mb Full Duplex? */ 380 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { 381 DEBUGOUT("Advertise 2500mb Full duplex\n"); 382 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS; 383 } else 384 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS; 385 386 /* Check for a software override of the flow control settings, and 387 * setup the PHY advertisement registers accordingly. If 388 * auto-negotiation is enabled, then software will have to set the 389 * "PAUSE" bits to the correct value in the Auto-Negotiation 390 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 391 * negotiation. 392 * 393 * The possible values of the "fc" parameter are: 394 * 0: Flow control is completely disabled 395 * 1: Rx flow control is enabled (we can receive pause frames 396 * but not send pause frames). 397 * 2: Tx flow control is enabled (we can send pause frames 398 * but we do not support receiving pause frames). 399 * 3: Both Rx and Tx flow control (symmetric) are enabled. 400 * other: No software override. The flow control configuration 401 * in the EEPROM is used. 402 */ 403 switch (hw->fc.current_mode) { 404 case igc_fc_none: 405 /* Flow control (Rx & Tx) is completely disabled by a 406 * software over-ride. 407 */ 408 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 409 break; 410 case igc_fc_rx_pause: 411 /* Rx Flow control is enabled, and Tx Flow control is 412 * disabled, by a software over-ride. 413 * 414 * Since there really isn't a way to advertise that we are 415 * capable of Rx Pause ONLY, we will advertise that we 416 * support both symmetric and asymmetric Rx PAUSE. Later 417 * (in igc_config_fc_after_link_up) we will disable the 418 * hw's ability to send PAUSE frames. 419 */ 420 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 421 break; 422 case igc_fc_tx_pause: 423 /* Tx Flow control is enabled, and Rx Flow control is 424 * disabled, by a software over-ride. 425 */ 426 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 427 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 428 break; 429 case igc_fc_full: 430 /* Flow control (both Rx and Tx) is enabled by a software 431 * over-ride. 432 */ 433 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 434 break; 435 default: 436 DEBUGOUT("Flow control param set incorrectly\n"); 437 return -IGC_ERR_CONFIG; 438 } 439 440 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 441 if (ret_val) 442 return ret_val; 443 444 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 445 446 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 447 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 448 mii_1000t_ctrl_reg); 449 450 if (phy->autoneg_mask & ADVERTISE_2500_FULL) 451 ret_val = phy->ops.write_reg(hw, 452 (STANDARD_AN_REG_MASK << MMD_DEVADDR_SHIFT) | 453 ANEG_MULTIGBT_AN_CTRL, aneg_multigbt_an_ctrl); 454 455 return ret_val; 456 } 457 458 /** 459 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link 460 * @hw: pointer to the HW structure 461 * 462 * Performs initial bounds checking on autoneg advertisement parameter, then 463 * configure to advertise the full capability. Setup the PHY to autoneg 464 * and restart the negotiation process between the link partner. If 465 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 466 **/ 467 static int 468 igc_copper_link_autoneg(struct igc_hw *hw) 469 { 470 struct igc_phy_info *phy = &hw->phy; 471 uint16_t phy_ctrl; 472 int ret_val; 473 474 DEBUGFUNC("igc_copper_link_autoneg"); 475 476 /* Perform some bounds checking on the autoneg advertisement 477 * parameter. 478 */ 479 phy->autoneg_advertised &= phy->autoneg_mask; 480 481 /* If autoneg_advertised is zero, we assume it was not defaulted 482 * by the calling code so we set to advertise full capability. 483 */ 484 if (!phy->autoneg_advertised) 485 phy->autoneg_advertised = phy->autoneg_mask; 486 487 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 488 ret_val = igc_phy_setup_autoneg(hw); 489 if (ret_val) { 490 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 491 return ret_val; 492 } 493 DEBUGOUT("Restarting Auto-Neg\n"); 494 495 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 496 * the Auto Neg Restart bit in the PHY control register. 497 */ 498 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 499 if (ret_val) 500 return ret_val; 501 502 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 503 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 504 if (ret_val) 505 return ret_val; 506 507 /* Does the user want to wait for Auto-Neg to complete here, or 508 * check at a later time (for example, callback routine). 509 */ 510 if (phy->autoneg_wait_to_complete) { 511 ret_val = igc_wait_autoneg(hw); 512 if (ret_val) 513 return ret_val; 514 } 515 516 hw->mac.get_link_status = true; 517 518 return ret_val; 519 } 520 521 /** 522 * igc_setup_copper_link_generic - Configure copper link settings 523 * @hw: pointer to the HW structure 524 * 525 * Calls the appropriate function to configure the link for auto-neg or forced 526 * speed and duplex. Then we check for link, once link is established calls 527 * to configure collision distance and flow control are called. If link is 528 * not established, we return -IGC_ERR_PHY (-2). 529 **/ 530 int 531 igc_setup_copper_link_generic(struct igc_hw *hw) 532 { 533 int ret_val; 534 bool link; 535 536 DEBUGFUNC("igc_setup_copper_link_generic"); 537 538 if (hw->mac.autoneg) { 539 /* Setup autoneg and flow control advertisement and perform 540 * autonegotiation. 541 */ 542 ret_val = igc_copper_link_autoneg(hw); 543 if (ret_val) 544 return ret_val; 545 } else { 546 /* PHY will be set to 10H, 10F, 100H or 100F 547 * depending on user settings. 548 */ 549 DEBUGOUT("Forcing Speed and Duplex\n"); 550 ret_val = hw->phy.ops.force_speed_duplex(hw); 551 if (ret_val) { 552 DEBUGOUT("Error Forcing Speed and Duplex\n"); 553 return ret_val; 554 } 555 } 556 557 /* Check link status. Wait up to 100 microseconds for link to become 558 * valid. 559 */ 560 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 561 &link); 562 if (ret_val) 563 return ret_val; 564 565 if (link) { 566 DEBUGOUT("Valid link established!!!\n"); 567 hw->mac.ops.config_collision_dist(hw); 568 ret_val = igc_config_fc_after_link_up_generic(hw); 569 } else 570 DEBUGOUT("Unable to establish link!!!\n"); 571 572 return ret_val; 573 } 574 575 /** 576 * igc_check_downshift_generic - Checks whether a downshift in speed occurred 577 * @hw: pointer to the HW structure 578 * 579 * Success returns 0, Failure returns 1 580 * 581 * A downshift is detected by querying the PHY link health. 582 **/ 583 int 584 igc_check_downshift_generic(struct igc_hw *hw) 585 { 586 struct igc_phy_info *phy = &hw->phy; 587 int ret_val; 588 589 DEBUGFUNC("igc_check_downshift_generic"); 590 591 switch (phy->type) { 592 case igc_phy_i225: 593 default: 594 /* speed downshift not supported */ 595 phy->speed_downgraded = false; 596 return IGC_SUCCESS; 597 } 598 599 return ret_val; 600 } 601 602 /** 603 * igc_wait_autoneg - Wait for auto-neg completion 604 * @hw: pointer to the HW structure 605 * 606 * Waits for auto-negotiation to complete or for the auto-negotiation time 607 * limit to expire, which ever happens first. 608 **/ 609 int 610 igc_wait_autoneg(struct igc_hw *hw) 611 { 612 uint16_t i, phy_status; 613 int ret_val = IGC_SUCCESS; 614 615 DEBUGFUNC("igc_wait_autoneg"); 616 617 if (!hw->phy.ops.read_reg) 618 return IGC_SUCCESS; 619 620 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 621 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 622 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status); 623 if (ret_val) 624 break; 625 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status); 626 if (ret_val) 627 break; 628 if (phy_status & MII_SR_AUTONEG_COMPLETE) 629 break; 630 msec_delay(100); 631 } 632 633 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 634 * has completed. 635 */ 636 return ret_val; 637 } 638 639 /** 640 * igc_phy_has_link_generic - Polls PHY for link 641 * @hw: pointer to the HW structure 642 * @iterations: number of times to poll for link 643 * @usec_interval: delay between polling attempts 644 * @success: pointer to whether polling was successful or not 645 * 646 * Polls the PHY status register for link, 'iterations' number of times. 647 **/ 648 int 649 igc_phy_has_link_generic(struct igc_hw *hw, uint32_t iterations, 650 uint32_t usec_interval, bool *success) 651 { 652 uint16_t i, phy_status; 653 int ret_val = IGC_SUCCESS; 654 655 DEBUGFUNC("igc_phy_has_link_generic"); 656 657 if (!hw->phy.ops.read_reg) 658 return IGC_SUCCESS; 659 660 for (i = 0; i < iterations; i++) { 661 /* Some PHYs require the MII_BMSR register to be read 662 * twice due to the link bit being sticky. No harm doing 663 * it across the board. 664 */ 665 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status); 666 if (ret_val) { 667 /* If the first read fails, another entity may have 668 * ownership of the resources, wait and try again to 669 * see if they have relinquished the resources yet. 670 */ 671 if (usec_interval >= 1000) 672 msec_delay(usec_interval/1000); 673 else 674 DELAY(usec_interval); 675 } 676 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status); 677 if (ret_val) 678 break; 679 if (phy_status & MII_SR_LINK_STATUS) 680 break; 681 if (usec_interval >= 1000) 682 msec_delay(usec_interval/1000); 683 else 684 DELAY(usec_interval); 685 } 686 687 *success = (i < iterations); 688 689 return ret_val; 690 } 691 692 /** 693 * igc_phy_hw_reset_generic - PHY hardware reset 694 * @hw: pointer to the HW structure 695 * 696 * Verify the reset block is not blocking us from resetting. Acquire 697 * semaphore (if necessary) and read/set/write the device control reset 698 * bit in the PHY. Wait the appropriate delay time for the device to 699 * reset and release the semaphore (if necessary). 700 **/ 701 int 702 igc_phy_hw_reset_generic(struct igc_hw *hw) 703 { 704 struct igc_phy_info *phy = &hw->phy; 705 uint32_t ctrl, timeout = 10000, phpm = 0; 706 int ret_val; 707 708 DEBUGFUNC("igc_phy_hw_reset_generic"); 709 710 if (phy->ops.check_reset_block) { 711 ret_val = phy->ops.check_reset_block(hw); 712 if (ret_val) 713 return IGC_SUCCESS; 714 } 715 716 ret_val = phy->ops.acquire(hw); 717 if (ret_val) 718 return ret_val; 719 720 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); 721 722 ctrl = IGC_READ_REG(hw, IGC_CTRL); 723 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); 724 IGC_WRITE_FLUSH(hw); 725 726 DELAY(phy->reset_delay_us); 727 728 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 729 IGC_WRITE_FLUSH(hw); 730 731 DELAY(150); 732 733 do { 734 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); 735 timeout--; 736 DELAY(1); 737 } while (!(phpm & IGC_I225_PHPM_RST_COMPL) && timeout); 738 739 if (!timeout) 740 DEBUGOUT("Timeout expired after a phy reset\n"); 741 742 phy->ops.release(hw); 743 744 return ret_val; 745 } 746 747 /** 748 * igc_power_up_phy_copper - Restore copper link in case of PHY power down 749 * @hw: pointer to the HW structure 750 * 751 * In the case of a PHY power down to save power, or to turn off link during a 752 * driver unload, or wake on lan is not enabled, restore the link to previous 753 * settings. 754 **/ 755 void 756 igc_power_up_phy_copper(struct igc_hw *hw) 757 { 758 uint16_t mii_reg = 0; 759 760 /* The PHY will retain its settings across a power down/up cycle */ 761 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 762 mii_reg &= ~MII_CR_POWER_DOWN; 763 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 764 DELAY(300); 765 } 766 767 /** 768 * igc_power_down_phy_copper - Restore copper link in case of PHY power down 769 * @hw: pointer to the HW structure 770 * 771 * In the case of a PHY power down to save power, or to turn off link during a 772 * driver unload, or wake on lan is not enabled, restore the link to previous 773 * settings. 774 **/ 775 void 776 igc_power_down_phy_copper(struct igc_hw *hw) 777 { 778 uint16_t mii_reg = 0; 779 780 /* The PHY will retain its settings across a power down/up cycle */ 781 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 782 mii_reg |= MII_CR_POWER_DOWN; 783 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 784 msec_delay(1); 785 } 786 787 /** 788 * igc_write_phy_reg_gpy - Write GPY PHY register 789 * @hw: pointer to the HW structure 790 * @offset: register offset to write to 791 * @data: data to write at register offset 792 * 793 * Acquires semaphore, if necessary, then writes the data to PHY register 794 * at the offset. Release any acquired semaphores before exiting. 795 **/ 796 int 797 igc_write_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t data) 798 { 799 uint8_t dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 800 int ret_val; 801 802 DEBUGFUNC("igc_write_phy_reg_gpy"); 803 804 offset = offset & GPY_REG_MASK; 805 806 if (!dev_addr) { 807 ret_val = hw->phy.ops.acquire(hw); 808 if (ret_val) 809 return ret_val; 810 ret_val = igc_write_phy_reg_mdic(hw, offset, data); 811 if (ret_val) 812 return ret_val; 813 hw->phy.ops.release(hw); 814 } else { 815 ret_val = igc_write_xmdio_reg(hw, (uint16_t)offset, dev_addr, 816 data); 817 } 818 819 return ret_val; 820 } 821 822 /** 823 * igc_read_phy_reg_gpy - Read GPY PHY register 824 * @hw: pointer to the HW structure 825 * @offset: lower half is register offset to read to 826 * upper half is MMD to use. 827 * @data: data to read at register offset 828 * 829 * Acquires semaphore, if necessary, then reads the data in the PHY register 830 * at the offset. Release any acquired semaphores before exiting. 831 **/ 832 int 833 igc_read_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t *data) 834 { 835 uint8_t dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 836 int ret_val; 837 838 DEBUGFUNC("igc_read_phy_reg_gpy"); 839 840 offset = offset & GPY_REG_MASK; 841 842 if (!dev_addr) { 843 ret_val = hw->phy.ops.acquire(hw); 844 if (ret_val) 845 return ret_val; 846 ret_val = igc_read_phy_reg_mdic(hw, offset, data); 847 if (ret_val) 848 return ret_val; 849 hw->phy.ops.release(hw); 850 } else { 851 ret_val = igc_read_xmdio_reg(hw, (uint16_t)offset, dev_addr, 852 data); 853 } 854 855 return ret_val; 856 } 857 858 /** 859 * __igc_access_xmdio_reg - Read/write XMDIO register 860 * @hw: pointer to the HW structure 861 * @address: XMDIO address to program 862 * @dev_addr: device address to program 863 * @data: pointer to value to read/write from/to the XMDIO address 864 * @read: boolean flag to indicate read or write 865 **/ 866 static int 867 __igc_access_xmdio_reg(struct igc_hw *hw, uint16_t address, uint8_t dev_addr, 868 uint16_t *data, bool read) 869 { 870 int ret_val; 871 872 DEBUGFUNC("__igc_access_xmdio_reg"); 873 874 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); 875 if (ret_val) 876 return ret_val; 877 878 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); 879 if (ret_val) 880 return ret_val; 881 882 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | 883 dev_addr); 884 if (ret_val) 885 return ret_val; 886 887 if (read) 888 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); 889 else 890 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); 891 if (ret_val) 892 return ret_val; 893 894 /* Recalibrate the device back to 0 */ 895 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); 896 if (ret_val) 897 return ret_val; 898 899 return ret_val; 900 } 901 902 /** 903 * igc_read_xmdio_reg - Read XMDIO register 904 * @hw: pointer to the HW structure 905 * @addr: XMDIO address to program 906 * @dev_addr: device address to program 907 * @data: value to be read from the EMI address 908 **/ 909 int 910 igc_read_xmdio_reg(struct igc_hw *hw, uint16_t addr, uint8_t dev_addr, 911 uint16_t *data) 912 { 913 DEBUGFUNC("igc_read_xmdio_reg"); 914 915 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); 916 } 917 918 /** 919 * igc_write_xmdio_reg - Write XMDIO register 920 * @hw: pointer to the HW structure 921 * @addr: XMDIO address to program 922 * @dev_addr: device address to program 923 * @data: value to be written to the XMDIO address 924 **/ 925 int 926 igc_write_xmdio_reg(struct igc_hw *hw, uint16_t addr, uint8_t dev_addr, 927 uint16_t data) 928 { 929 DEBUGFUNC("igc_write_xmdio_reg"); 930 931 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); 932 } 933
Indexes created Sun Sep 21 14:09:52 GMT 2025