1 /* $NetBSD: if_igc.h,v 1.3 2024/06/27 07:31:41 rin Exp $ */ 2 /* $OpenBSD: if_igc.h,v 1.2 2022/01/09 05:42:50 jsg Exp $ */ 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * Copyright (c) 2016 Nicole Graziano <nicole (at) nextbsd.org> 7 * All rights reserved. 8 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _IGC_H_ 35 #define _IGC_H_ 36 37 #ifdef _KERNEL_OPT 38 #include "opt_if_igc.h" 39 #endif 40 41 #include <sys/types.h> 42 #include <sys/atomic.h> 43 #include <sys/pcq.h> 44 #include <sys/workqueue.h> 45 46 #include <dev/pci/igc/igc_api.h> 47 #include <dev/pci/igc/igc_i225.h> 48 49 #ifdef __HAVE_ATOMIC64_LOADSTORE 50 #define IGC_EVENT_COUNTERS 51 #endif 52 53 /* 54 * IGC_MAX_TXD: Maximum number of Transmit Descriptors 55 * Valid Range: 128-4096 56 * Default Value: 1024 57 * This value is the number of transmit descriptors allocated by the driver. 58 * Increasing this value allows the driver to queue more transmits. Each 59 * descriptor is 16 bytes. 60 * Since TDLEN should be multiple of 128bytes, the number of transmit 61 * descriptors should meet the following condition. 62 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 63 */ 64 #define IGC_MIN_TXD 128 65 #define IGC_MAX_TXD 4096 66 #define IGC_DEFAULT_TXD 1024 67 #define IGC_DEFAULT_MULTI_TXD 4096 68 #define IGC_MAX_TXD 4096 69 70 /* 71 * IGC_MAX_RXD - Maximum number of receive Descriptors 72 * Valid Range: 128-4096 73 * Default Value: 1024 74 * This value is the number of receive descriptors allocated by the driver. 75 * Increasing this value allows the driver to buffer more incoming packets. 76 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 77 * descriptor. The maximum MTU size is 16110. 78 * Since TDLEN should be multiple of 128bytes, the number of transmit 79 * descriptors should meet the following condition. 80 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 81 */ 82 #define IGC_MIN_RXD 128 83 #define IGC_MAX_RXD 4096 84 #define IGC_DEFAULT_RXD 1024 85 #define IGC_DEFAULT_MULTI_RXD 4096 86 #define IGC_MAX_RXD 4096 87 88 /* 89 * IGC_TIDV_VAL - Transmit Interrupt Delay Value 90 * Valid Range: 0-65535 (0=off) 91 * Default Value: 64 92 * This value delays the generation of transmit interrupts in units of 93 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 94 * efficiency if properly tuned for specific network traffic. If the 95 * system is reporting dropped transmits, this value may be set too high 96 * causing the driver to run out of available transmit descriptors. 97 */ 98 #define IGC_TIDV_VAL 64 99 100 /* 101 * IGC_TADV_VAL - Transmit Absolute Interrupt Delay Value 102 * Valid Range: 0-65535 (0=off) 103 * Default Value: 64 104 * This value, in units of 1.024 microseconds, limits the delay in which a 105 * transmit interrupt is generated. Useful only if IGC_TIDV is non-zero, 106 * this value ensures that an interrupt is generated after the initial 107 * packet is sent on the wire within the set amount of time. Proper tuning, 108 * along with IGC_TIDV_VAL, may improve traffic throughput in specific 109 * network conditions. 110 */ 111 #define IGC_TADV_VAL 64 112 113 /* 114 * IGC_RDTR_VAL - Receive Interrupt Delay Timer (Packet Timer) 115 * Valid Range: 0-65535 (0=off) 116 * Default Value: 0 117 * This value delays the generation of receive interrupts in units of 1.024 118 * microseconds. Receive interrupt reduction can improve CPU efficiency if 119 * properly tuned for specific network traffic. Increasing this value adds 120 * extra latency to frame reception and can end up decreasing the throughput 121 * of TCP traffic. If the system is reporting dropped receives, this value 122 * may be set too high, causing the driver to run out of available receive 123 * descriptors. 124 * 125 * CAUTION: When setting IGC_RDTR to a value other than 0, adapters 126 * may hang (stop transmitting) under certain network conditions. 127 * If this occurs a WATCHDOG message is logged in the system 128 * event log. In addition, the controller is automatically reset, 129 * restoring the network connection. To eliminate the potential 130 * for the hang ensure that IGC_RDTR is set to 0. 131 */ 132 #define IGC_RDTR_VAL 0 133 134 /* 135 * Receive Interrupt Absolute Delay Timer 136 * Valid Range: 0-65535 (0=off) 137 * Default Value: 64 138 * This value, in units of 1.024 microseconds, limits the delay in which a 139 * receive interrupt is generated. Useful only if IGC_RDTR is non-zero, 140 * this value ensures that an interrupt is generated after the initial 141 * packet is received within the set amount of time. Proper tuning, 142 * along with IGC_RDTR, may improve traffic throughput in specific network 143 * conditions. 144 */ 145 #define IGC_RADV_VAL 64 146 147 /* 148 * This parameter controls whether or not autonegotiation is enabled. 149 * 0 - Disable autonegotiation 150 * 1 - Enable autonegotiation 151 */ 152 #define DO_AUTO_NEG true 153 154 #define AUTONEG_ADV_DEFAULT \ 155 (ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 156 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 157 158 #define AUTO_ALL_MODES 0 159 160 /* 161 * Miscellaneous constants 162 */ 163 #define MAX_NUM_MULTICAST_ADDRESSES 128 164 #define IGC_FC_PAUSE_TIME 0x0680 165 166 #define IGC_TXPBSIZE 20408 167 #define IGC_PKTTYPE_MASK 0x0000FFF0 168 #define IGC_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 169 170 #define IGC_RX_PTHRESH 8 171 #define IGC_RX_HTHRESH 8 172 #define IGC_RX_WTHRESH 4 173 174 #define IGC_TX_PTHRESH 8 175 #define IGC_TX_HTHRESH 1 176 177 /* 178 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 179 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 180 * also optimize cache line size effect. H/W supports up to cache line size 128. 181 */ 182 #define IGC_DBA_ALIGN 128 183 184 /* 185 * This parameter controls the duration of transmit watchdog timer. 186 */ 187 #define IGC_TX_TIMEOUT 5 /* set to 5 seconds */ 188 189 #define IGC_PCIREG PCI_MAPREG_START 190 191 #define IGC_MAX_VECTORS 8 192 193 /* Enable/disable debugging statements in shared code */ 194 #define DBG 0 195 196 #define DEBUGOUT(...) \ 197 do { if (DBG) printf(__VA_ARGS__); } while (0) 198 #define DEBUGOUT1(...) DEBUGOUT(__VA_ARGS__) 199 #define DEBUGOUT2(...) DEBUGOUT(__VA_ARGS__) 200 #define DEBUGOUT3(...) DEBUGOUT(__VA_ARGS__) 201 #define DEBUGOUT7(...) DEBUGOUT(__VA_ARGS__) 202 #define DEBUGFUNC(F) DEBUGOUT(F "\n") 203 204 /* Compatibility glue. */ 205 #define msec_delay(x) DELAY(1000 * (x)) 206 207 #define IGC_MAX_SCATTER 40 208 #define IGC_TSO_SIZE 65535 209 210 #define MAX_INTS_PER_SEC 8000 211 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 212 213 #define IGC_MAX_INTRS (IGC_MAX_NQUEUES + 1) 214 215 /* Forward declaration. */ 216 struct igc_hw; 217 218 struct igc_osdep { 219 bus_dma_tag_t os_dmat; 220 bus_space_tag_t os_memt; 221 bus_space_handle_t os_memh; 222 223 bus_size_t os_memsize; 224 bus_addr_t os_membase; 225 226 void *os_sc; 227 struct pci_attach_args os_pa; 228 }; 229 230 231 struct igc_tx_buf { 232 uint32_t eop_index; 233 struct mbuf *m_head; 234 bus_dmamap_t map; 235 }; 236 237 struct igc_rx_buf { 238 struct mbuf *buf; 239 struct mbuf *fmp; /* First mbuf pointers. */ 240 bus_dmamap_t map; 241 }; 242 243 /* 244 * Bus dma allocation structure used by igc_dma_malloc and igc_dma_free. 245 */ 246 struct igc_dma_alloc { 247 void *dma_vaddr; 248 bus_dma_tag_t dma_tag; 249 bus_dmamap_t dma_map; 250 bus_dma_segment_t dma_seg; 251 bus_size_t dma_size; 252 int dma_nseg; 253 }; 254 255 /* 256 * Driver queue struct: this is the interrupt container 257 * for the associated tx and rx ring. 258 */ 259 struct igc_queue { 260 struct igc_softc *sc; 261 uint32_t msix; 262 uint32_t eims; 263 uint32_t eitr_setting; 264 pci_intr_handle_t ih; 265 void *tag; 266 struct tx_ring *txr; 267 struct rx_ring *rxr; 268 269 void *igcq_si; 270 bool igcq_workqueue; 271 struct work igcq_wq_cookie; 272 273 #ifdef IGC_EVENT_COUNTERS 274 uint64_t *igcq_driver_counters; 275 276 struct evcnt *igcq_queue_evcnts; 277 char igcq_queue_evname[EVCNT_STRING_MAX]; 278 #endif 279 }; 280 281 /* 282 * The transmit ring, one per tx queue. 283 */ 284 struct tx_ring { 285 struct igc_softc *sc; 286 struct ifqueue *ifq; 287 uint32_t me; 288 uint32_t watchdog_timer; 289 union igc_adv_tx_desc *tx_base; 290 struct igc_tx_buf *tx_buffers; 291 struct igc_dma_alloc txdma; 292 uint32_t next_avail_desc; 293 uint32_t next_to_clean; 294 bus_dma_tag_t txtag; 295 296 pcq_t *txr_interq; 297 298 kmutex_t txr_lock; 299 300 struct igc_queue *txr_igcq; 301 }; 302 303 /* 304 * The Receive ring, one per rx queue. 305 */ 306 struct rx_ring { 307 struct igc_softc *sc; 308 uint32_t me; 309 union igc_adv_rx_desc *rx_base; 310 struct igc_rx_buf *rx_buffers; 311 struct igc_dma_alloc rxdma; 312 uint32_t last_desc_filled; 313 uint32_t next_to_check; 314 #if IF_RXR 315 struct if_rxring rx_ring; 316 #endif 317 318 kmutex_t rxr_lock; 319 320 struct igc_queue *rxr_igcq; 321 }; 322 323 /* Our adapter structure. */ 324 struct igc_softc { 325 device_t sc_dev; 326 struct ethercom sc_ec; 327 struct ifmedia media; 328 #if 1 329 pci_intr_type_t sc_intr_type; 330 int sc_nintrs; 331 pci_intr_handle_t *sc_intrs; 332 void *sc_ihs[IGC_MAX_INTRS]; 333 #else 334 struct intrmap *sc_intrmap; 335 #endif 336 337 struct igc_osdep osdep; 338 struct igc_hw hw; 339 340 uint16_t sc_if_flags; 341 uint16_t fc; 342 uint16_t link_active; 343 uint16_t link_speed; 344 uint16_t link_duplex; 345 uint32_t dmac; 346 347 int num_tx_desc; 348 int num_rx_desc; 349 350 uint32_t max_frame_size; 351 uint32_t rx_mbuf_sz; 352 uint32_t linkvec; 353 uint32_t msix_linkmask; 354 uint32_t msix_queuesmask; 355 356 struct if_percpuq *sc_ipq; 357 unsigned int sc_nqueues; 358 struct igc_queue *queues; 359 bool sc_txrx_workqueue; 360 struct workqueue *sc_queue_wq; 361 362 u_int sc_rx_intr_process_limit; 363 u_int sc_tx_intr_process_limit; 364 u_int sc_rx_process_limit; 365 u_int sc_tx_process_limit; 366 367 struct tx_ring *tx_rings; 368 struct rx_ring *rx_rings; 369 370 /* Multicast array memory */ 371 #define IGC_MTA_LEN (ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES) 372 uint8_t *mta; 373 374 kmutex_t sc_core_lock; 375 376 callout_t sc_tick_ch; 377 bool sc_core_stopping; 378 379 #ifdef IGC_EVENT_COUNTERS 380 struct evcnt *sc_global_evcnts; 381 382 struct evcnt *sc_driver_evcnts; 383 384 struct evcnt *sc_mac_evcnts; 385 char sc_mac_evname[EVCNT_STRING_MAX]; 386 #endif 387 }; 388 389 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 390 391 /* Register READ/WRITE macros */ 392 #define IGC_WRITE_FLUSH(a) IGC_READ_REG(a, IGC_STATUS) 393 #define IGC_READ_REG(a, reg) \ 394 bus_space_read_4(((struct igc_osdep *)(a)->back)->os_memt, \ 395 ((struct igc_osdep *)(a)->back)->os_memh, reg) 396 #define IGC_WRITE_REG(a, reg, value) \ 397 bus_space_write_4(((struct igc_osdep *)(a)->back)->os_memt, \ 398 ((struct igc_osdep *)(a)->back)->os_memh, reg, value) 399 #define IGC_READ_REG_ARRAY(a, reg, off) \ 400 bus_space_read_4(((struct igc_osdep *)(a)->back)->os_memt, \ 401 ((struct igc_osdep *)(a)->back)->os_memh, (reg + ((off) << 2))) 402 #define IGC_WRITE_REG_ARRAY(a, reg, off, value) \ 403 bus_space_write_4(((struct igc_osdep *)(a)->back)->os_memt, \ 404 ((struct igc_osdep *)(a)->back)->os_memh, \ 405 (reg + ((off) << 2)),value) 406 407 #endif /* _IGC_H_ */ 408
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