1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 /* 30 * Authors: 31 * Kevin E. Martin <martin (at) xfree86.org> 32 * Rickard E. Faith <faith (at) valinux.com> 33 * Alan Hourihane <alanh (at) fairlite.demon.co.uk> 34 * 35 */ 36 37 #ifndef _RADEON_H_ 38 #define _RADEON_H_ 39 40 #include <stdlib.h> /* For abs() */ 41 #include <unistd.h> /* For usleep() */ 42 #include <sys/time.h> /* For gettimeofday() */ 43 44 #include "config.h" 45 46 #include "xf86str.h" 47 #include "compiler.h" 48 #include "xf86fbman.h" 49 50 /* PCI support */ 51 #include "xf86Pci.h" 52 53 #ifdef USE_EXA 54 #include "exa.h" 55 #endif 56 #ifdef USE_XAA 57 #include "xaa.h" 58 #endif 59 60 /* Exa and Cursor Support */ 61 #include "vbe.h" 62 #include "xf86Cursor.h" 63 64 /* DDC support */ 65 #include "xf86DDC.h" 66 67 /* Xv support */ 68 #include "xf86xv.h" 69 70 #include "radeon_probe.h" 71 #include "radeon_tv.h" 72 73 /* DRI support */ 74 #ifdef XF86DRI 75 #define _XF86DRI_SERVER_ 76 #include "dri.h" 77 #include "GL/glxint.h" 78 #include "xf86drm.h" 79 #include "radeon_drm.h" 80 81 #ifdef DAMAGE 82 #include "damage.h" 83 #include "globals.h" 84 #endif 85 #endif 86 87 #include "xf86Crtc.h" 88 #include "X11/Xatom.h" 89 90 #ifdef XF86DRM_MODE 91 #include "radeon_bo.h" 92 #include "radeon_cs.h" 93 #include "radeon_dri2.h" 94 #include "drmmode_display.h" 95 #include "radeon_surface.h" 96 #else 97 #include "radeon_dummy_bufmgr.h" 98 #endif 99 100 /* Render support */ 101 #ifdef RENDER 102 #include "picturestr.h" 103 #endif 104 105 #include "compat-api.h" 106 107 #include "simple_list.h" 108 #include "atipcirename.h" 109 110 #ifndef MAX 111 #define MAX(a,b) ((a)>(b)?(a):(b)) 112 #endif 113 #ifndef MIN 114 #define MIN(a,b) ((a)>(b)?(b):(a)) 115 #endif 116 117 #if HAVE_BYTESWAP_H 118 #include <byteswap.h> 119 #elif defined(USE_SYS_ENDIAN_H) 120 #include <sys/endian.h> 121 #else 122 #define bswap_16(value) \ 123 ((((value) & 0xff) << 8) | ((value) >> 8)) 124 125 #define bswap_32(value) \ 126 (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ 127 (uint32_t)bswap_16((uint16_t)((value) >> 16))) 128 129 #define bswap_64(value) \ 130 (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ 131 << 32) | \ 132 (uint64_t)bswap_32((uint32_t)((value) >> 32))) 133 #endif 134 135 #if X_BYTE_ORDER == X_BIG_ENDIAN 136 #define le32_to_cpu(x) bswap_32(x) 137 #define le16_to_cpu(x) bswap_16(x) 138 #define cpu_to_le32(x) bswap_32(x) 139 #define cpu_to_le16(x) bswap_16(x) 140 #else 141 #define le32_to_cpu(x) (x) 142 #define le16_to_cpu(x) (x) 143 #define cpu_to_le32(x) (x) 144 #define cpu_to_le16(x) (x) 145 #endif 146 147 /* Provide substitutes for gcc's __FUNCTION__ on other compilers */ 148 #if !defined(__GNUC__) && !defined(__FUNCTION__) 149 # define __FUNCTION__ __func__ /* C99 */ 150 #endif 151 152 #ifndef HAVE_XF86MODEBANDWIDTH 153 extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); 154 #define MODE_BANDWIDTH MODE_BAD 155 #endif 156 157 typedef enum { 158 OPTION_NOACCEL, 159 OPTION_SW_CURSOR, 160 OPTION_DAC_6BIT, 161 OPTION_DAC_8BIT, 162 #ifdef XF86DRI 163 OPTION_BUS_TYPE, 164 OPTION_CP_PIO, 165 OPTION_USEC_TIMEOUT, 166 OPTION_AGP_MODE, 167 OPTION_AGP_FW, 168 OPTION_GART_SIZE, 169 OPTION_GART_SIZE_OLD, 170 OPTION_RING_SIZE, 171 OPTION_BUFFER_SIZE, 172 OPTION_DEPTH_MOVE, 173 OPTION_PAGE_FLIP, 174 OPTION_NO_BACKBUFFER, 175 OPTION_XV_DMA, 176 OPTION_FBTEX_PERCENT, 177 OPTION_DEPTH_BITS, 178 OPTION_PCIAPER_SIZE, 179 #ifdef USE_EXA 180 OPTION_ACCEL_DFS, 181 OPTION_EXA_PIXMAPS, 182 #endif 183 #endif 184 OPTION_IGNORE_EDID, 185 OPTION_CUSTOM_EDID, 186 OPTION_DISP_PRIORITY, 187 OPTION_PANEL_SIZE, 188 OPTION_MIN_DOTCLOCK, 189 OPTION_COLOR_TILING, 190 OPTION_COLOR_TILING_2D, 191 #ifdef XvExtension 192 OPTION_VIDEO_KEY, 193 OPTION_RAGE_THEATRE_CRYSTAL, 194 OPTION_RAGE_THEATRE_TUNER_PORT, 195 OPTION_RAGE_THEATRE_COMPOSITE_PORT, 196 OPTION_RAGE_THEATRE_SVIDEO_PORT, 197 OPTION_TUNER_TYPE, 198 OPTION_RAGE_THEATRE_MICROC_PATH, 199 OPTION_RAGE_THEATRE_MICROC_TYPE, 200 OPTION_SCALER_WIDTH, 201 #endif 202 #ifdef RENDER 203 OPTION_RENDER_ACCEL, 204 OPTION_SUBPIXEL_ORDER, 205 #endif 206 OPTION_SHOWCACHE, 207 OPTION_CLOCK_GATING, 208 OPTION_BIOS_HOTKEYS, 209 OPTION_VGA_ACCESS, 210 OPTION_REVERSE_DDC, 211 OPTION_LVDS_PROBE_PLL, 212 OPTION_ACCELMETHOD, 213 OPTION_CONNECTORTABLE, 214 OPTION_DRI, 215 OPTION_DEFAULT_CONNECTOR_TABLE, 216 #if defined(__powerpc__) 217 OPTION_MAC_MODEL, 218 #endif 219 OPTION_DEFAULT_TMDS_PLL, 220 OPTION_TVDAC_LOAD_DETECT, 221 OPTION_FORCE_TVOUT, 222 OPTION_TVSTD, 223 OPTION_IGNORE_LID_STATUS, 224 OPTION_DEFAULT_TVDAC_ADJ, 225 OPTION_INT10, 226 OPTION_EXA_VSYNC, 227 OPTION_ATOM_TVOUT, 228 OPTION_R4XX_ATOM, 229 OPTION_FORCE_LOW_POWER, 230 OPTION_DYNAMIC_PM, 231 OPTION_NEW_PLL, 232 OPTION_ZAPHOD_HEADS, 233 OPTION_SWAPBUFFERS_WAIT 234 } RADEONOpts; 235 236 237 #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ 238 #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ 239 240 #define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ 241 242 /* Buffer are aligned on 4096 byte boundaries */ 243 #define RADEON_GPU_PAGE_SIZE 4096 244 #define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1) 245 #define RADEON_VBIOS_SIZE 0x00010000 246 #define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX 247 * Need to comfirm this is not used 248 * for something else. 249 */ 250 251 #define xFixedToFloat(f) (((float) (f)) / 65536) 252 253 #define RADEON_LOGLEVEL_DEBUG 4 254 255 /* for Xv, outputs */ 256 #define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) 257 258 /* Other macros */ 259 #define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 260 #define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) 261 #define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) 262 263 typedef struct { 264 int revision; 265 uint16_t rr1_offset; 266 uint16_t rr2_offset; 267 uint16_t dyn_clk_offset; 268 uint16_t pll_offset; 269 uint16_t mem_config_offset; 270 uint16_t mem_reset_offset; 271 uint16_t short_mem_offset; 272 uint16_t rr3_offset; 273 uint16_t rr4_offset; 274 } RADEONBIOSInitTable; 275 276 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 277 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 278 #define RADEON_PLL_USE_REF_DIV (1 << 2) 279 #define RADEON_PLL_LEGACY (1 << 3) 280 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 281 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 282 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 283 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 284 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 285 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 286 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 287 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 288 #define RADEON_PLL_USE_POST_DIV (1 << 12) 289 290 typedef struct { 291 uint32_t reference_freq; 292 uint32_t reference_div; 293 uint32_t post_div; 294 uint32_t pll_in_min; 295 uint32_t pll_in_max; 296 uint32_t pll_out_min; 297 uint32_t pll_out_max; 298 uint16_t xclk; 299 300 uint32_t min_ref_div; 301 uint32_t max_ref_div; 302 uint32_t min_post_div; 303 uint32_t max_post_div; 304 uint32_t min_feedback_div; 305 uint32_t max_feedback_div; 306 uint32_t min_frac_feedback_div; 307 uint32_t max_frac_feedback_div; 308 uint32_t best_vco; 309 } RADEONPLLRec, *RADEONPLLPtr; 310 311 typedef struct { 312 int bitsPerPixel; 313 int depth; 314 int displayWidth; 315 int displayHeight; 316 int pixel_code; 317 int pixel_bytes; 318 DisplayModePtr mode; 319 } RADEONFBLayout; 320 321 #define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ 322 (info->ChipFamily == CHIP_FAMILY_RV200) || \ 323 (info->ChipFamily == CHIP_FAMILY_RS100) || \ 324 (info->ChipFamily == CHIP_FAMILY_RS200) || \ 325 (info->ChipFamily == CHIP_FAMILY_RV250) || \ 326 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 327 (info->ChipFamily == CHIP_FAMILY_RS300)) 328 329 330 #define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ 331 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 332 (info->ChipFamily == CHIP_FAMILY_R350) || \ 333 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 334 (info->ChipFamily == CHIP_FAMILY_R420) || \ 335 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 336 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 337 (info->ChipFamily == CHIP_FAMILY_RS480)) 338 339 #define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) 340 341 #define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) 342 343 #define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730)) 344 345 #define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR)) 346 347 #define IS_DCE41_VARIANT ((info->ChipFamily >= CHIP_FAMILY_PALM)) 348 349 #define IS_DCE5_VARIANT ((info->ChipFamily >= CHIP_FAMILY_BARTS)) 350 351 #define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR) 352 353 #define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600) 354 355 #define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ 356 (info->ChipFamily == CHIP_FAMILY_R520) || \ 357 (info->ChipFamily == CHIP_FAMILY_RV530) || \ 358 (info->ChipFamily == CHIP_FAMILY_R580) || \ 359 (info->ChipFamily == CHIP_FAMILY_RV560) || \ 360 (info->ChipFamily == CHIP_FAMILY_RV570)) 361 362 #define IS_R400_3D ((info->ChipFamily == CHIP_FAMILY_R420) || \ 363 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 364 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 365 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 366 (info->ChipFamily == CHIP_FAMILY_RS740)) 367 368 #define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ 369 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 370 (info->ChipFamily == CHIP_FAMILY_R350) || \ 371 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 372 (info->ChipFamily == CHIP_FAMILY_R420) || \ 373 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 374 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 375 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 376 (info->ChipFamily == CHIP_FAMILY_RS740) || \ 377 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 378 (info->ChipFamily == CHIP_FAMILY_RS480)) 379 380 #define IS_R200_3D ((info->ChipFamily == CHIP_FAMILY_RV250) || \ 381 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 382 (info->ChipFamily == CHIP_FAMILY_RS300) || \ 383 (info->ChipFamily == CHIP_FAMILY_R200)) 384 385 /* 386 * Errata workarounds 387 */ 388 typedef enum { 389 CHIP_ERRATA_R300_CG = 0x00000001, 390 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 391 CHIP_ERRATA_PLL_DELAY = 0x00000004 392 } RADEONErrata; 393 394 typedef enum { 395 RADEON_DVOCHIP_NONE, 396 RADEON_SIL_164, 397 RADEON_SIL_1178 398 } RADEONExtTMDSChip; 399 400 #if defined(__powerpc__) 401 typedef enum { 402 RADEON_MAC_NONE, 403 RADEON_MAC_IBOOK, 404 RADEON_MAC_POWERBOOK_EXTERNAL, 405 RADEON_MAC_POWERBOOK_INTERNAL, 406 RADEON_MAC_POWERBOOK_VGA, 407 RADEON_MAC_MINI_EXTERNAL, 408 RADEON_MAC_MINI_INTERNAL, 409 RADEON_MAC_IMAC_G5_ISIGHT, 410 RADEON_MAC_EMAC, 411 RADEON_MAC_SAM440EP 412 } RADEONMacModel; 413 #endif 414 415 typedef enum { 416 CARD_PCI, 417 CARD_AGP, 418 CARD_PCIE 419 } RADEONCardType; 420 421 typedef enum { 422 POWER_DEFAULT, 423 POWER_LOW, 424 POWER_HIGH 425 } RADEONPMType; 426 427 typedef struct { 428 RADEONPMType type; 429 uint32_t sclk; 430 uint32_t mclk; 431 uint32_t pcie_lanes; 432 uint32_t flags; 433 } RADEONPowerMode; 434 435 typedef struct { 436 /* power modes */ 437 int num_modes; 438 int current_mode; 439 RADEONPowerMode mode[3]; 440 441 Bool clock_gating_enabled; 442 Bool dynamic_mode_enabled; 443 Bool force_low_power_enabled; 444 } RADEONPowerManagement; 445 446 typedef struct _atomBiosHandle *atomBiosHandlePtr; 447 448 struct radeon_exa_pixmap_priv { 449 struct radeon_bo *bo; 450 uint32_t tiling_flags; 451 #ifdef XF86DRM_MODE 452 struct radeon_surface surface; 453 #endif 454 Bool bo_mapped; 455 }; 456 457 #define RADEON_2D_EXA_COPY 1 458 #define RADEON_2D_EXA_SOLID 2 459 460 struct radeon_2d_state { 461 int op; // 462 uint32_t dst_pitch_offset; 463 uint32_t src_pitch_offset; 464 uint32_t dp_gui_master_cntl; 465 uint32_t dp_cntl; 466 uint32_t dp_write_mask; 467 uint32_t dp_brush_frgd_clr; 468 uint32_t dp_brush_bkgd_clr; 469 uint32_t dp_src_frgd_clr; 470 uint32_t dp_src_bkgd_clr; 471 uint32_t default_sc_bottom_right; 472 struct radeon_bo *dst_bo; 473 struct radeon_bo *src_bo; 474 }; 475 476 #ifdef XF86DRI 477 struct radeon_cp { 478 Bool CPRuns; /* CP is running */ 479 Bool CPInUse; /* CP has been used by X server */ 480 Bool CPStarted; /* CP has started */ 481 int CPMode; /* CP mode that server/clients use */ 482 int CPFifoSize; /* Size of the CP command FIFO */ 483 int CPusecTimeout; /* CP timeout in usecs */ 484 Bool needCacheFlush; 485 486 /* CP accleration */ 487 drmBufPtr indirectBuffer; 488 int indirectStart; 489 490 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ 491 int dma_begin_count; 492 char *dma_debug_func; 493 int dma_debug_lineno; 494 495 }; 496 497 typedef struct { 498 /* Nothing here yet */ 499 int dummy; 500 } RADEONConfigPrivRec, *RADEONConfigPrivPtr; 501 502 typedef struct { 503 /* Nothing here yet */ 504 int dummy; 505 } RADEONDRIContextRec, *RADEONDRIContextPtr; 506 507 struct radeon_dri { 508 Bool noBackBuffer; 509 510 Bool newMemoryMap; 511 drmVersionPtr pLibDRMVersion; 512 drmVersionPtr pKernelDRMVersion; 513 DRIInfoPtr pDRIInfo; 514 int drmFD; 515 int numVisualConfigs; 516 __GLXvisualConfig *pVisualConfigs; 517 RADEONConfigPrivPtr pVisualConfigsPriv; 518 Bool (*DRICloseScreen)(CLOSE_SCREEN_ARGS_DECL); 519 520 drm_handle_t fbHandle; 521 522 drmSize registerSize; 523 drm_handle_t registerHandle; 524 525 drmSize pciSize; 526 drm_handle_t pciMemHandle; 527 unsigned char *PCI; /* Map */ 528 529 Bool depthMoves; /* Enable depth moves -- slow! */ 530 Bool allowPageFlip; /* Enable 3d page flipping */ 531 #ifdef DAMAGE 532 DamagePtr pDamage; 533 RegionRec driRegion; 534 #endif 535 Bool have3DWindows; /* Are there any 3d clients? */ 536 537 int pciAperSize; 538 drmSize gartSize; 539 drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ 540 unsigned long gartOffset; 541 unsigned char *AGP; /* Map */ 542 int agpMode; 543 544 uint32_t pciCommand; 545 546 /* CP ring buffer data */ 547 unsigned long ringStart; /* Offset into GART space */ 548 drm_handle_t ringHandle; /* Handle from drmAddMap */ 549 drmSize ringMapSize; /* Size of map */ 550 int ringSize; /* Size of ring (in MB) */ 551 drmAddress ring; /* Map */ 552 int ringSizeLog2QW; 553 554 unsigned long ringReadOffset; /* Offset into GART space */ 555 drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ 556 drmSize ringReadMapSize; /* Size of map */ 557 drmAddress ringReadPtr; /* Map */ 558 559 /* CP vertex/indirect buffer data */ 560 unsigned long bufStart; /* Offset into GART space */ 561 drm_handle_t bufHandle; /* Handle from drmAddMap */ 562 drmSize bufMapSize; /* Size of map */ 563 int bufSize; /* Size of buffers (in MB) */ 564 drmAddress buf; /* Map */ 565 int bufNumBufs; /* Number of buffers */ 566 drmBufMapPtr buffers; /* Buffer map */ 567 568 /* CP GART Texture data */ 569 unsigned long gartTexStart; /* Offset into GART space */ 570 drm_handle_t gartTexHandle; /* Handle from drmAddMap */ 571 drmSize gartTexMapSize; /* Size of map */ 572 int gartTexSize; /* Size of GART tex space (in MB) */ 573 drmAddress gartTex; /* Map */ 574 int log2GARTTexGran; 575 576 /* DRI screen private data */ 577 int fbX; 578 int fbY; 579 int backX; 580 int backY; 581 int depthX; 582 int depthY; 583 584 int frontOffset; 585 int frontPitch; 586 int backOffset; 587 int backPitch; 588 int depthOffset; 589 int depthPitch; 590 int depthBits; 591 int textureOffset; 592 int textureSize; 593 int log2TexGran; 594 595 int pciGartSize; 596 uint32_t pciGartOffset; 597 void *pciGartBackup; 598 599 int irq; 600 601 #ifdef USE_XAA 602 uint32_t frontPitchOffset; 603 uint32_t backPitchOffset; 604 uint32_t depthPitchOffset; 605 606 /* offscreen memory management */ 607 int backLines; 608 FBAreaPtr backArea; 609 int depthTexLines; 610 FBAreaPtr depthTexArea; 611 #endif 612 613 }; 614 #endif 615 616 #define DMA_BO_FREE_TIME 1000 617 618 struct radeon_dma_bo { 619 struct radeon_dma_bo *next, *prev; 620 struct radeon_bo *bo; 621 int expire_counter; 622 }; 623 624 struct r600_accel_object { 625 uint32_t pitch; 626 uint32_t width; 627 uint32_t height; 628 uint32_t offset; 629 int bpp; 630 uint32_t domain; 631 struct radeon_bo *bo; 632 uint32_t tiling_flags; 633 #if defined(XF86DRM_MODE) 634 struct radeon_surface *surface; 635 #endif 636 }; 637 638 struct radeon_vbo_object { 639 int vb_offset; 640 uint64_t vb_mc_addr; 641 int vb_total; 642 void *vb_ptr; 643 uint32_t vb_size; 644 uint32_t vb_op_vert_size; 645 int32_t vb_start_op; 646 struct radeon_bo *vb_bo; 647 unsigned verts_per_op; 648 }; 649 650 struct radeon_accel_state { 651 /* common accel data */ 652 int fifo_slots; /* Free slots in the FIFO (64 max) */ 653 /* Computed values for Radeon */ 654 uint32_t dp_gui_master_cntl; 655 uint32_t dp_gui_master_cntl_clip; 656 uint32_t trans_color; 657 /* Saved values for ScreenToScreenCopy */ 658 int xdir; 659 int ydir; 660 uint32_t dst_pitch_offset; 661 662 /* render accel */ 663 unsigned short texW[2]; 664 unsigned short texH[2]; 665 Bool XInited3D; /* X itself has the 3D context */ 666 int num_gb_pipes; 667 Bool has_tcl; 668 Bool allowHWDFS; 669 670 #ifdef USE_EXA 671 /* EXA */ 672 ExaDriverPtr exa; 673 int exaSyncMarker; 674 int exaMarkerSynced; 675 int engineMode; 676 #define EXA_ENGINEMODE_UNKNOWN 0 677 #define EXA_ENGINEMODE_2D 1 678 #define EXA_ENGINEMODE_3D 2 679 680 int composite_op; 681 PicturePtr dst_pic; 682 PicturePtr msk_pic; 683 PicturePtr src_pic; 684 PixmapPtr dst_pix; 685 PixmapPtr msk_pix; 686 PixmapPtr src_pix; 687 Bool is_transform[2]; 688 PictTransform *transform[2]; 689 /* Whether we are tiling horizontally and vertically */ 690 Bool need_src_tile_x; 691 Bool need_src_tile_y; 692 /* Size of tiles ... set to 65536x65536 if not tiling in that direction */ 693 Bool src_tile_width; 694 Bool src_tile_height; 695 uint32_t *draw_header; 696 unsigned vtx_count; 697 unsigned num_vtx; 698 Bool vsync; 699 700 drmBufPtr ib; 701 702 struct radeon_vbo_object vbo; 703 struct radeon_vbo_object cbuf; 704 705 /* where to discard IB from if we cancel operation */ 706 uint32_t ib_reset_op; 707 #ifdef XF86DRM_MODE 708 struct radeon_dma_bo bo_free; 709 struct radeon_dma_bo bo_wait; 710 struct radeon_dma_bo bo_reserved; 711 Bool use_vbos; 712 #endif 713 void (*finish_op)(ScrnInfoPtr, int); 714 // shader storage 715 ExaOffscreenArea *shaders; 716 struct radeon_bo *shaders_bo; 717 uint32_t solid_vs_offset; 718 uint32_t solid_ps_offset; 719 uint32_t copy_vs_offset; 720 uint32_t copy_ps_offset; 721 uint32_t comp_vs_offset; 722 uint32_t comp_ps_offset; 723 uint32_t xv_vs_offset; 724 uint32_t xv_ps_offset; 725 // shader consts 726 uint32_t solid_vs_const_offset; 727 uint32_t solid_ps_const_offset; 728 uint32_t copy_vs_const_offset; 729 uint32_t copy_ps_const_offset; 730 uint32_t comp_vs_const_offset; 731 uint32_t comp_ps_const_offset; 732 uint32_t comp_mask_ps_const_offset; 733 uint32_t xv_vs_const_offset; 734 uint32_t xv_ps_const_offset; 735 736 //size/addr stuff 737 struct r600_accel_object src_obj[2]; 738 struct r600_accel_object dst_obj; 739 uint32_t src_size[2]; 740 uint32_t dst_size; 741 742 uint32_t vs_size; 743 uint64_t vs_mc_addr; 744 uint32_t ps_size; 745 uint64_t ps_mc_addr; 746 747 // UTS/DFS 748 drmBufPtr scratch; 749 750 // solid/copy 751 ExaOffscreenArea *copy_area; 752 struct radeon_bo *copy_area_bo; 753 Bool same_surface; 754 int rop; 755 uint32_t planemask; 756 uint32_t fg; 757 758 // composite 759 Bool component_alpha; 760 Bool src_alpha; 761 // vline 762 xf86CrtcPtr vline_crtc; 763 int vline_y1; 764 int vline_y2; 765 #endif 766 767 #ifdef USE_XAA 768 /* XAA */ 769 XAAInfoRecPtr accel; 770 /* ScanlineScreenToScreenColorExpand support */ 771 unsigned char *scratch_buffer[1]; 772 unsigned char *scratch_save; 773 int scanline_x; 774 int scanline_y; 775 int scanline_w; 776 int scanline_h; 777 int scanline_h_w; 778 int scanline_words; 779 int scanline_direct; 780 int scanline_bpp; /* Only used for ImageWrite */ 781 int scanline_fg; 782 int scanline_bg; 783 int scanline_hpass; 784 int scanline_x1clip; 785 int scanline_x2clip; 786 /* Saved values for DashedTwoPointLine */ 787 int dashLen; 788 uint32_t dashPattern; 789 int dash_fg; 790 int dash_bg; 791 792 FBLinearPtr RenderTex; 793 void (*RenderCallback)(ScrnInfoPtr); 794 Time RenderTimeout; 795 /* 796 * XAAForceTransBlit is used to change the behavior of the XAA 797 * SetupForScreenToScreenCopy function, to make it DGA-friendly. 798 */ 799 Bool XAAForceTransBlit; 800 #endif 801 802 }; 803 804 typedef struct { 805 EntityInfoPtr pEnt; 806 pciVideoPtr PciInfo; 807 #ifndef XSERVER_LIBPCIACCESS 808 PCITAG PciTag; 809 #endif 810 int Chipset; 811 RADEONChipFamily ChipFamily; 812 RADEONErrata ChipErrata; 813 814 unsigned long long LinearAddr; /* Frame buffer physical address */ 815 unsigned long long MMIOAddr; /* MMIO region physical address */ 816 unsigned long long BIOSAddr; /* BIOS physical address */ 817 uint64_t fbLocation; 818 uint32_t gartLocation; 819 uint32_t mc_fb_location; 820 uint32_t mc_agp_location; 821 uint32_t mc_agp_location_hi; 822 823 void *MMIO; /* Map of MMIO region */ 824 void *FB; /* Map of frame buffer */ 825 uint8_t *VBIOS; /* Video BIOS pointer */ 826 827 Bool IsAtomBios; /* New BIOS used in R420 etc. */ 828 int ROMHeaderStart; /* Start of the ROM Info Table */ 829 int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ 830 831 uint32_t MemCntl; 832 uint32_t BusCntl; 833 unsigned long MMIOSize; /* MMIO region physical address */ 834 unsigned long FbMapSize; /* Size of frame buffer, in bytes */ 835 unsigned long FbSecureSize; /* Size of secured fb area at end of 836 framebuffer */ 837 838 Bool IsMobility; /* Mobile chips for laptops */ 839 Bool IsIGP; /* IGP chips */ 840 Bool HasSingleDAC; /* only TVDAC on chip */ 841 Bool ddc_mode; /* Validate mode by matching exactly 842 * the modes supported in DDC data 843 */ 844 Bool R300CGWorkaround; 845 846 /* EDID or BIOS values for FPs */ 847 int RefDivider; 848 int FeedbackDivider; 849 int PostDivider; 850 Bool UseBiosDividers; 851 /* EDID data using DDC interface */ 852 Bool ddc_bios; 853 Bool ddc1; 854 Bool ddc2; 855 856 RADEONPLLRec pll; 857 int default_dispclk; 858 int dp_extclk; 859 860 int RamWidth; 861 float sclk; /* in MHz */ 862 float mclk; /* in MHz */ 863 Bool IsDDR; 864 int DispPriority; 865 866 RADEONSavePtr SavedReg; /* Original (text) mode */ 867 RADEONSavePtr ModeReg; /* Current mode */ 868 Bool (*CloseScreen)(CLOSE_SCREEN_ARGS_DECL); 869 870 void (*BlockHandler)(BLOCKHANDLER_ARGS_DECL); 871 872 Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ 873 874 xf86CursorInfoPtr cursor; 875 #ifdef ARGB_CURSOR 876 Bool cursor_argb; 877 #endif 878 int cursor_fg; 879 int cursor_bg; 880 881 int pix24bpp; /* Depth of pixmap for 24bpp fb */ 882 Bool dac6bits; /* Use 6 bit DAC? */ 883 884 RADEONFBLayout CurrentLayout; 885 886 #ifdef XF86DRI 887 Bool directRenderingEnabled; 888 Bool directRenderingInited; 889 RADEONCardType cardType; /* Current card is a PCI card */ 890 struct radeon_cp *cp; 891 struct radeon_dri *dri; 892 #ifdef XF86DRM_MODE 893 struct radeon_dri2 dri2; 894 #endif 895 #ifdef USE_EXA 896 Bool accelDFS; 897 #endif 898 Bool DMAForXv; 899 #endif /* XF86DRI */ 900 901 /* accel */ 902 Bool RenderAccel; /* Render */ 903 Bool allowColorTiling; 904 Bool allowColorTiling2D; 905 Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ 906 struct radeon_accel_state *accel_state; 907 Bool accelOn; 908 Bool useEXA; 909 #ifdef USE_EXA 910 Bool exa_pixmaps; 911 Bool exa_force_create; 912 XF86ModReqInfo exaReq; 913 #endif 914 #ifdef USE_XAA 915 XF86ModReqInfo xaaReq; 916 #endif 917 918 /* XVideo */ 919 XF86VideoAdaptorPtr adaptor; 920 void (*VideoTimerCallback)(ScrnInfoPtr, Time); 921 int videoKey; 922 int RageTheatreCrystal; 923 int RageTheatreTunerPort; 924 int RageTheatreCompositePort; 925 int RageTheatreSVideoPort; 926 int tunerType; 927 const char* RageTheatreMicrocPath; 928 const char* RageTheatreMicrocType; 929 Bool MM_TABLE_valid; 930 struct { 931 uint8_t table_revision; 932 uint8_t table_size; 933 uint8_t tuner_type; 934 uint8_t audio_chip; 935 uint8_t product_id; 936 uint8_t tuner_voltage_teletext_fm; 937 uint8_t i2s_config; /* configuration of the sound chip */ 938 uint8_t video_decoder_type; 939 uint8_t video_decoder_host_config; 940 uint8_t input[5]; 941 } MM_TABLE; 942 uint16_t video_decoder_type; 943 int overlay_scaler_buffer_width; 944 int ecp_div; 945 unsigned int xv_max_width; 946 unsigned int xv_max_height; 947 948 /* general */ 949 OptionInfoPtr Options; 950 951 DisplayModePtr currentMode, savedCurrentMode; 952 953 /* special handlings for DELL triple-head server */ 954 Bool IsDellServer; 955 956 Bool VGAAccess; 957 958 int MaxSurfaceWidth; 959 int MaxLines; 960 961 Bool want_vblank_interrupts; 962 RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; 963 radeon_encoder_ptr encoders[RADEON_MAX_BIOS_CONNECTOR]; 964 RADEONBIOSInitTable BiosTable; 965 966 /* save crtc state for console restore */ 967 Bool crtc_on; 968 Bool crtc2_on; 969 970 Bool InternalTVOut; 971 972 #if defined(__powerpc__) 973 RADEONMacModel MacModel; 974 #endif 975 RADEONExtTMDSChip ext_tmds_chip; 976 977 atomBiosHandlePtr atomBIOS; 978 unsigned long FbFreeStart, FbFreeSize; 979 unsigned char* BIOSCopy; 980 981 CreateScreenResourcesProcPtr CreateScreenResources; 982 983 /* if no devices are connected at server startup */ 984 Bool first_load_no_devices; 985 986 Bool IsSecondary; 987 Bool IsPrimary; 988 989 Bool r600_shadow_fb; 990 void *fb_shadow; 991 992 /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ 993 Bool get_hardcoded_edid_from_bios; 994 995 int virtualX; 996 int virtualY; 997 998 Bool r4xx_atom; 999 1000 /* pm */ 1001 RADEONPowerManagement pm; 1002 1003 /* igp info */ 1004 float igp_sideport_mclk; 1005 float igp_system_mclk; 1006 float igp_ht_link_clk; 1007 float igp_ht_link_width; 1008 1009 int can_resize; 1010 void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 1011 struct radeon_2d_state state_2d; 1012 Bool kms_enabled; 1013 struct radeon_bo *front_bo; 1014 #ifdef XF86DRM_MODE 1015 struct radeon_bo_manager *bufmgr; 1016 struct radeon_cs_manager *csm; 1017 struct radeon_cs *cs; 1018 1019 struct radeon_bo *cursor_bo[32]; 1020 uint64_t vram_size; 1021 uint64_t gart_size; 1022 drmmode_rec drmmode; 1023 /* r6xx+ tile config */ 1024 Bool have_tiling_info; 1025 uint32_t tile_config; 1026 int group_bytes; 1027 int num_channels; 1028 int num_banks; 1029 int r7xx_bank_op; 1030 struct radeon_surface_manager *surf_man; 1031 struct radeon_surface front_surface; 1032 #else 1033 /* fake bool */ 1034 Bool cs; 1035 #endif 1036 1037 /* Xv bicubic filtering */ 1038 struct radeon_bo *bicubic_bo; 1039 void *bicubic_memory; 1040 int bicubic_offset; 1041 /* kms pageflipping */ 1042 Bool allowPageFlip; 1043 1044 /* Perform vsync'ed SwapBuffers? */ 1045 Bool swapBuffersWait; 1046 } RADEONInfoRec, *RADEONInfoPtr; 1047 1048 #define RADEONWaitForFifo(pScrn, entries) \ 1049 do { \ 1050 if (info->accel_state->fifo_slots < entries) \ 1051 RADEONWaitForFifoFunction(pScrn, entries); \ 1052 info->accel_state->fifo_slots -= entries; \ 1053 } while (0) 1054 1055 /* legacy_crtc.c */ 1056 extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); 1057 extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1058 DisplayModePtr adjusted_mode, int x, int y); 1059 extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 1060 RADEONSavePtr restore); 1061 extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 1062 RADEONSavePtr restore); 1063 extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 1064 RADEONSavePtr restore); 1065 extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 1066 RADEONSavePtr restore); 1067 extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 1068 RADEONSavePtr restore); 1069 extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1070 extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1071 extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1072 extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1073 extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1074 1075 /* legacy_output.c */ 1076 extern RADEONMonitorType legacy_dac_detect(xf86OutputPtr output); 1077 extern void legacy_output_dpms(xf86OutputPtr output, int mode); 1078 extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, 1079 DisplayModePtr adjusted_mode); 1080 extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); 1081 extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); 1082 extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); 1083 extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1084 extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1085 extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1086 extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1087 extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1088 extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1089 extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1090 extern void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID); 1091 1092 extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1093 extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1094 extern void RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1095 extern void RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1096 extern void RADEONGetLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1097 1098 /* radeon_accel.c */ 1099 extern Bool RADEONAccelInit(ScreenPtr pScreen); 1100 extern void RADEONEngineFlush(ScrnInfoPtr pScrn); 1101 extern void RADEONEngineInit(ScrnInfoPtr pScrn); 1102 extern void RADEONEngineReset(ScrnInfoPtr pScrn); 1103 extern void RADEONEngineRestore(ScrnInfoPtr pScrn); 1104 extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, 1105 unsigned int w, uint32_t dstPitchOff, 1106 uint32_t *bufPitch, int x, int *y, 1107 unsigned int *h, unsigned int *hpass); 1108 extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, 1109 unsigned int bpp, 1110 uint8_t *dst, uint8_t *src, 1111 unsigned int hpass, 1112 unsigned int dstPitch, 1113 unsigned int srcPitch); 1114 extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); 1115 extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, 1116 uint32_t pitch, int cpp, 1117 uint32_t *dstPitchOffset, int *x, int *y); 1118 extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); 1119 extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); 1120 #ifdef XF86DRI 1121 extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); 1122 extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); 1123 extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); 1124 extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); 1125 # ifdef USE_XAA 1126 extern Bool RADEONSetupMemXAA_DRI(ScreenPtr pScreen); 1127 # endif 1128 uint32_t radeonGetPixmapOffset(PixmapPtr pPix); 1129 #endif 1130 extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); 1131 1132 #ifdef USE_XAA 1133 /* radeon_accelfuncs.c */ 1134 extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); 1135 extern Bool RADEONSetupMemXAA(ScreenPtr pScreen); 1136 #endif 1137 1138 /* radeon_bios.c */ 1139 extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); 1140 extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); 1141 extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); 1142 extern Bool RADEONGetDAC2InfoFromBIOS(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1143 extern Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1144 extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); 1145 extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); 1146 extern Bool RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1147 extern Bool RADEONGetTMDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1148 extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); 1149 extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); 1150 extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); 1151 extern Bool radeon_card_posted(ScrnInfoPtr pScrn); 1152 1153 /* radeon_commonfuncs.c */ 1154 #ifdef XF86DRI 1155 extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); 1156 extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix, 1157 xf86CrtcPtr crtc, int start, int stop); 1158 #endif 1159 extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); 1160 extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix, 1161 xf86CrtcPtr crtc, int start, int stop); 1162 1163 /* radeon_crtc.c */ 1164 extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); 1165 extern void radeon_do_crtc_dpms(xf86CrtcPtr crtc, int mode); 1166 extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); 1167 extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); 1168 extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); 1169 extern void RADEONBlank(ScrnInfoPtr pScrn); 1170 extern void RADEONComputePLL(xf86CrtcPtr crtc, 1171 RADEONPLLPtr pll, unsigned long freq, 1172 uint32_t *chosen_dot_clock_freq, 1173 uint32_t *chosen_feedback_div, 1174 uint32_t *chosen_frac_feedback_div, 1175 uint32_t *chosen_reference_div, 1176 uint32_t *chosen_post_div, int flags); 1177 extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, 1178 DisplayModePtr pMode); 1179 extern void RADEONUnblank(ScrnInfoPtr pScrn); 1180 extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); 1181 extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); 1182 1183 /* radeon_cursor.c */ 1184 extern Bool RADEONCursorInit(ScreenPtr pScreen); 1185 extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); 1186 extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); 1187 extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); 1188 extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); 1189 extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); 1190 1191 #ifdef XF86DRI 1192 /* radeon_dri.c */ 1193 extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); 1194 extern void RADEONDRICloseScreen(ScreenPtr pScreen); 1195 extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); 1196 extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); 1197 extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); 1198 extern void RADEONDRIResume(ScreenPtr pScreen); 1199 extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); 1200 extern int RADEONDRISetParam(ScrnInfoPtr pScrn, 1201 unsigned int param, int64_t value); 1202 extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); 1203 extern void RADEONDRIStop(ScreenPtr pScreen); 1204 #endif 1205 1206 /* radeon_driver.c */ 1207 extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone); 1208 extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); 1209 extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); 1210 extern int RADEONMinBits(int val); 1211 extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); 1212 extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); 1213 extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); 1214 extern unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr); 1215 extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); 1216 extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); 1217 extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); 1218 extern void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data); 1219 extern void RADEONPllErrataAfterData(RADEONInfoPtr info); 1220 extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); 1221 extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); 1222 extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); 1223 extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1224 RADEONInfoPtr info); 1225 extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 1226 RADEONSavePtr restore); 1227 extern Bool 1228 RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name); 1229 1230 Bool RADEONGetRec(ScrnInfoPtr pScrn); 1231 void RADEONFreeRec(ScrnInfoPtr pScrn); 1232 Bool RADEONPreInitVisual(ScrnInfoPtr pScrn); 1233 Bool RADEONPreInitWeight(ScrnInfoPtr pScrn); 1234 1235 extern Bool RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, 1236 char *name, xf86OutputPtr output); 1237 extern void RADEON_DP_GetDPCD(xf86OutputPtr output); 1238 extern int RADEON_DP_GetSinkType(xf86OutputPtr output); 1239 1240 /* radeon_pm.c */ 1241 extern void RADEONPMInit(ScrnInfoPtr pScrn); 1242 extern void RADEONPMBlockHandler(ScrnInfoPtr pScrn); 1243 extern void RADEONPMEnterVT(ScrnInfoPtr pScrn); 1244 extern void RADEONPMLeaveVT(ScrnInfoPtr pScrn); 1245 extern void RADEONPMFini(ScrnInfoPtr pScrn); 1246 1247 #ifdef USE_EXA 1248 /* radeon_exa.c */ 1249 extern unsigned eg_tile_split(unsigned tile_split); 1250 extern Bool RADEONSetupMemEXA(ScreenPtr pScreen); 1251 extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t); 1252 1253 /* radeon_exa_funcs.c */ 1254 extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, 1255 int dstY, int w, int h); 1256 extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, 1257 int dstY, int w, int h); 1258 extern Bool RADEONDrawInitCP(ScreenPtr pScreen); 1259 extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); 1260 extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, 1261 uint32_t src_pitch_offset, 1262 uint32_t dst_pitch_offset, 1263 uint32_t datatype, int rop, 1264 Pixel planemask); 1265 extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, 1266 uint32_t src_pitch_offset, 1267 uint32_t dst_pitch_offset, 1268 uint32_t datatype, int rop, 1269 Pixel planemask); 1270 extern Bool R600DrawInit(ScreenPtr pScreen); 1271 extern Bool R600LoadShaders(ScrnInfoPtr pScrn); 1272 #ifdef XF86DRM_MODE 1273 extern Bool EVERGREENDrawInit(ScreenPtr pScreen); 1274 #endif 1275 #endif 1276 1277 #if defined(XF86DRI) && defined(USE_EXA) 1278 /* radeon_exa.c */ 1279 extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); 1280 extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, 1281 uint32_t *pitch_offset); 1282 extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); 1283 #endif 1284 1285 /* radeon_modes.c */ 1286 extern void RADEONSetPitch(ScrnInfoPtr pScrn); 1287 extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output); 1288 1289 /* radeon_output.c */ 1290 extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); 1291 extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); 1292 extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); 1293 extern void RADEONInitConnector(xf86OutputPtr output); 1294 extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); 1295 extern void RADEONSetOutputType(ScrnInfoPtr pScrn, 1296 RADEONOutputPrivatePtr radeon_output); 1297 extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); 1298 extern Bool RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, Bool lock_state); 1299 1300 extern Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); 1301 1302 /* radeon_tv.c */ 1303 extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1304 extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1305 DisplayModePtr mode, xf86OutputPtr output); 1306 extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1307 DisplayModePtr mode, xf86OutputPtr output); 1308 extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1309 DisplayModePtr mode, xf86OutputPtr output); 1310 extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1311 DisplayModePtr mode, xf86OutputPtr output); 1312 extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, 1313 DisplayModePtr mode, BOOL IsPrimary); 1314 extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1315 extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); 1316 1317 /* radeon_video.c */ 1318 extern void RADEONInitVideo(ScreenPtr pScreen); 1319 extern void RADEONResetVideo(ScrnInfoPtr pScrn); 1320 extern Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn); 1321 extern xf86CrtcPtr radeon_pick_best_crtc(ScrnInfoPtr pScrn, 1322 int x1, int x2, int y1, int y2); 1323 1324 /* radeon_legacy_memory.c */ 1325 extern uint32_t 1326 radeon_legacy_allocate_memory(ScrnInfoPtr pScrn, 1327 void **mem_struct, 1328 int size, 1329 int align, 1330 int domain); 1331 extern void 1332 radeon_legacy_free_memory(ScrnInfoPtr pScrn, 1333 void *mem_struct); 1334 1335 #ifdef XF86DRM_MODE 1336 extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); 1337 extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 1338 int num, const char *file, 1339 const char *func, int line); 1340 void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); 1341 struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix); 1342 #endif 1343 struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); 1344 void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo); 1345 uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix); 1346 1347 #ifdef XF86DRI 1348 # ifdef USE_XAA 1349 /* radeon_accelfuncs.c */ 1350 extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); 1351 # endif 1352 1353 #define RADEONCP_START(pScrn, info) \ 1354 do { \ 1355 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \ 1356 if (_ret) { \ 1357 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1358 "%s: CP start %d\n", __FUNCTION__, _ret); \ 1359 } \ 1360 info->cp->CPStarted = TRUE; \ 1361 } while (0) 1362 1363 #define RADEONCP_RELEASE(pScrn, info) \ 1364 do { \ 1365 if (info->cs) { \ 1366 radeon_cs_flush_indirect(pScrn); \ 1367 } else if (info->cp->CPInUse) { \ 1368 RADEON_PURGE_CACHE(); \ 1369 RADEON_WAIT_UNTIL_IDLE(); \ 1370 RADEONCPReleaseIndirect(pScrn); \ 1371 info->cp->CPInUse = FALSE; \ 1372 } \ 1373 } while (0) 1374 1375 #define RADEONCP_STOP(pScrn, info) \ 1376 do { \ 1377 int _ret; \ 1378 if (info->cp->CPStarted) { \ 1379 _ret = RADEONCPStop(pScrn, info); \ 1380 if (_ret) { \ 1381 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1382 "%s: CP stop %d\n", __FUNCTION__, _ret); \ 1383 } \ 1384 info->cp->CPStarted = FALSE; \ 1385 } \ 1386 if (info->ChipFamily < CHIP_FAMILY_R600) \ 1387 RADEONEngineRestore(pScrn); \ 1388 info->cp->CPRuns = FALSE; \ 1389 } while (0) 1390 1391 #define RADEONCP_RESET(pScrn, info) \ 1392 do { \ 1393 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \ 1394 if (_ret) { \ 1395 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1396 "%s: CP reset %d\n", __FUNCTION__, _ret); \ 1397 } \ 1398 } while (0) 1399 1400 #define RADEONCP_REFRESH(pScrn, info) \ 1401 do { \ 1402 if (!info->cp->CPInUse && !info->cs) { \ 1403 if (info->cp->needCacheFlush) { \ 1404 RADEON_PURGE_CACHE(); \ 1405 RADEON_PURGE_ZCACHE(); \ 1406 info->cp->needCacheFlush = FALSE; \ 1407 } \ 1408 RADEON_WAIT_UNTIL_IDLE(); \ 1409 info->cp->CPInUse = TRUE; \ 1410 } \ 1411 } while (0) 1412 1413 1414 #define CP_PACKET0(reg, n) \ 1415 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1416 #define CP_PACKET1(reg0, reg1) \ 1417 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) 1418 #define CP_PACKET2() \ 1419 (RADEON_CP_PACKET2) 1420 #define CP_PACKET3(pkt, n) \ 1421 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1422 1423 1424 #define RADEON_VERBOSE 0 1425 1426 #define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 1427 1428 #define BEGIN_RING(n) do { \ 1429 if (RADEON_VERBOSE) { \ 1430 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1431 "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ 1432 } \ 1433 if (info->cs) { radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); } else { \ 1434 if (++info->cp->dma_begin_count != 1) { \ 1435 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1436 "BEGIN_RING without end at %s:%d\n", \ 1437 info->cp->dma_debug_func, info->cp->dma_debug_lineno); \ 1438 info->cp->dma_begin_count = 1; \ 1439 } \ 1440 info->cp->dma_debug_func = __FILE__; \ 1441 info->cp->dma_debug_lineno = __LINE__; \ 1442 if (!info->cp->indirectBuffer) { \ 1443 info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ 1444 info->cp->indirectStart = 0; \ 1445 } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ 1446 info->cp->indirectBuffer->total) { \ 1447 RADEONCPFlushIndirect(pScrn, 1); \ 1448 } \ 1449 __expected = n; \ 1450 __head = (pointer)((char *)info->cp->indirectBuffer->address + \ 1451 info->cp->indirectBuffer->used); \ 1452 __count = 0; \ 1453 } \ 1454 } while (0) 1455 1456 #define ADVANCE_RING() do { \ 1457 if (info->cs) radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); else { \ 1458 if (info->cp->dma_begin_count-- != 1) { \ 1459 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1460 "ADVANCE_RING without begin at %s:%d\n", \ 1461 __FILE__, __LINE__); \ 1462 info->cp->dma_begin_count = 0; \ 1463 } \ 1464 if (__count != __expected) { \ 1465 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1466 "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ 1467 __count, __expected, __FILE__, __LINE__); \ 1468 } \ 1469 if (RADEON_VERBOSE) { \ 1470 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1471 "ADVANCE_RING() start: %d used: %d count: %d\n", \ 1472 info->cp->indirectStart, \ 1473 info->cp->indirectBuffer->used, \ 1474 __count * (int)sizeof(uint32_t)); \ 1475 } \ 1476 info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ 1477 } \ 1478 } while (0) 1479 1480 #define OUT_RING(x) do { \ 1481 if (RADEON_VERBOSE) { \ 1482 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1483 " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ 1484 } \ 1485 if (info->cs) radeon_cs_write_dword(info->cs, (x)); else \ 1486 __head[__count++] = (x); \ 1487 } while (0) 1488 1489 #define OUT_RING_REG(reg, val) \ 1490 do { \ 1491 OUT_RING(CP_PACKET0(reg, 0)); \ 1492 OUT_RING(val); \ 1493 } while (0) 1494 1495 #define OUT_RING_RELOC(x, read_domains, write_domain) \ 1496 do { \ 1497 int _ret; \ 1498 _ret = radeon_cs_write_reloc(info->cs, x, read_domains, write_domain, 0); \ 1499 if (_ret) ErrorF("reloc emit failure %d\n", _ret); \ 1500 } while(0) 1501 1502 1503 #define FLUSH_RING() \ 1504 do { \ 1505 if (RADEON_VERBOSE) \ 1506 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1507 "FLUSH_RING in %s\n", __FUNCTION__); \ 1508 if (info->cs) \ 1509 radeon_cs_flush_indirect(pScrn); \ 1510 else if (info->cp->indirectBuffer) \ 1511 RADEONCPFlushIndirect(pScrn, 0); \ 1512 } while (0) 1513 1514 1515 #define RADEON_WAIT_UNTIL_2D_IDLE() \ 1516 do { \ 1517 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1518 BEGIN_RING(2); \ 1519 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1520 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1521 RADEON_WAIT_HOST_IDLECLEAN)); \ 1522 ADVANCE_RING(); \ 1523 } \ 1524 } while (0) 1525 1526 #define RADEON_WAIT_UNTIL_3D_IDLE() \ 1527 do { \ 1528 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1529 BEGIN_RING(2); \ 1530 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1531 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \ 1532 RADEON_WAIT_HOST_IDLECLEAN)); \ 1533 ADVANCE_RING(); \ 1534 } \ 1535 } while (0) 1536 1537 #define RADEON_WAIT_UNTIL_IDLE() \ 1538 do { \ 1539 if (RADEON_VERBOSE) { \ 1540 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1541 "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__); \ 1542 } \ 1543 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1544 BEGIN_RING(2); \ 1545 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1546 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1547 RADEON_WAIT_3D_IDLECLEAN | \ 1548 RADEON_WAIT_HOST_IDLECLEAN)); \ 1549 ADVANCE_RING(); \ 1550 } \ 1551 } while (0) 1552 1553 #define RADEON_PURGE_CACHE() \ 1554 do { \ 1555 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1556 BEGIN_RING(2); \ 1557 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1558 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1559 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1560 } else { \ 1561 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1562 OUT_RING(R300_RB3D_DC_FLUSH_ALL); \ 1563 } \ 1564 ADVANCE_RING(); \ 1565 } \ 1566 } while (0) 1567 1568 #define RADEON_PURGE_ZCACHE() \ 1569 do { \ 1570 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1571 BEGIN_RING(2); \ 1572 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1573 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1574 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ 1575 } else { \ 1576 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \ 1577 OUT_RING(R300_ZC_FLUSH_ALL); \ 1578 } \ 1579 ADVANCE_RING(); \ 1580 } \ 1581 } while (0) 1582 1583 #endif /* XF86DRI */ 1584 1585 #if defined(XF86DRI) && defined(USE_EXA) 1586 1587 #ifdef XF86DRM_MODE 1588 #define CS_FULL(cs) ((cs)->cdw > 15 * 1024) 1589 #else 1590 #define CS_FULL(cs) FALSE 1591 #endif 1592 1593 #define RADEON_SWITCH_TO_2D() \ 1594 do { \ 1595 uint32_t flush = 0; \ 1596 switch (info->accel_state->engineMode) { \ 1597 case EXA_ENGINEMODE_UNKNOWN: \ 1598 flush = 1; \ 1599 break; \ 1600 case EXA_ENGINEMODE_3D: \ 1601 flush = !info->cs || CS_FULL(info->cs); \ 1602 break; \ 1603 case EXA_ENGINEMODE_2D: \ 1604 flush = info->cs && CS_FULL(info->cs); \ 1605 break; \ 1606 } \ 1607 if (flush) { \ 1608 if (info->cs) \ 1609 radeon_cs_flush_indirect(pScrn); \ 1610 else if (info->directRenderingEnabled) \ 1611 RADEONCPFlushIndirect(pScrn, 1); \ 1612 } \ 1613 info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ 1614 } while (0); 1615 1616 #define RADEON_SWITCH_TO_3D() \ 1617 do { \ 1618 uint32_t flush = 0; \ 1619 switch (info->accel_state->engineMode) { \ 1620 case EXA_ENGINEMODE_UNKNOWN: \ 1621 flush = 1; \ 1622 break; \ 1623 case EXA_ENGINEMODE_2D: \ 1624 flush = !info->cs || CS_FULL(info->cs); \ 1625 break; \ 1626 case EXA_ENGINEMODE_3D: \ 1627 flush = info->cs && CS_FULL(info->cs); \ 1628 break; \ 1629 } \ 1630 if (flush) { \ 1631 if (info->cs) \ 1632 radeon_cs_flush_indirect(pScrn); \ 1633 else if (info->directRenderingEnabled) \ 1634 RADEONCPFlushIndirect(pScrn, 1); \ 1635 } \ 1636 if (!info->accel_state->XInited3D) \ 1637 RADEONInit3DEngine(pScrn); \ 1638 info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ 1639 } while (0); 1640 #else 1641 #define RADEON_SWITCH_TO_2D() 1642 #define RADEON_SWITCH_TO_3D() 1643 #endif 1644 1645 static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1646 { 1647 #ifdef USE_EXA 1648 if (info->useEXA) 1649 exaMarkSync(pScrn->pScreen); 1650 #endif 1651 #ifdef USE_XAA 1652 if (!info->useEXA) 1653 SET_SYNC_FLAG(info->accel_state->accel); 1654 #endif 1655 } 1656 1657 static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1658 { 1659 #ifdef USE_EXA 1660 if (info->useEXA && pScrn->pScreen) 1661 exaWaitSync(pScrn->pScreen); 1662 #endif 1663 #ifdef USE_XAA 1664 if (!info->useEXA && info->accel_state->accel) 1665 info->accel_state->accel->Sync(pScrn); 1666 #endif 1667 } 1668 1669 static __inline__ void radeon_init_timeout(struct timeval *endtime, 1670 unsigned int timeout) 1671 { 1672 gettimeofday(endtime, NULL); 1673 endtime->tv_usec += timeout; 1674 endtime->tv_sec += endtime->tv_usec / 1000000; 1675 endtime->tv_usec %= 1000000; 1676 } 1677 1678 static __inline__ int radeon_timedout(const struct timeval *endtime) 1679 { 1680 struct timeval now; 1681 gettimeofday(&now, NULL); 1682 return now.tv_sec == endtime->tv_sec ? 1683 now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec; 1684 } 1685 1686 enum { 1687 RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000, 1688 RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000, 1689 RADEON_CREATE_PIXMAP_DEPTH = 0x40000000, /* for r200 */ 1690 RADEON_CREATE_PIXMAP_SZBUFFER = 0x80000000, /* for eg */ 1691 }; 1692 1693 #endif /* _RADEON_H_ */ 1694
Indexes created Sun Jul 19 00:25:04 UTC 2026