1 /* $Id: imx23_icoll.c,v 1.6 2025/10/09 06:15:16 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define _INTR_PRIVATE 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: imx23_icoll.c,v 1.6 2025/10/09 06:15:16 skrll Exp $"); 36 37 #include <sys/param.h> 38 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/errno.h> 43 #include <sys/systm.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <arm/pic/picvar.h> 48 49 #include <arm/imx/imx23_icollreg.h> 50 #include <arm/imx/imx23_icollvar.h> 51 #include <arm/imx/imx23var.h> 52 53 #define ICOLL_SOFT_RST_LOOP 455 /* At least 1 us ... */ 54 #define ICOLL_READ(sc, reg) \ 55 bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 56 #define ICOLL_WRITE(sc, reg, val) \ 57 bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 58 59 #define ICOLL_IRQ_REG_SIZE 0x10 60 #define ICOLL_CLR_IRQ(sc, irq) \ 61 ICOLL_WRITE(sc, HW_ICOLL_INTERRUPT0_CLR + \ 62 (irq) * ICOLL_IRQ_REG_SIZE, \ 63 HW_ICOLL_INTERRUPT_ENABLE) 64 #define ICOLL_SET_IRQ(sc, irq) \ 65 ICOLL_WRITE(sc, HW_ICOLL_INTERRUPT0_SET + \ 66 (irq) * ICOLL_IRQ_REG_SIZE, \ 67 HW_ICOLL_INTERRUPT_ENABLE) 68 #define ICOLL_GET_PRIO(sc, irq) \ 69 __SHIFTOUT(ICOLL_READ(sc, HW_ICOLL_INTERRUPT0 + \ 70 (irq) * ICOLL_IRQ_REG_SIZE), \ 71 HW_ICOLL_INTERRUPT_PRIORITY) 72 73 #define PICTOSOFTC(pic) \ 74 ((struct icoll_softc *)((char *)(pic) - \ 75 offsetof(struct icoll_softc, sc_pic))) 76 77 /* 78 * pic callbacks. 79 */ 80 static void icoll_unblock_irqs(struct pic_softc *, size_t, uint32_t); 81 static void icoll_block_irqs(struct pic_softc *, size_t, uint32_t); 82 static int icoll_find_pending_irqs(struct pic_softc *); 83 static void icoll_establish_irq(struct pic_softc *, struct intrsource *); 84 static void icoll_source_name(struct pic_softc *, int, char *, size_t); 85 static void icoll_set_priority(struct pic_softc *, int); 86 87 /* 88 * autoconf(9) callbacks. 89 */ 90 static int icoll_match(device_t, cfdata_t, void *); 91 static void icoll_attach(device_t, device_t, void *); 92 static int icoll_activate(device_t, enum devact); 93 94 const static struct pic_ops icoll_pic_ops = { 95 .pic_unblock_irqs = icoll_unblock_irqs, 96 .pic_block_irqs = icoll_block_irqs, 97 .pic_find_pending_irqs = icoll_find_pending_irqs, 98 .pic_establish_irq = icoll_establish_irq, 99 .pic_source_name = icoll_source_name, 100 .pic_set_priority = icoll_set_priority 101 }; 102 103 /* For IRQ handler. */ 104 static struct icoll_softc *icoll_sc; 105 106 /* 107 * Private to driver. 108 */ 109 static void icoll_reset(struct icoll_softc *); 110 111 CFATTACH_DECL3_NEW(imx23icoll, 112 sizeof(struct icoll_softc), 113 icoll_match, 114 icoll_attach, 115 NULL, 116 icoll_activate, 117 NULL, 118 NULL, 119 0); 120 121 /* 122 * ARM interrupt handler. 123 */ 124 void 125 imx23_intr_dispatch(struct clockframe *frame) 126 { 127 struct cpu_info * const ci = curcpu(); 128 struct pic_softc *pic_sc; 129 int saved_spl; 130 uint8_t irq; 131 uint8_t prio; 132 133 pic_sc = &icoll_sc->sc_pic; 134 135 ci->ci_data.cpu_nintr++; 136 137 /* Save current spl. */ 138 saved_spl = curcpl(); 139 140 /* IRQ to be handled. */ 141 irq = __SHIFTOUT(ICOLL_READ(icoll_sc, HW_ICOLL_STAT), 142 HW_ICOLL_STAT_VECTOR_NUMBER); 143 144 /* Save IRQ's priority. Acknowledge it later. */ 145 prio = ICOLL_GET_PRIO(icoll_sc, irq); 146 147 /* 148 * Notify ICOLL to deassert IRQ before re-enabling the IRQ's. 149 * This is done by writing anything to HW_ICOLL_VECTOR. 150 */ 151 ICOLL_WRITE(icoll_sc, HW_ICOLL_VECTOR, 152 __SHIFTIN(0x3fffffff, HW_ICOLL_VECTOR_IRQVECTOR)); 153 154 /* Bogus IRQ. */ 155 if (irq == 0x7f) { 156 cpsie(I32_bit); 157 ICOLL_WRITE(icoll_sc, HW_ICOLL_LEVELACK, (1<<prio)); 158 cpsid(I32_bit); 159 return; 160 } 161 162 /* Raise the spl to the level of the IRQ. */ 163 if (pic_sc->pic_sources[irq]->is_ipl > ci->ci_cpl) 164 saved_spl = _splraise(pic_sc->pic_sources[irq]->is_ipl); 165 166 /* Call the handler registered for the IRQ. */ 167 cpsie(I32_bit); 168 pic_dispatch(pic_sc->pic_sources[irq], frame); 169 170 /* 171 * Acknowledge the IRQ by writing its priority to HW_ICOLL_LEVELACK. 172 * Interrupts should be enabled. 173 */ 174 ICOLL_WRITE(icoll_sc, HW_ICOLL_LEVELACK, (1<<prio)); 175 cpsid(I32_bit); 176 177 /* Restore the saved spl. */ 178 splx(saved_spl); 179 180 return; 181 } 182 183 /* 184 * pic callbacks. 185 */ 186 static void 187 icoll_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 188 { 189 struct icoll_softc *sc = PICTOSOFTC(pic); 190 uint8_t b; 191 192 for (;;) { 193 b = ffs(irq_mask); 194 if (b == 0) break; 195 b--; /* Zero based index. */ 196 ICOLL_SET_IRQ(sc, irq_base + b); 197 irq_mask &= ~(1<<b); 198 } 199 200 return; 201 } 202 203 static void 204 icoll_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 205 { 206 struct icoll_softc *sc = PICTOSOFTC(pic); 207 uint8_t b; 208 209 for (;;) { 210 b = ffs(irq_mask); 211 if (b == 0) break; 212 b--; /* Zero based index. */ 213 ICOLL_CLR_IRQ(sc, irq_base + b); 214 irq_mask &= ~(1<<b); 215 } 216 217 return; 218 } 219 220 static int 221 icoll_find_pending_irqs(struct pic_softc *pic) 222 { 223 return 0; /* ICOLL HW doesn't provide list of pending interrupts. */ 224 } 225 226 static void 227 icoll_establish_irq(struct pic_softc *pic, struct intrsource *is) 228 { 229 return; /* Nothing to establish. */ 230 } 231 232 static void 233 icoll_source_name(struct pic_softc *pic, int irq, char *is_source, size_t size) 234 { 235 snprintf(is_source, size, "irq %d", irq); 236 } 237 238 /* 239 * Set new interrupt priority level by enabling or disabling IRQ's. 240 */ 241 static void 242 icoll_set_priority(struct pic_softc *pic, int newipl) 243 { 244 struct icoll_softc *sc = PICTOSOFTC(pic); 245 struct intrsource *is; 246 int i; 247 248 register_t psw = DISABLE_INTERRUPT_SAVE(); 249 250 for (i = 0; i < pic->pic_maxsources; i++) { 251 is = pic->pic_sources[i]; 252 if (is == NULL) 253 continue; 254 if (is->is_ipl > newipl) 255 ICOLL_SET_IRQ(sc, pic->pic_irqbase + is->is_irq); 256 else 257 ICOLL_CLR_IRQ(sc, pic->pic_irqbase + is->is_irq); 258 } 259 260 curcpu()->ci_cpl = newipl; 261 262 if ((psw & I32_bit) == 0) { 263 ENABLE_INTERRUPT(); 264 } 265 } 266 267 /* 268 * autoconf(9) callbacks. 269 */ 270 static int 271 icoll_match(device_t parent, cfdata_t match, void *aux) 272 { 273 struct apb_attach_args *aa = aux; 274 275 if ((aa->aa_addr == HW_ICOLL_BASE) && (aa->aa_size == HW_ICOLL_SIZE)) 276 return 1; 277 278 return 0; 279 } 280 281 static void 282 icoll_attach(device_t parent, device_t self, void *aux) 283 { 284 static int icoll_attached = 0; 285 struct icoll_softc *sc = device_private(self); 286 struct apb_attach_args *aa = aux; 287 288 if (icoll_attached) 289 return; 290 291 if (bus_space_map(aa->aa_iot, 292 aa->aa_addr, aa->aa_size, 0, &(sc->sc_hdl))) { 293 aprint_error_dev(self, "unable to map bus space\n"); 294 return; 295 } 296 297 imx23icoll_init(sc, self, aa->aa_iot); 298 299 aprint_normal("\n"); 300 icoll_attached = 1; 301 302 return; 303 } 304 305 void 306 imx23icoll_init(struct icoll_softc *sc, device_t self, bus_space_tag_t iot) 307 { 308 icoll_sc = sc; 309 310 sc->sc_iot = iot; 311 312 sc->sc_pic.pic_maxsources = IRQ_LAST + 1; 313 sc->sc_pic.pic_ops = &icoll_pic_ops; 314 strlcpy(sc->sc_pic.pic_name, device_xname(self), 315 sizeof(sc->sc_pic.pic_name)); 316 317 icoll_reset(sc); 318 pic_add(&sc->sc_pic, 0); 319 } 320 321 static int 322 icoll_activate(device_t self, enum devact act) 323 { 324 return EOPNOTSUPP; 325 } 326 327 /* 328 * Reset the ICOLL block. 329 * 330 * Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block" 331 */ 332 static void 333 icoll_reset(struct icoll_softc *sc) 334 { 335 unsigned int loop; 336 337 /* 338 * Prepare for soft-reset by making sure that SFTRST is not currently 339 * asserted. Also clear CLKGATE so we can wait for its assertion below. 340 */ 341 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_SFTRST); 342 343 /* Wait at least a microsecond for SFTRST to deassert. */ 344 loop = 0; 345 while ((ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_SFTRST) || 346 (loop < ICOLL_SOFT_RST_LOOP)) { 347 loop++; 348 } 349 350 /* Clear CLKGATE so we can wait for its assertion below. */ 351 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_CLKGATE); 352 353 /* Soft-reset the block. */ 354 ICOLL_WRITE(sc, HW_ICOLL_CTRL_SET, HW_ICOLL_CTRL_SFTRST); 355 356 /* Wait until clock is in the gated state. */ 357 while (!(ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_CLKGATE)); 358 359 /* Bring block out of reset. */ 360 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_SFTRST); 361 362 loop = 0; 363 while ((ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_SFTRST) || 364 (loop < ICOLL_SOFT_RST_LOOP)) { 365 loop++; 366 } 367 368 ICOLL_WRITE(sc, HW_ICOLL_CTRL_CLR, HW_ICOLL_CTRL_CLKGATE); 369 370 /* Wait until clock is in the NON-gated state. */ 371 while (ICOLL_READ(sc, HW_ICOLL_CTRL) & HW_ICOLL_CTRL_CLKGATE); 372 373 return; 374 } 375
Indexes created Sat Oct 11 19:10:01 GMT 2025