| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/ |
| mt8167.dtsi | 26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
55 mediatek,infracfg = <&infracfg>;
81 mediatek,infracfg = <&infracfg>;
92 mediatek,infracfg = <&infracfg>;
100 mediatek,infracfg = <&infracfg>
[all...] |
| mt8516.dtsi | 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
188 infracfg: infracfg@10001000 { label
189 compatible = "mediatek,mt8516-infracfg", "syscon";
349 <&infracfg CLK_IFR_I2C0_SEL>,
368 <&infracfg CLK_IFR_I2C1_SEL>,
387 <&infracfg CLK_IFR_I2C2_SEL>
[all...] |
| mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
89 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
205 infracfg: infracfg@10000000 { label
206 compatible = "mediatek,mt7622-infracfg",
217 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
219 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
242 infracfg = <&infracfg>;
251 clocks = <&infracfg CLK_INFRA_IRRX_PD>
[all...] |
| mt2712e.dtsi | 252 infracfg: syscon@10001000 { label
253 compatible = "mediatek,mt2712-infracfg", "syscon";
293 infracfg = <&infracfg>;
319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
330 clocks = <&infracfg CLK_INFRA_M4U>;
347 clocks = <&infracfg CLK_INFRA_M4U>;
661 <&infracfg CLK_INFRA_AO_SPI0>;
|
| mt8183.dtsi | 376 infracfg: syscon@10001000 { label
377 compatible = "mediatek,mt8183-infracfg", "syscon";
429 <&infracfg CLK_INFRA_AUDIO>,
430 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
437 mediatek,infracfg = <&infracfg>;
467 mediatek,infracfg = <&infracfg>;
489 mediatek,infracfg = <&infracfg>;
[all...] |
| mt8173.dtsi | 166 clocks = <&infracfg CLK_INFRA_CA53SEL>,
181 clocks = <&infracfg CLK_INFRA_CA53SEL>,
196 clocks = <&infracfg CLK_INFRA_CA72SEL>,
211 clocks = <&infracfg CLK_INFRA_CA72SEL>,
362 infracfg: power-controller@10001000 { label
363 compatible = "mediatek,mt8173-infracfg", "syscon";
490 mediatek,infracfg = <&infracfg>;
524 mediatek,infracfg = <&infracfg>;
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| mt8135.dtsi | 133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
|
| mt2701.dtsi | 132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
193 clocks = <&infracfg CLK_INFRA_SMI>,
195 <&infracfg CLK_INFRA_SMI>;
223 clocks = <&infracfg CLK_INFRA_M4U>;
435 clocks = <&infracfg CLK_INFRA_AUDIO>,
|
| mt7629.dtsi | 81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
134 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
477 mediatek,infracfg = <&infracfg>;
|
| mt7623.dtsi | 80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
277 infracfg = <&infracfg>;
305 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>
[all...] |
