1 /* $NetBSD: interrupt.h,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */ 2 3 /* 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Kevin Tian <kevin.tian (at) intel.com> 27 * Zhi Wang <zhi.a.wang (at) intel.com> 28 * 29 * Contributors: 30 * Min he <min.he (at) intel.com> 31 * 32 */ 33 34 #ifndef _GVT_INTERRUPT_H_ 35 #define _GVT_INTERRUPT_H_ 36 37 #include <linux/types.h> 38 39 enum intel_gvt_event_type { 40 RCS_MI_USER_INTERRUPT = 0, 41 RCS_DEBUG, 42 RCS_MMIO_SYNC_FLUSH, 43 RCS_CMD_STREAMER_ERR, 44 RCS_PIPE_CONTROL, 45 RCS_L3_PARITY_ERR, 46 RCS_WATCHDOG_EXCEEDED, 47 RCS_PAGE_DIRECTORY_FAULT, 48 RCS_AS_CONTEXT_SWITCH, 49 RCS_MONITOR_BUFF_HALF_FULL, 50 51 VCS_MI_USER_INTERRUPT, 52 VCS_MMIO_SYNC_FLUSH, 53 VCS_CMD_STREAMER_ERR, 54 VCS_MI_FLUSH_DW, 55 VCS_WATCHDOG_EXCEEDED, 56 VCS_PAGE_DIRECTORY_FAULT, 57 VCS_AS_CONTEXT_SWITCH, 58 59 VCS2_MI_USER_INTERRUPT, 60 VCS2_MI_FLUSH_DW, 61 VCS2_AS_CONTEXT_SWITCH, 62 63 BCS_MI_USER_INTERRUPT, 64 BCS_MMIO_SYNC_FLUSH, 65 BCS_CMD_STREAMER_ERR, 66 BCS_MI_FLUSH_DW, 67 BCS_PAGE_DIRECTORY_FAULT, 68 BCS_AS_CONTEXT_SWITCH, 69 70 VECS_MI_USER_INTERRUPT, 71 VECS_MI_FLUSH_DW, 72 VECS_AS_CONTEXT_SWITCH, 73 74 PIPE_A_FIFO_UNDERRUN, 75 PIPE_B_FIFO_UNDERRUN, 76 PIPE_A_CRC_ERR, 77 PIPE_B_CRC_ERR, 78 PIPE_A_CRC_DONE, 79 PIPE_B_CRC_DONE, 80 PIPE_A_ODD_FIELD, 81 PIPE_B_ODD_FIELD, 82 PIPE_A_EVEN_FIELD, 83 PIPE_B_EVEN_FIELD, 84 PIPE_A_LINE_COMPARE, 85 PIPE_B_LINE_COMPARE, 86 PIPE_C_LINE_COMPARE, 87 PIPE_A_VBLANK, 88 PIPE_B_VBLANK, 89 PIPE_C_VBLANK, 90 PIPE_A_VSYNC, 91 PIPE_B_VSYNC, 92 PIPE_C_VSYNC, 93 PRIMARY_A_FLIP_DONE, 94 PRIMARY_B_FLIP_DONE, 95 PRIMARY_C_FLIP_DONE, 96 SPRITE_A_FLIP_DONE, 97 SPRITE_B_FLIP_DONE, 98 SPRITE_C_FLIP_DONE, 99 100 PCU_THERMAL, 101 PCU_PCODE2DRIVER_MAILBOX, 102 103 DPST_PHASE_IN, 104 DPST_HISTOGRAM, 105 GSE, 106 DP_A_HOTPLUG, 107 AUX_CHANNEL_A, 108 PERF_COUNTER, 109 POISON, 110 GTT_FAULT, 111 ERROR_INTERRUPT_COMBINED, 112 113 FDI_RX_INTERRUPTS_TRANSCODER_A, 114 AUDIO_CP_CHANGE_TRANSCODER_A, 115 AUDIO_CP_REQUEST_TRANSCODER_A, 116 FDI_RX_INTERRUPTS_TRANSCODER_B, 117 AUDIO_CP_CHANGE_TRANSCODER_B, 118 AUDIO_CP_REQUEST_TRANSCODER_B, 119 FDI_RX_INTERRUPTS_TRANSCODER_C, 120 AUDIO_CP_CHANGE_TRANSCODER_C, 121 AUDIO_CP_REQUEST_TRANSCODER_C, 122 ERR_AND_DBG, 123 GMBUS, 124 SDVO_B_HOTPLUG, 125 CRT_HOTPLUG, 126 DP_B_HOTPLUG, 127 DP_C_HOTPLUG, 128 DP_D_HOTPLUG, 129 AUX_CHANNEL_B, 130 AUX_CHANNEL_C, 131 AUX_CHANNEL_D, 132 AUDIO_POWER_STATE_CHANGE_B, 133 AUDIO_POWER_STATE_CHANGE_C, 134 AUDIO_POWER_STATE_CHANGE_D, 135 136 INTEL_GVT_EVENT_RESERVED, 137 INTEL_GVT_EVENT_MAX, 138 }; 139 140 struct intel_gvt_irq; 141 struct intel_gvt; 142 struct intel_vgpu; 143 144 typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq, 145 enum intel_gvt_event_type event, struct intel_vgpu *vgpu); 146 147 struct intel_gvt_irq_ops { 148 void (*init_irq)(struct intel_gvt_irq *irq); 149 void (*check_pending_irq)(struct intel_vgpu *vgpu); 150 }; 151 152 /* the list of physical interrupt control register groups */ 153 enum intel_gvt_irq_type { 154 INTEL_GVT_IRQ_INFO_GT, 155 INTEL_GVT_IRQ_INFO_DPY, 156 INTEL_GVT_IRQ_INFO_PCH, 157 INTEL_GVT_IRQ_INFO_PM, 158 159 INTEL_GVT_IRQ_INFO_MASTER, 160 INTEL_GVT_IRQ_INFO_GT0, 161 INTEL_GVT_IRQ_INFO_GT1, 162 INTEL_GVT_IRQ_INFO_GT2, 163 INTEL_GVT_IRQ_INFO_GT3, 164 INTEL_GVT_IRQ_INFO_DE_PIPE_A, 165 INTEL_GVT_IRQ_INFO_DE_PIPE_B, 166 INTEL_GVT_IRQ_INFO_DE_PIPE_C, 167 INTEL_GVT_IRQ_INFO_DE_PORT, 168 INTEL_GVT_IRQ_INFO_DE_MISC, 169 INTEL_GVT_IRQ_INFO_AUD, 170 INTEL_GVT_IRQ_INFO_PCU, 171 172 INTEL_GVT_IRQ_INFO_MAX, 173 }; 174 175 #define INTEL_GVT_IRQ_BITWIDTH 32 176 177 /* device specific interrupt bit definitions */ 178 struct intel_gvt_irq_info { 179 char *name; 180 i915_reg_t reg_base; 181 enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; 182 unsigned long warned; 183 int group; 184 DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); 185 bool has_upstream_irq; 186 }; 187 188 /* per-event information */ 189 struct intel_gvt_event_info { 190 int bit; /* map to register bit */ 191 int policy; /* forwarding policy */ 192 struct intel_gvt_irq_info *info; /* register info */ 193 gvt_event_virt_handler_t v_handler; /* for v_event */ 194 }; 195 196 struct intel_gvt_irq_map { 197 int up_irq_group; 198 int up_irq_bit; 199 int down_irq_group; 200 u32 down_irq_bitmask; 201 }; 202 203 struct intel_gvt_vblank_timer { 204 struct hrtimer timer; 205 u64 period; 206 }; 207 208 /* structure containing device specific IRQ state */ 209 struct intel_gvt_irq { 210 struct intel_gvt_irq_ops *ops; 211 struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX]; 212 DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX); 213 struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX]; 214 DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX); 215 struct intel_gvt_irq_map *irq_map; 216 struct intel_gvt_vblank_timer vblank_timer; 217 }; 218 219 int intel_gvt_init_irq(struct intel_gvt *gvt); 220 void intel_gvt_clean_irq(struct intel_gvt *gvt); 221 222 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 223 enum intel_gvt_event_type event); 224 225 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 226 void *p_data, unsigned int bytes); 227 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 228 unsigned int reg, void *p_data, unsigned int bytes); 229 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 230 unsigned int reg, void *p_data, unsigned int bytes); 231 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 232 unsigned int reg, void *p_data, unsigned int bytes); 233 234 int gvt_ring_id_to_pipe_control_notify_event(int ring_id); 235 int gvt_ring_id_to_mi_flush_dw_event(int ring_id); 236 int gvt_ring_id_to_mi_user_interrupt_event(int ring_id); 237 238 #endif /* _GVT_INTERRUPT_H_ */ 239
Indexes created Sun Sep 21 16:09:51 GMT 2025