1 /* $NetBSD: pci_machdep.c,v 1.65 2024/09/07 06:17:38 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.65 2024/09/07 06:17:38 andvar Exp $"); 36 37 #include "opt_mbtype.h" 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/time.h> 42 #include <sys/systm.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/kmem.h> 46 47 #define _ATARI_BUS_DMA_PRIVATE 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/cpu.h> 57 #include <machine/iomap.h> 58 #include <machine/mfp.h> 59 60 #include <atari/atari/device.h> 61 #include <atari/pci/pci_vga.h> 62 63 /* 64 * Sizes of pci memory and I/O area. 65 */ 66 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 67 #define PCI_IO_END 0x10000000 /* 256 MByte */ 68 69 /* 70 * We preserve some space at the begin of the pci area for 32BIT_1M 71 * devices and standard vga. 72 */ 73 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 74 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 75 I/O addresses up to 0xffff) */ 76 77 /* 78 * PCI memory and IO should be aligned according to these masks 79 */ 80 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 81 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 82 83 /* 84 * Convert a PCI 'device' number to a slot number. 85 */ 86 #define DEV2SLOT(dev) (3 - dev) 87 88 /* 89 * Struct to hold the memory and I/O datas of the pci devices 90 */ 91 struct pci_memreg { 92 LIST_ENTRY(pci_memreg) link; 93 int dev; 94 pcitag_t tag; 95 pcireg_t reg, address, mask; 96 uint32_t size; 97 uint32_t csr; 98 }; 99 100 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 101 102 /* 103 * Entry points for PCI DMA. Use only the 'standard' functions. 104 */ 105 int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 106 bus_size_t, int, bus_dmamap_t *); 107 struct atari_bus_dma_tag pci_bus_dma_tag = { 108 0, 109 #if defined(_ATARIHW_) 110 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */ 111 #else 112 0, 113 #endif 114 _bus_dmamap_create, 115 _bus_dmamap_destroy, 116 _bus_dmamap_load, 117 _bus_dmamap_load_mbuf, 118 _bus_dmamap_load_uio, 119 _bus_dmamap_load_raw, 120 _bus_dmamap_unload, 121 _bus_dmamap_sync, 122 }; 123 124 int ataripcibusprint(void *, const char *); 125 int pcibusmatch(device_t, cfdata_t, void *); 126 void pcibusattach(device_t, device_t, void *); 127 128 static void enable_pci_devices(void); 129 static void insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem); 130 static int overlap_pci_areas(struct pci_memreg *p, 131 struct pci_memreg *self, u_int addr, u_int size, u_int what); 132 133 CFATTACH_DECL_NEW(pcib, 0, 134 pcibusmatch, pcibusattach, NULL, NULL); 135 136 /* 137 * We need some static storage to probe pci-busses for VGA cards during 138 * early console init. 139 */ 140 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 141 142 int 143 pcibusmatch(device_t parent, cfdata_t cf, void *aux) 144 { 145 static int nmatched = 0; 146 147 if (strcmp((char *)aux, "pcib")) 148 return 0; /* Wrong number... */ 149 150 if (atari_realconfig == 0) 151 return 1; 152 153 if ((machineid & (ATARI_HADES|ATARI_MILAN)) != 0) { 154 /* 155 * Both Hades and Milan have only one pci bus 156 */ 157 if (nmatched) 158 return 0; 159 nmatched++; 160 return 1; 161 } 162 return 0; 163 } 164 165 void 166 pcibusattach(device_t parent, device_t self, void *aux) 167 { 168 struct pcibus_attach_args pba; 169 170 pba.pba_pc = NULL; 171 pba.pba_bus = 0; 172 pba.pba_bridgetag = NULL; 173 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 174 pba.pba_dmat = &pci_bus_dma_tag; 175 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 176 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]); 177 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 178 printf("leb_alloc_bus_space_tag failed!\n"); 179 return; 180 } 181 pba.pba_iot->base = PCI_IO_PHYS; 182 pba.pba_memt->base = PCI_MEM_PHYS; 183 184 if (self == NULL) { 185 /* 186 * Scan the bus for a VGA-card that we support. If we 187 * find one, try to initialize it to a 'standard' text 188 * mode (80x25). 189 */ 190 check_for_vga(pba.pba_iot, pba.pba_memt); 191 return; 192 } 193 194 enable_pci_devices(); 195 196 #if defined(_ATARIHW_) 197 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 198 #endif 199 200 printf("\n"); 201 202 config_found(self, &pba, ataripcibusprint, CFARGS_NONE); 203 } 204 205 int 206 ataripcibusprint(void *aux, const char *name) 207 { 208 209 if (name == NULL) 210 return UNCONF; 211 return QUIET; 212 } 213 214 void 215 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 216 { 217 } 218 219 /* 220 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 221 * We only disable all devices here. Memory and I/O enabling is done 222 * later at pcibusattach. 223 */ 224 void 225 init_pci_bus(void) 226 { 227 pci_chipset_tag_t pc = NULL; /* XXX */ 228 pcitag_t tag; 229 pcireg_t csr; 230 int device, maxndevs; 231 uint32_t id; 232 233 tag = 0; 234 id = 0; 235 236 maxndevs = pci_bus_maxdevs(pc, 0); 237 238 for (device = 0; device < maxndevs; device++) { 239 240 tag = pci_make_tag(pc, 0, device, 0); 241 id = pci_conf_read(pc, tag, PCI_ID_REG); 242 if (id == 0 || id == 0xffffffff) 243 continue; 244 245 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 246 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 247 csr &= ~PCI_COMMAND_MASTER_ENABLE; 248 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 249 } 250 } 251 252 /* 253 * insert a new element in an existing list that the ID's (size in struct 254 * pci_memreg) are sorted. 255 */ 256 static void 257 insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem) 258 { 259 struct pci_memreg *p, *q; 260 261 p = LIST_FIRST(head); 262 q = NULL; 263 264 for (; p != NULL && p->size < elem->size; 265 q = p, p = LIST_NEXT(p, link)) 266 ; 267 268 if (q == NULL) { 269 LIST_INSERT_HEAD(head, elem, link); 270 } else { 271 LIST_INSERT_AFTER(q, elem, link); 272 } 273 } 274 275 /* 276 * Test if a new selected area overlaps with an already (probably preselected) 277 * pci area. 278 */ 279 static int 280 overlap_pci_areas(struct pci_memreg *p, struct pci_memreg *self, u_int addr, 281 u_int size, u_int what) 282 { 283 struct pci_memreg *q; 284 285 if (p == NULL) 286 return 0; 287 288 q = p; 289 while (q != NULL) { 290 if ((q != self) && (q->csr & what)) { 291 if ((addr >= q->address) && 292 (addr < (q->address + q->size))) { 293 #ifdef DEBUG_PCI_MACHDEP 294 printf("\noverlap area dev %d reg 0x%02x " 295 "with dev %d reg 0x%02x", 296 self->dev, self->reg, q->dev, q->reg); 297 #endif 298 return 1; 299 } 300 if ((q->address >= addr) && 301 (q->address < (addr + size))) { 302 #ifdef DEBUG_PCI_MACHDEP 303 printf("\noverlap area dev %d reg 0x%02x " 304 "with dev %d reg 0x%02x", 305 self->dev, self->reg, q->dev, q->reg); 306 #endif 307 return 1; 308 } 309 } 310 q = LIST_NEXT(q, link); 311 } 312 return 0; 313 } 314 315 /* 316 * Enable memory and I/O on pci devices. Care about already enabled devices 317 * (probably by the console driver). 318 * 319 * The idea behind the following code is: 320 * We build a by sizes sorted list of the requirements of the different 321 * pci devices. After that we choose the start addresses of that areas 322 * in such a way that they are placed as closed as possible together. 323 */ 324 static void 325 enable_pci_devices(void) 326 { 327 PCI_MEMREG memlist; 328 PCI_MEMREG iolist; 329 struct pci_memreg *p, *q; 330 int dev, reg; 331 uint32_t id, class; 332 pcitag_t tag; 333 pcireg_t csr, address, mask; 334 pci_chipset_tag_t pc; 335 int sizecnt, membase_1m; 336 337 pc = 0; 338 csr = 0; 339 tag = 0; 340 341 LIST_INIT(&memlist); 342 LIST_INIT(&iolist); 343 344 /* 345 * first step: go through all devices and gather memory and I/O 346 * sizes 347 */ 348 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 349 350 tag = pci_make_tag(pc, 0, dev, 0); 351 id = pci_conf_read(pc, tag, PCI_ID_REG); 352 if (id == 0 || id == 0xffffffff) 353 continue; 354 355 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 356 357 /* 358 * special case: if a display card is found and memory is 359 * enabled preserve 128k at 0xa0000 as vga memory. 360 * XXX: if a display card is found without being enabled, 361 * leave it alone! You will usually only create conflicts 362 * by enabling it. 363 */ 364 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 365 switch (PCI_CLASS(class)) { 366 case PCI_CLASS_PREHISTORIC: 367 case PCI_CLASS_DISPLAY: 368 if (csr & (PCI_COMMAND_MEM_ENABLE | 369 PCI_COMMAND_MASTER_ENABLE)) { 370 p = kmem_zalloc(sizeof(struct pci_memreg), 371 KM_SLEEP); 372 p->dev = dev; 373 p->csr = csr; 374 p->tag = tag; 375 p->reg = 0; /* there is no register 376 about this */ 377 p->size = 0x20000; /* 128kByte */ 378 p->mask = 0xfffe0000; 379 p->address = 0xa0000; 380 381 insert_into_list(&memlist, p); 382 } else 383 continue; 384 } 385 386 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 387 address = pci_conf_read(pc, tag, reg); 388 pci_conf_write(pc, tag, reg, 0xffffffff); 389 mask = pci_conf_read(pc, tag, reg); 390 pci_conf_write(pc, tag, reg, address); 391 if (mask == 0) 392 continue; /* Register unused */ 393 394 p = kmem_zalloc(sizeof(struct pci_memreg), 395 KM_SLEEP); 396 p->dev = dev; 397 p->csr = csr; 398 p->tag = tag; 399 p->reg = reg; 400 p->mask = mask; 401 p->address = 0; 402 403 if ((mask & PCI_MAPREG_TYPE_IO) != 0) { 404 p->size = PCI_MAPREG_IO_SIZE(mask); 405 406 /* 407 * Align IO if necessary 408 */ 409 if (p->size < PCI_MAPREG_IO_SIZE( 410 PCI_MACHDEP_IO_ALIGN_MASK)) { 411 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 412 p->size = PCI_MAPREG_IO_SIZE(p->mask); 413 } 414 415 /* 416 * if I/O is already enabled 417 * (probably by the console driver) 418 * save the address in order to take care 419 * about it later. 420 */ 421 if ((csr & PCI_COMMAND_IO_ENABLE) != 0) 422 p->address = address; 423 424 insert_into_list(&iolist, p); 425 } else { 426 p->size = PCI_MAPREG_MEM_SIZE(mask); 427 428 /* 429 * Align memory if necessary 430 */ 431 if (p->size < PCI_MAPREG_IO_SIZE( 432 PCI_MACHDEP_MEM_ALIGN_MASK)) { 433 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 434 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 435 } 436 437 /* 438 * if memory is already enabled 439 * (probably by the console driver) 440 * save the address in order to take care 441 * about it later. 442 */ 443 if ((csr & PCI_COMMAND_MEM_ENABLE) != 0) 444 p->address = address; 445 446 insert_into_list(&memlist, p); 447 448 if (PCI_MAPREG_MEM_TYPE(mask) == 449 PCI_MAPREG_MEM_TYPE_64BIT) 450 reg++; 451 } 452 } 453 454 #if defined(_ATARIHW_) 455 /* 456 * Both interrupt pin & line are set to the device (== slot) 457 * number. This makes sense on the atari Hades because the 458 * individual slots are hard-wired to a specific MFP-pin. 459 */ 460 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 461 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 462 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 463 #else 464 /* 465 * On the Milan, we accept the BIOS's choice. 466 */ 467 /* 468 * ..except the secondary IDE interrupt that 469 * the BIOS doesn't setup. 470 */ 471 #define PIIX_PCIB_MBIRQ0 0x70 472 if ((PCI_VENDOR(id) == PCI_VENDOR_INTEL) && 473 (PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_82371FB_ISA)) { 474 /* 475 * Set Interrupt Routing for MBIRQ0 to IRQ15. 476 * Note Milan's ROM bootloader v1.2 and v1.4 477 * incorrectly set MBIRQ0 to IRQ14 (not 15) 478 * and unused MBIRQ1 to IRQ 15, 479 * so explicitly disable MBIRQ1. 480 */ 481 csr = pci_conf_read(pc, tag, PIIX_PCIB_MBIRQ0); 482 csr &= ~0x0000ffff; 483 /* MBIRQ1: disable, MBIRQ0: IRQ15 */ 484 csr |= 0x0000800f; 485 pci_conf_write(pc, tag, PIIX_PCIB_MBIRQ0, csr); 486 #ifdef DEBUG_PCI_MACHDEP 487 printf("\npcib0: enable and route MBIRQ0 to irq 15\n"); 488 #endif 489 } 490 #endif 491 } 492 493 /* 494 * second step: calculate the memory and I/O addresses beginning from 495 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 496 * 497 * begin with memory list 498 */ 499 500 address = PCI_MEM_START; 501 sizecnt = 0; 502 membase_1m = 0; 503 p = LIST_FIRST(&memlist); 504 while (p != NULL) { 505 if ((p->csr & PCI_COMMAND_MEM_ENABLE) == 0) { 506 if (PCI_MAPREG_MEM_TYPE(p->mask) == 507 PCI_MAPREG_MEM_TYPE_32BIT_1M) { 508 if (p->size > membase_1m) 509 membase_1m = p->size; 510 do { 511 p->address = membase_1m; 512 membase_1m += p->size; 513 } while (overlap_pci_areas(LIST_FIRST(&memlist), 514 p, p->address, p->size, 515 PCI_COMMAND_MEM_ENABLE)); 516 if (membase_1m > 0x00100000) { 517 /* 518 * Should we panic here? 519 */ 520 printf("\npcibus0: dev %d reg %d:" 521 " memory not configured", 522 p->dev, p->reg); 523 p->reg = 0; 524 } 525 } else { 526 if (sizecnt && (p->size > sizecnt)) 527 sizecnt = 528 ((p->size + sizecnt) & p->mask) & 529 PCI_MAPREG_MEM_ADDR_MASK; 530 if (sizecnt > address) { 531 address = sizecnt; 532 sizecnt = 0; 533 } 534 535 do { 536 p->address = address + sizecnt; 537 sizecnt += p->size; 538 } while (overlap_pci_areas(LIST_FIRST(&memlist), 539 p, p->address, p->size, 540 PCI_COMMAND_MEM_ENABLE)); 541 542 if ((address + sizecnt) > PCI_MEM_END) { 543 /* 544 * Should we panic here? 545 */ 546 printf("\npcibus0: dev %d reg %d:" 547 " memory not configured", 548 p->dev, p->reg); 549 p->reg = 0; 550 } 551 } 552 if (p->reg > 0) { 553 pci_conf_write(pc, p->tag, p->reg, p->address); 554 csr = pci_conf_read(pc, p->tag, 555 PCI_COMMAND_STATUS_REG); 556 csr |= PCI_COMMAND_MEM_ENABLE | 557 PCI_COMMAND_MASTER_ENABLE; 558 pci_conf_write(pc, p->tag, 559 PCI_COMMAND_STATUS_REG, csr); 560 p->csr = csr; 561 } 562 } 563 p = LIST_NEXT(p, link); 564 } 565 566 /* 567 * now the I/O list 568 */ 569 570 address = PCI_IO_START; 571 sizecnt = 0; 572 p = LIST_FIRST(&iolist); 573 while (p != NULL) { 574 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 575 576 if (sizecnt && (p->size > sizecnt)) 577 sizecnt = ((p->size + sizecnt) & p->mask) & 578 PCI_MAPREG_IO_ADDR_MASK; 579 if (sizecnt > address) { 580 address = sizecnt; 581 sizecnt = 0; 582 } 583 584 do { 585 p->address = address + sizecnt; 586 sizecnt += p->size; 587 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, 588 p->address, p->size, PCI_COMMAND_IO_ENABLE)); 589 590 if ((address + sizecnt) > PCI_IO_END) { 591 /* 592 * Should we panic here? 593 */ 594 printf("\npcibus0: dev %d reg %d:" 595 " io not configured", 596 p->dev, p->reg); 597 } else { 598 pci_conf_write(pc, p->tag, p->reg, p->address); 599 csr = pci_conf_read(pc, p->tag, 600 PCI_COMMAND_STATUS_REG); 601 csr |= PCI_COMMAND_IO_ENABLE | 602 PCI_COMMAND_MASTER_ENABLE; 603 pci_conf_write(pc, p->tag, 604 PCI_COMMAND_STATUS_REG, csr); 605 p->csr = csr; 606 } 607 } 608 p = LIST_NEXT(p, link); 609 } 610 611 #ifdef DEBUG_PCI_MACHDEP 612 printf("\nI/O List:\n"); 613 p = LIST_FIRST(&iolist); 614 615 while (p != NULL) { 616 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", 617 p->dev, p->reg, p->size, p->address); 618 p = LIST_NEXT(p, link); 619 } 620 printf("\nMemlist:"); 621 p = LIST_FIRST(&memlist); 622 623 while (p != NULL) { 624 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", 625 p->dev, p->reg, p->size, p->address); 626 p = LIST_NEXT(p, link); 627 } 628 #endif 629 630 /* 631 * Free the lists 632 */ 633 p = LIST_FIRST(&iolist); 634 while (p != NULL) { 635 q = p; 636 LIST_REMOVE(q, link); 637 kmem_free(p, sizeof(*p)); 638 p = LIST_FIRST(&iolist); 639 } 640 p = LIST_FIRST(&memlist); 641 while (p != NULL) { 642 q = p; 643 LIST_REMOVE(q, link); 644 kmem_free(p, sizeof(*p)); 645 p = LIST_FIRST(&memlist); 646 } 647 } 648 649 pcitag_t 650 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 651 { 652 653 return (bus << 16) | (device << 11) | (function << 8); 654 } 655 656 void 657 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 658 { 659 660 if (bp != NULL) 661 *bp = (tag >> 16) & 0xff; 662 if (dp != NULL) 663 *dp = (tag >> 11) & 0x1f; 664 if (fp != NULL) 665 *fp = (tag >> 8) & 0x7; 666 } 667 668 int 669 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 670 { 671 int line = pa->pa_intrline; 672 673 #if defined(_MILANHW_) 674 /* 675 * On the Hades, the 'pin' info is useless. 676 */ 677 { 678 int pin = pa->pa_intrpin; 679 680 if (pin == 0) { 681 /* No IRQ used. */ 682 goto bad; 683 } 684 if (pin > PCI_INTERRUPT_PIN_MAX) { 685 printf("pci_intr_map: bad interrupt pin %d\n", pin); 686 goto bad; 687 } 688 } 689 #endif /* _MILANHW_ */ 690 691 /* 692 * According to the PCI-spec, 255 means `unknown' or `no connection'. 693 * Interpret this as 'no interrupt assigned'. 694 */ 695 if (line == 255) 696 goto bad; 697 698 /* 699 * Values are pretty useless on the Hades since all interrupt 700 * lines for a card are tied together and hardwired to a 701 * specific TT-MFP I/O port. 702 * On the Milan, they are tied to the ICU. 703 */ 704 #if defined(_MILANHW_) 705 if (line >= 16) { 706 printf("pci_intr_map: bad interrupt line %d\n", line); 707 goto bad; 708 } 709 if (line == 2) { 710 printf("pci_intr_map: changed line 2 to line 9\n"); 711 line = 9; 712 } 713 /* Assume line == 0 means unassigned */ 714 if (line == 0) 715 goto bad; 716 #endif 717 *ihp = line; 718 return 0; 719 720 bad: 721 *ihp = -1; 722 return 1; 723 } 724 725 const char * 726 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 727 size_t len) 728 { 729 730 if (ih == -1) 731 panic("pci_intr_string: bogus handle 0x%x", ih); 732 733 snprintf(buf, len, "irq %d", ih); 734 return buf; 735 } 736 737 const struct evcnt * 738 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 739 { 740 741 /* XXX for now, no evcnt parent reported */ 742 return NULL; 743 } 744
Indexes created Mon Sep 22 05:09:51 GMT 2025