1 /* $NetBSD: intel_combo_phy.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: MIT 4 /* 5 * Copyright 2018 Intel Corporation 6 */ 7 8 #include <sys/cdefs.h> 9 __KERNEL_RCSID(0, "$NetBSD: intel_combo_phy.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $"); 10 11 #include "intel_combo_phy.h" 12 #include "intel_display_types.h" 13 14 #define for_each_combo_phy(__dev_priv, __phy) \ 15 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 16 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 17 18 #define for_each_combo_phy_reverse(__dev_priv, __phy) \ 19 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ 20 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 21 22 enum { 23 PROCMON_0_85V_DOT_0, 24 PROCMON_0_95V_DOT_0, 25 PROCMON_0_95V_DOT_1, 26 PROCMON_1_05V_DOT_0, 27 PROCMON_1_05V_DOT_1, 28 }; 29 30 static const struct cnl_procmon { 31 u32 dw1, dw9, dw10; 32 } cnl_procmon_values[] = { 33 [PROCMON_0_85V_DOT_0] = 34 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 35 [PROCMON_0_95V_DOT_0] = 36 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 37 [PROCMON_0_95V_DOT_1] = 38 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 39 [PROCMON_1_05V_DOT_0] = 40 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 41 [PROCMON_1_05V_DOT_1] = 42 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 43 }; 44 45 /* 46 * CNL has just one set of registers, while gen11 has a set for each combo PHY. 47 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we 48 * call the ICL macros even though the function has CNL on its name. 49 */ 50 static const struct cnl_procmon * 51 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) 52 { 53 const struct cnl_procmon *procmon; 54 u32 val; 55 56 val = I915_READ(ICL_PORT_COMP_DW3(phy)); 57 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 58 default: 59 MISSING_CASE(val); 60 /* fall through */ 61 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 62 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 63 break; 64 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 65 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 66 break; 67 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 68 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 69 break; 70 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 71 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 72 break; 73 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 74 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 75 break; 76 } 77 78 return procmon; 79 } 80 81 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 82 enum phy phy) 83 { 84 const struct cnl_procmon *procmon; 85 u32 val; 86 87 procmon = cnl_get_procmon_ref_values(dev_priv, phy); 88 89 val = I915_READ(ICL_PORT_COMP_DW1(phy)); 90 val &= ~((0xff << 16) | 0xff); 91 val |= procmon->dw1; 92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val); 93 94 I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); 95 I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); 96 } 97 98 static bool check_phy_reg(struct drm_i915_private *dev_priv, 99 enum phy phy, i915_reg_t reg, u32 mask, 100 u32 expected_val) 101 { 102 u32 val = I915_READ(reg); 103 104 if ((val & mask) != expected_val) { 105 DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: " 106 "current %08x mask %08x expected %08x\n", 107 phy_name(phy), 108 reg.reg, val, mask, expected_val); 109 return false; 110 } 111 112 return true; 113 } 114 115 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, 116 enum phy phy) 117 { 118 const struct cnl_procmon *procmon; 119 bool ret; 120 121 procmon = cnl_get_procmon_ref_values(dev_priv, phy); 122 123 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), 124 (0xff << 16) | 0xff, procmon->dw1); 125 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), 126 -1U, procmon->dw9); 127 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), 128 -1U, procmon->dw10); 129 130 return ret; 131 } 132 133 static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) 134 { 135 return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && 136 (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT); 137 } 138 139 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) 140 { 141 enum phy phy = PHY_A; 142 bool ret; 143 144 if (!cnl_combo_phy_enabled(dev_priv)) 145 return false; 146 147 ret = cnl_verify_procmon_ref_values(dev_priv, phy); 148 149 ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, 150 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); 151 152 return ret; 153 } 154 155 static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) 156 { 157 u32 val; 158 159 val = I915_READ(CHICKEN_MISC_2); 160 val &= ~CNL_COMP_PWR_DOWN; 161 I915_WRITE(CHICKEN_MISC_2, val); 162 163 /* Dummy PORT_A to get the correct CNL register from the ICL macro */ 164 cnl_set_procmon_ref_values(dev_priv, PHY_A); 165 166 val = I915_READ(CNL_PORT_COMP_DW0); 167 val |= COMP_INIT; 168 I915_WRITE(CNL_PORT_COMP_DW0, val); 169 170 val = I915_READ(CNL_PORT_CL1CM_DW5); 171 val |= CL_POWER_DOWN_ENABLE; 172 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 173 } 174 175 static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) 176 { 177 u32 val; 178 179 if (!cnl_combo_phy_verify_state(dev_priv)) 180 DRM_WARN("Combo PHY HW state changed unexpectedly.\n"); 181 182 val = I915_READ(CHICKEN_MISC_2); 183 val |= CNL_COMP_PWR_DOWN; 184 I915_WRITE(CHICKEN_MISC_2, val); 185 } 186 187 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, 188 enum phy phy) 189 { 190 /* The PHY C added by EHL has no PHY_MISC register */ 191 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) 192 return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; 193 else 194 return !(I915_READ(ICL_PHY_MISC(phy)) & 195 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && 196 (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT); 197 } 198 199 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, 200 enum phy phy) 201 { 202 bool ret; 203 204 if (!icl_combo_phy_enabled(dev_priv, phy)) 205 return false; 206 207 ret = cnl_verify_procmon_ref_values(dev_priv, phy); 208 209 if (phy == PHY_A) 210 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), 211 IREFGEN, IREFGEN); 212 213 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), 214 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); 215 216 return ret; 217 } 218 219 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, 220 enum phy phy, bool is_dsi, 221 int lane_count, bool lane_reversal) 222 { 223 u8 lane_mask; 224 u32 val; 225 226 if (is_dsi) { 227 WARN_ON(lane_reversal); 228 229 switch (lane_count) { 230 case 1: 231 lane_mask = PWR_DOWN_LN_3_1_0; 232 break; 233 case 2: 234 lane_mask = PWR_DOWN_LN_3_1; 235 break; 236 case 3: 237 lane_mask = PWR_DOWN_LN_3; 238 break; 239 default: 240 MISSING_CASE(lane_count); 241 /* fall-through */ 242 case 4: 243 lane_mask = PWR_UP_ALL_LANES; 244 break; 245 } 246 } else { 247 switch (lane_count) { 248 case 1: 249 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : 250 PWR_DOWN_LN_3_2_1; 251 break; 252 case 2: 253 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : 254 PWR_DOWN_LN_3_2; 255 break; 256 default: 257 MISSING_CASE(lane_count); 258 /* fall-through */ 259 case 4: 260 lane_mask = PWR_UP_ALL_LANES; 261 break; 262 } 263 } 264 265 val = I915_READ(ICL_PORT_CL_DW10(phy)); 266 val &= ~PWR_DOWN_LN_MASK; 267 val |= lane_mask << PWR_DOWN_LN_SHIFT; 268 I915_WRITE(ICL_PORT_CL_DW10(phy), val); 269 } 270 271 static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) 272 { 273 bool ddi_a_present = i915->vbt.ddi_port_info[PORT_A].child != NULL; 274 bool ddi_d_present = i915->vbt.ddi_port_info[PORT_D].child != NULL; 275 bool dsi_present = intel_bios_is_dsi_present(i915, NULL); 276 277 /* 278 * VBT's 'dvo port' field for child devices references the DDI, not 279 * the PHY. So if combo PHY A is wired up to drive an external 280 * display, we should see a child device present on PORT_D and 281 * nothing on PORT_A and no DSI. 282 */ 283 if (ddi_d_present && !ddi_a_present && !dsi_present) 284 return val | ICL_PHY_MISC_MUX_DDID; 285 286 /* 287 * If we encounter a VBT that claims to have an external display on 288 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message 289 * in the log and let the internal display win. 290 */ 291 if (ddi_d_present) 292 DRM_ERROR("VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); 293 294 return val & ~ICL_PHY_MISC_MUX_DDID; 295 } 296 297 static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 298 { 299 enum phy phy; 300 301 for_each_combo_phy(dev_priv, phy) { 302 u32 val; 303 304 if (icl_combo_phy_verify_state(dev_priv, phy)) { 305 DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n", 306 phy_name(phy)); 307 continue; 308 } 309 310 /* 311 * Although EHL adds a combo PHY C, there's no PHY_MISC 312 * register for it and no need to program the 313 * DE_IO_COMP_PWR_DOWN setting on PHY C. 314 */ 315 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) 316 goto skip_phy_misc; 317 318 /* 319 * EHL's combo PHY A can be hooked up to either an external 320 * display (via DDI-D) or an internal display (via DDI-A or 321 * the DSI DPHY). This is a motherboard design decision that 322 * can't be changed on the fly, so initialize the PHY's mux 323 * based on whether our VBT indicates the presence of any 324 * "internal" child devices. 325 */ 326 val = I915_READ(ICL_PHY_MISC(phy)); 327 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) 328 val = ehl_combo_phy_a_mux(dev_priv, val); 329 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 330 I915_WRITE(ICL_PHY_MISC(phy), val); 331 332 skip_phy_misc: 333 cnl_set_procmon_ref_values(dev_priv, phy); 334 335 if (phy == PHY_A) { 336 val = I915_READ(ICL_PORT_COMP_DW8(phy)); 337 val |= IREFGEN; 338 I915_WRITE(ICL_PORT_COMP_DW8(phy), val); 339 } 340 341 val = I915_READ(ICL_PORT_COMP_DW0(phy)); 342 val |= COMP_INIT; 343 I915_WRITE(ICL_PORT_COMP_DW0(phy), val); 344 345 val = I915_READ(ICL_PORT_CL_DW5(phy)); 346 val |= CL_POWER_DOWN_ENABLE; 347 I915_WRITE(ICL_PORT_CL_DW5(phy), val); 348 } 349 } 350 351 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) 352 { 353 enum phy phy; 354 355 for_each_combo_phy_reverse(dev_priv, phy) { 356 u32 val; 357 358 if (phy == PHY_A && 359 !icl_combo_phy_verify_state(dev_priv, phy)) 360 DRM_WARN("Combo PHY %c HW state changed unexpectedly\n", 361 phy_name(phy)); 362 363 /* 364 * Although EHL adds a combo PHY C, there's no PHY_MISC 365 * register for it and no need to program the 366 * DE_IO_COMP_PWR_DOWN setting on PHY C. 367 */ 368 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) 369 goto skip_phy_misc; 370 371 val = I915_READ(ICL_PHY_MISC(phy)); 372 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 373 I915_WRITE(ICL_PHY_MISC(phy), val); 374 375 skip_phy_misc: 376 val = I915_READ(ICL_PORT_COMP_DW0(phy)); 377 val &= ~COMP_INIT; 378 I915_WRITE(ICL_PORT_COMP_DW0(phy), val); 379 } 380 } 381 382 void intel_combo_phy_init(struct drm_i915_private *i915) 383 { 384 if (INTEL_GEN(i915) >= 11) 385 icl_combo_phys_init(i915); 386 else if (IS_CANNONLAKE(i915)) 387 cnl_combo_phys_init(i915); 388 } 389 390 void intel_combo_phy_uninit(struct drm_i915_private *i915) 391 { 392 if (INTEL_GEN(i915) >= 11) 393 icl_combo_phys_uninit(i915); 394 else if (IS_CANNONLAKE(i915)) 395 cnl_combo_phys_uninit(i915); 396 } 397
Indexes created Sat Sep 20 22:09:52 GMT 2025