1 /* $NetBSD: i915_cmd_parser.c,v 1.28 2021/12/19 12:25:37 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Brad Volkin <bradley.d.volkin (at) intel.com> 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: i915_cmd_parser.c,v 1.28 2021/12/19 12:25:37 riastradh Exp $"); 32 33 #include <linux/bitmap.h> 34 35 #include "gt/intel_engine.h" 36 37 #include "i915_drv.h" 38 #include "i915_memcpy.h" 39 40 /** 41 * DOC: batch buffer command parser 42 * 43 * Motivation: 44 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 45 * require userspace code to submit batches containing commands such as 46 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 47 * generations of the hardware will noop these commands in "unsecure" batches 48 * (which includes all userspace batches submitted via i915) even though the 49 * commands may be safe and represent the intended programming model of the 50 * device. 51 * 52 * The software command parser is similar in operation to the command parsing 53 * done in hardware for unsecure batches. However, the software parser allows 54 * some operations that would be noop'd by hardware, if the parser determines 55 * the operation is safe, and submits the batch as "secure" to prevent hardware 56 * parsing. 57 * 58 * Threats: 59 * At a high level, the hardware (and software) checks attempt to prevent 60 * granting userspace undue privileges. There are three categories of privilege. 61 * 62 * First, commands which are explicitly defined as privileged or which should 63 * only be used by the kernel driver. The parser rejects such commands 64 * 65 * Second, commands which access registers. To support correct/enhanced 66 * userspace functionality, particularly certain OpenGL extensions, the parser 67 * provides a whitelist of registers which userspace may safely access 68 * 69 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 70 * The parser always rejects such commands. 71 * 72 * The majority of the problematic commands fall in the MI_* range, with only a 73 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW). 74 * 75 * Implementation: 76 * Each engine maintains tables of commands and registers which the parser 77 * uses in scanning batch buffers submitted to that engine. 78 * 79 * Since the set of commands that the parser must check for is significantly 80 * smaller than the number of commands supported, the parser tables contain only 81 * those commands required by the parser. This generally works because command 82 * opcode ranges have standard command length encodings. So for commands that 83 * the parser does not need to check, it can easily skip them. This is 84 * implemented via a per-engine length decoding vfunc. 85 * 86 * Unfortunately, there are a number of commands that do not follow the standard 87 * length encoding for their opcode range, primarily amongst the MI_* commands. 88 * To handle this, the parser provides a way to define explicit "skip" entries 89 * in the per-engine command tables. 90 * 91 * Other command table entries map fairly directly to high level categories 92 * mentioned above: rejected, register whitelist. The parser implements a number 93 * of checks, including the privileged memory checks, via a general bitmasking 94 * mechanism. 95 */ 96 97 /* 98 * A command that requires special handling by the command parser. 99 */ 100 struct drm_i915_cmd_descriptor { 101 /* 102 * Flags describing how the command parser processes the command. 103 * 104 * CMD_DESC_FIXED: The command has a fixed length if this is set, 105 * a length mask if not set 106 * CMD_DESC_SKIP: The command is allowed but does not follow the 107 * standard length encoding for the opcode range in 108 * which it falls 109 * CMD_DESC_REJECT: The command is never allowed 110 * CMD_DESC_REGISTER: The command should be checked against the 111 * register whitelist for the appropriate ring 112 */ 113 u32 flags; 114 #define CMD_DESC_FIXED (1<<0) 115 #define CMD_DESC_SKIP (1<<1) 116 #define CMD_DESC_REJECT (1<<2) 117 #define CMD_DESC_REGISTER (1<<3) 118 #define CMD_DESC_BITMASK (1<<4) 119 120 /* 121 * The command's unique identification bits and the bitmask to get them. 122 * This isn't strictly the opcode field as defined in the spec and may 123 * also include type, subtype, and/or subop fields. 124 */ 125 struct { 126 u32 value; 127 u32 mask; 128 } cmd; 129 130 /* 131 * The command's length. The command is either fixed length (i.e. does 132 * not include a length field) or has a length field mask. The flag 133 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 134 * a length mask. All command entries in a command table must include 135 * length information. 136 */ 137 union { 138 u32 fixed; 139 u32 mask; 140 } length; 141 142 /* 143 * Describes where to find a register address in the command to check 144 * against the ring's register whitelist. Only valid if flags has the 145 * CMD_DESC_REGISTER bit set. 146 * 147 * A non-zero step value implies that the command may access multiple 148 * registers in sequence (e.g. LRI), in that case step gives the 149 * distance in dwords between individual offset fields. 150 */ 151 struct { 152 u32 offset; 153 u32 mask; 154 u32 step; 155 } reg; 156 157 #define MAX_CMD_DESC_BITMASKS 3 158 /* 159 * Describes command checks where a particular dword is masked and 160 * compared against an expected value. If the command does not match 161 * the expected value, the parser rejects it. Only valid if flags has 162 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 163 * are valid. 164 * 165 * If the check specifies a non-zero condition_mask then the parser 166 * only performs the check when the bits specified by condition_mask 167 * are non-zero. 168 */ 169 struct { 170 u32 offset; 171 u32 mask; 172 u32 expected; 173 u32 condition_offset; 174 u32 condition_mask; 175 } bits[MAX_CMD_DESC_BITMASKS]; 176 }; 177 178 /* 179 * A table of commands requiring special handling by the command parser. 180 * 181 * Each engine has an array of tables. Each table consists of an array of 182 * command descriptors, which must be sorted with command opcodes in 183 * ascending order. 184 */ 185 struct drm_i915_cmd_table { 186 const struct drm_i915_cmd_descriptor *table; 187 int count; 188 }; 189 190 #define STD_MI_OPCODE_SHIFT (32 - 9) 191 #define STD_3D_OPCODE_SHIFT (32 - 16) 192 #define STD_2D_OPCODE_SHIFT (32 - 10) 193 #define STD_MFX_OPCODE_SHIFT (32 - 16) 194 #define MIN_OPCODE_SHIFT 16 195 196 #define CMD(op, opm, f, lm, fl, ...) \ 197 { \ 198 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 199 .cmd = { (op & ~0u << (opm)), ~0u << (opm) }, \ 200 .length = { (lm) }, \ 201 __VA_ARGS__ \ 202 } 203 204 /* Convenience macros to compress the tables */ 205 #define SMI STD_MI_OPCODE_SHIFT 206 #define S3D STD_3D_OPCODE_SHIFT 207 #define S2D STD_2D_OPCODE_SHIFT 208 #define SMFX STD_MFX_OPCODE_SHIFT 209 #define F true 210 #define S CMD_DESC_SKIP 211 #define R CMD_DESC_REJECT 212 #define W CMD_DESC_REGISTER 213 #define B CMD_DESC_BITMASK 214 215 /* Command Mask Fixed Len Action 216 ---------------------------------------------------------- */ 217 static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = { 218 CMD( MI_NOOP, SMI, F, 1, S ), 219 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 220 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ), 221 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 222 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 223 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 224 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 225 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 226 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 227 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 228 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 229 .reg = { .offset = 1, .mask = 0x007FFFFC }, 230 .bits = {{ 231 .offset = 0, 232 .mask = MI_GLOBAL_GTT, 233 .expected = 0, 234 }}, ), 235 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 236 .reg = { .offset = 1, .mask = 0x007FFFFC }, 237 .bits = {{ 238 .offset = 0, 239 .mask = MI_GLOBAL_GTT, 240 .expected = 0, 241 }}, ), 242 /* 243 * MI_BATCH_BUFFER_START requires some special handling. It's not 244 * really a 'skip' action but it doesn't seem like it's worth adding 245 * a new action. See intel_engine_cmd_parser(). 246 */ 247 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 248 }; 249 250 static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = { 251 CMD( MI_FLUSH, SMI, F, 1, S ), 252 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 253 CMD( MI_PREDICATE, SMI, F, 1, S ), 254 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 255 CMD( MI_SET_APPID, SMI, F, 1, S ), 256 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 257 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 258 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 259 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 260 .bits = {{ 261 .offset = 0, 262 .mask = MI_GLOBAL_GTT, 263 .expected = 0, 264 }}, ), 265 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 266 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 267 .bits = {{ 268 .offset = 0, 269 .mask = MI_GLOBAL_GTT, 270 .expected = 0, 271 }}, ), 272 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 273 .bits = {{ 274 .offset = 1, 275 .mask = MI_REPORT_PERF_COUNT_GGTT, 276 .expected = 0, 277 }}, ), 278 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 279 .bits = {{ 280 .offset = 0, 281 .mask = MI_GLOBAL_GTT, 282 .expected = 0, 283 }}, ), 284 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 285 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 286 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 287 .bits = {{ 288 .offset = 2, 289 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 290 .expected = 0, 291 }}, ), 292 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 293 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 294 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 295 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 296 .bits = {{ 297 .offset = 1, 298 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 299 .expected = 0, 300 }, 301 { 302 .offset = 1, 303 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 304 PIPE_CONTROL_STORE_DATA_INDEX), 305 .expected = 0, 306 .condition_offset = 1, 307 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 308 }}, ), 309 }; 310 311 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 312 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 313 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 314 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 315 CMD( MI_SET_APPID, SMI, F, 1, S ), 316 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 317 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 318 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 319 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 320 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 321 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 322 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 323 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 324 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 325 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 326 327 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 328 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 329 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 330 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 331 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 332 }; 333 334 static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = { 335 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 336 CMD( MI_SET_APPID, SMI, F, 1, S ), 337 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 338 .bits = {{ 339 .offset = 0, 340 .mask = MI_GLOBAL_GTT, 341 .expected = 0, 342 }}, ), 343 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 344 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 345 .bits = {{ 346 .offset = 0, 347 .mask = MI_FLUSH_DW_NOTIFY, 348 .expected = 0, 349 }, 350 { 351 .offset = 1, 352 .mask = MI_FLUSH_DW_USE_GTT, 353 .expected = 0, 354 .condition_offset = 0, 355 .condition_mask = MI_FLUSH_DW_OP_MASK, 356 }, 357 { 358 .offset = 0, 359 .mask = MI_FLUSH_DW_STORE_INDEX, 360 .expected = 0, 361 .condition_offset = 0, 362 .condition_mask = MI_FLUSH_DW_OP_MASK, 363 }}, ), 364 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 365 .bits = {{ 366 .offset = 0, 367 .mask = MI_GLOBAL_GTT, 368 .expected = 0, 369 }}, ), 370 /* 371 * MFX_WAIT doesn't fit the way we handle length for most commands. 372 * It has a length field but it uses a non-standard length bias. 373 * It is always 1 dword though, so just treat it as fixed length. 374 */ 375 CMD( MFX_WAIT, SMFX, F, 1, S ), 376 }; 377 378 static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = { 379 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 380 CMD( MI_SET_APPID, SMI, F, 1, S ), 381 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 382 .bits = {{ 383 .offset = 0, 384 .mask = MI_GLOBAL_GTT, 385 .expected = 0, 386 }}, ), 387 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 388 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 389 .bits = {{ 390 .offset = 0, 391 .mask = MI_FLUSH_DW_NOTIFY, 392 .expected = 0, 393 }, 394 { 395 .offset = 1, 396 .mask = MI_FLUSH_DW_USE_GTT, 397 .expected = 0, 398 .condition_offset = 0, 399 .condition_mask = MI_FLUSH_DW_OP_MASK, 400 }, 401 { 402 .offset = 0, 403 .mask = MI_FLUSH_DW_STORE_INDEX, 404 .expected = 0, 405 .condition_offset = 0, 406 .condition_mask = MI_FLUSH_DW_OP_MASK, 407 }}, ), 408 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 409 .bits = {{ 410 .offset = 0, 411 .mask = MI_GLOBAL_GTT, 412 .expected = 0, 413 }}, ), 414 }; 415 416 static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = { 417 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 418 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 419 .bits = {{ 420 .offset = 0, 421 .mask = MI_GLOBAL_GTT, 422 .expected = 0, 423 }}, ), 424 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 425 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 426 .bits = {{ 427 .offset = 0, 428 .mask = MI_FLUSH_DW_NOTIFY, 429 .expected = 0, 430 }, 431 { 432 .offset = 1, 433 .mask = MI_FLUSH_DW_USE_GTT, 434 .expected = 0, 435 .condition_offset = 0, 436 .condition_mask = MI_FLUSH_DW_OP_MASK, 437 }, 438 { 439 .offset = 0, 440 .mask = MI_FLUSH_DW_STORE_INDEX, 441 .expected = 0, 442 .condition_offset = 0, 443 .condition_mask = MI_FLUSH_DW_OP_MASK, 444 }}, ), 445 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 446 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 447 }; 448 449 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 450 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 451 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 452 }; 453 454 /* 455 * For Gen9 we can still rely on the h/w to enforce cmd security, and only 456 * need to re-enforce the register access checks. We therefore only need to 457 * teach the cmdparser how to find the end of each command, and identify 458 * register accesses. The table doesn't need to reject any commands, and so 459 * the only commands listed here are: 460 * 1) Those that touch registers 461 * 2) Those that do not have the default 8-bit length 462 * 463 * Note that the default MI length mask chosen for this table is 0xFF, not 464 * the 0x3F used on older devices. This is because the vast majority of MI 465 * cmds on Gen9 use a standard 8-bit Length field. 466 * All the Gen9 blitter instructions are standard 0xFF length mask, and 467 * none allow access to non-general registers, so in fact no BLT cmds are 468 * included in the table at all. 469 * 470 */ 471 static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = { 472 CMD( MI_NOOP, SMI, F, 1, S ), 473 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ), 474 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ), 475 CMD( MI_FLUSH, SMI, F, 1, S ), 476 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 477 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 478 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), 479 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 480 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ), 481 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ), 482 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ), 483 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 484 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 485 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ), 486 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W, 487 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 488 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ), 489 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W, 490 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 491 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 492 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 493 494 /* 495 * We allow BB_START but apply further checks. We just sanitize the 496 * basic fields here. 497 */ 498 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0) 499 #define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1) 500 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B, 501 .bits = {{ 502 .offset = 0, 503 .mask = MI_BB_START_OPERAND_MASK, 504 .expected = MI_BB_START_OPERAND_EXPECT, 505 }}, ), 506 }; 507 508 static const struct drm_i915_cmd_descriptor noop_desc = 509 CMD(MI_NOOP, SMI, F, 1, S); 510 511 #undef CMD 512 #undef SMI 513 #undef S3D 514 #undef S2D 515 #undef SMFX 516 #undef F 517 #undef S 518 #undef R 519 #undef W 520 #undef B 521 522 static const struct drm_i915_cmd_table gen7_render_cmd_table[] = { 523 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 524 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 525 }; 526 527 static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = { 528 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 529 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 530 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 531 }; 532 533 static const struct drm_i915_cmd_table gen7_video_cmd_table[] = { 534 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 535 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) }, 536 }; 537 538 static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = { 539 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 540 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) }, 541 }; 542 543 static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = { 544 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 545 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 546 }; 547 548 static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = { 549 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 550 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 551 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 552 }; 553 554 static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = { 555 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) }, 556 }; 557 558 559 /* 560 * Register whitelists, sorted by increasing register offset. 561 */ 562 563 /* 564 * An individual whitelist entry granting access to register addr. If 565 * mask is non-zero the argument of immediate register writes will be 566 * AND-ed with mask, and the command will be rejected if the result 567 * doesn't match value. 568 * 569 * Registers with non-zero mask are only allowed to be written using 570 * LRI. 571 */ 572 struct drm_i915_reg_descriptor { 573 i915_reg_t addr; 574 u32 mask; 575 u32 value; 576 }; 577 578 /* Convenience macro for adding 32-bit registers. */ 579 #define REG32(_reg, ...) \ 580 { .addr = (_reg), __VA_ARGS__ } 581 582 /* 583 * Convenience macro for adding 64-bit registers. 584 * 585 * Some registers that userspace accesses are 64 bits. The register 586 * access commands only allow 32-bit accesses. Hence, we have to include 587 * entries for both halves of the 64-bit registers. 588 */ 589 #define REG64(_reg) \ 590 { .addr = _reg }, \ 591 { .addr = _reg ## _UDW } 592 593 #define REG64_IDX(_reg, idx) \ 594 { .addr = _reg(idx) }, \ 595 { .addr = _reg ## _UDW(idx) } 596 597 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 598 REG64(GPGPU_THREADS_DISPATCHED), 599 REG64(HS_INVOCATION_COUNT), 600 REG64(DS_INVOCATION_COUNT), 601 REG64(IA_VERTICES_COUNT), 602 REG64(IA_PRIMITIVES_COUNT), 603 REG64(VS_INVOCATION_COUNT), 604 REG64(GS_INVOCATION_COUNT), 605 REG64(GS_PRIMITIVES_COUNT), 606 REG64(CL_INVOCATION_COUNT), 607 REG64(CL_PRIMITIVES_COUNT), 608 REG64(PS_INVOCATION_COUNT), 609 REG64(PS_DEPTH_COUNT), 610 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 611 REG64(MI_PREDICATE_SRC0), 612 REG64(MI_PREDICATE_SRC1), 613 REG32(GEN7_3DPRIM_END_OFFSET), 614 REG32(GEN7_3DPRIM_START_VERTEX), 615 REG32(GEN7_3DPRIM_VERTEX_COUNT), 616 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 617 REG32(GEN7_3DPRIM_START_INSTANCE), 618 REG32(GEN7_3DPRIM_BASE_VERTEX), 619 REG32(GEN7_GPGPU_DISPATCHDIMX), 620 REG32(GEN7_GPGPU_DISPATCHDIMY), 621 REG32(GEN7_GPGPU_DISPATCHDIMZ), 622 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 623 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), 624 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), 625 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), 626 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), 627 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), 628 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), 629 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), 630 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), 631 REG32(GEN7_SO_WRITE_OFFSET(0)), 632 REG32(GEN7_SO_WRITE_OFFSET(1)), 633 REG32(GEN7_SO_WRITE_OFFSET(2)), 634 REG32(GEN7_SO_WRITE_OFFSET(3)), 635 REG32(GEN7_L3SQCREG1), 636 REG32(GEN7_L3CNTLREG2), 637 REG32(GEN7_L3CNTLREG3), 638 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 639 }; 640 641 static const struct drm_i915_reg_descriptor hsw_render_regs[] = { 642 REG64_IDX(HSW_CS_GPR, 0), 643 REG64_IDX(HSW_CS_GPR, 1), 644 REG64_IDX(HSW_CS_GPR, 2), 645 REG64_IDX(HSW_CS_GPR, 3), 646 REG64_IDX(HSW_CS_GPR, 4), 647 REG64_IDX(HSW_CS_GPR, 5), 648 REG64_IDX(HSW_CS_GPR, 6), 649 REG64_IDX(HSW_CS_GPR, 7), 650 REG64_IDX(HSW_CS_GPR, 8), 651 REG64_IDX(HSW_CS_GPR, 9), 652 REG64_IDX(HSW_CS_GPR, 10), 653 REG64_IDX(HSW_CS_GPR, 11), 654 REG64_IDX(HSW_CS_GPR, 12), 655 REG64_IDX(HSW_CS_GPR, 13), 656 REG64_IDX(HSW_CS_GPR, 14), 657 REG64_IDX(HSW_CS_GPR, 15), 658 REG32(HSW_SCRATCH1, 659 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 660 .value = 0), 661 REG32(HSW_ROW_CHICKEN3, 662 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 663 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 664 .value = 0), 665 }; 666 667 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 668 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 669 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 670 REG32(BCS_SWCTRL), 671 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 672 }; 673 674 static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { 675 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 676 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 677 REG32(BCS_SWCTRL), 678 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 679 REG64_IDX(BCS_GPR, 0), 680 REG64_IDX(BCS_GPR, 1), 681 REG64_IDX(BCS_GPR, 2), 682 REG64_IDX(BCS_GPR, 3), 683 REG64_IDX(BCS_GPR, 4), 684 REG64_IDX(BCS_GPR, 5), 685 REG64_IDX(BCS_GPR, 6), 686 REG64_IDX(BCS_GPR, 7), 687 REG64_IDX(BCS_GPR, 8), 688 REG64_IDX(BCS_GPR, 9), 689 REG64_IDX(BCS_GPR, 10), 690 REG64_IDX(BCS_GPR, 11), 691 REG64_IDX(BCS_GPR, 12), 692 REG64_IDX(BCS_GPR, 13), 693 REG64_IDX(BCS_GPR, 14), 694 REG64_IDX(BCS_GPR, 15), 695 }; 696 697 #undef REG64 698 #undef REG32 699 700 struct drm_i915_reg_table { 701 const struct drm_i915_reg_descriptor *regs; 702 int num_regs; 703 }; 704 705 static const struct drm_i915_reg_table ivb_render_reg_tables[] = { 706 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) }, 707 }; 708 709 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { 710 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) }, 711 }; 712 713 static const struct drm_i915_reg_table hsw_render_reg_tables[] = { 714 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) }, 715 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) }, 716 }; 717 718 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = { 719 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) }, 720 }; 721 722 static const struct drm_i915_reg_table gen9_blt_reg_tables[] = { 723 { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) }, 724 }; 725 726 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 727 { 728 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 729 u32 subclient = 730 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 731 732 if (client == INSTR_MI_CLIENT) 733 return 0x3F; 734 else if (client == INSTR_RC_CLIENT) { 735 if (subclient == INSTR_MEDIA_SUBCLIENT) 736 return 0xFFFF; 737 else 738 return 0xFF; 739 } 740 741 DRM_DEBUG("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 742 return 0; 743 } 744 745 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 746 { 747 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 748 u32 subclient = 749 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 750 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 751 752 if (client == INSTR_MI_CLIENT) 753 return 0x3F; 754 else if (client == INSTR_RC_CLIENT) { 755 if (subclient == INSTR_MEDIA_SUBCLIENT) { 756 if (op == 6) 757 return 0xFFFF; 758 else 759 return 0xFFF; 760 } else 761 return 0xFF; 762 } 763 764 DRM_DEBUG("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 765 return 0; 766 } 767 768 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 769 { 770 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 771 772 if (client == INSTR_MI_CLIENT) 773 return 0x3F; 774 else if (client == INSTR_BC_CLIENT) 775 return 0xFF; 776 777 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 778 return 0; 779 } 780 781 static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header) 782 { 783 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 784 785 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT) 786 return 0xFF; 787 788 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 789 return 0; 790 } 791 792 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, 793 const struct drm_i915_cmd_table *cmd_tables, 794 int cmd_table_count) 795 { 796 int i; 797 bool ret = true; 798 799 if (!cmd_tables || cmd_table_count == 0) 800 return true; 801 802 for (i = 0; i < cmd_table_count; i++) { 803 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 804 u32 previous = 0; 805 int j; 806 807 for (j = 0; j < table->count; j++) { 808 const struct drm_i915_cmd_descriptor *desc = 809 &table->table[j]; 810 u32 curr = desc->cmd.value & desc->cmd.mask; 811 812 if (curr < previous) { 813 DRM_ERROR("CMD: %s [%d] command table not sorted: " 814 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 815 engine->name, engine->id, 816 i, j, curr, previous); 817 ret = false; 818 } 819 820 previous = curr; 821 } 822 } 823 824 return ret; 825 } 826 827 static bool check_sorted(const struct intel_engine_cs *engine, 828 const struct drm_i915_reg_descriptor *reg_table, 829 int reg_count) 830 { 831 int i; 832 u32 previous = 0; 833 bool ret = true; 834 835 for (i = 0; i < reg_count; i++) { 836 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); 837 838 if (curr < previous) { 839 DRM_ERROR("CMD: %s [%d] register table not sorted: " 840 "entry=%d reg=0x%08X prev=0x%08X\n", 841 engine->name, engine->id, 842 i, curr, previous); 843 ret = false; 844 } 845 846 previous = curr; 847 } 848 849 return ret; 850 } 851 852 static bool validate_regs_sorted(struct intel_engine_cs *engine) 853 { 854 int i; 855 const struct drm_i915_reg_table *table; 856 857 for (i = 0; i < engine->reg_table_count; i++) { 858 table = &engine->reg_tables[i]; 859 if (!check_sorted(engine, table->regs, table->num_regs)) 860 return false; 861 } 862 863 return true; 864 } 865 866 struct cmd_node { 867 const struct drm_i915_cmd_descriptor *desc; 868 struct hlist_node node; 869 }; 870 871 /* 872 * Different command ranges have different numbers of bits for the opcode. For 873 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 874 * problem is that, for example, MI commands use bits 22:16 for other fields 875 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 876 * we mask a command from a batch it could hash to the wrong bucket due to 877 * non-opcode bits being set. But if we don't include those bits, some 3D 878 * commands may hash to the same bucket due to not including opcode bits that 879 * make the command unique. For now, we will risk hashing to the same bucket. 880 */ 881 static inline u32 cmd_header_key(u32 x) 882 { 883 switch (x >> INSTR_CLIENT_SHIFT) { 884 default: 885 case INSTR_MI_CLIENT: 886 return x >> STD_MI_OPCODE_SHIFT; 887 case INSTR_RC_CLIENT: 888 return x >> STD_3D_OPCODE_SHIFT; 889 case INSTR_BC_CLIENT: 890 return x >> STD_2D_OPCODE_SHIFT; 891 } 892 } 893 894 static int init_hash_table(struct intel_engine_cs *engine, 895 const struct drm_i915_cmd_table *cmd_tables, 896 int cmd_table_count) 897 { 898 int i, j; 899 900 hash_init(engine->cmd_hash); 901 902 for (i = 0; i < cmd_table_count; i++) { 903 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 904 905 for (j = 0; j < table->count; j++) { 906 const struct drm_i915_cmd_descriptor *desc = 907 &table->table[j]; 908 struct cmd_node *desc_node = 909 kmalloc(sizeof(*desc_node), GFP_KERNEL); 910 911 if (!desc_node) 912 return -ENOMEM; 913 914 desc_node->desc = desc; 915 hash_add(engine->cmd_hash, &desc_node->node, 916 cmd_header_key(desc->cmd.value)); 917 } 918 } 919 920 return 0; 921 } 922 923 static void fini_hash_table(struct intel_engine_cs *engine) 924 { 925 struct hlist_node *tmp; 926 struct cmd_node *desc_node; 927 int i; 928 929 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { 930 hash_del(&desc_node->node); 931 kfree(desc_node); 932 } 933 } 934 935 /** 936 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine 937 * @engine: the engine to initialize 938 * 939 * Optionally initializes fields related to batch buffer command parsing in the 940 * struct intel_engine_cs based on whether the platform requires software 941 * command parsing. 942 */ 943 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 944 { 945 const struct drm_i915_cmd_table *cmd_tables; 946 int cmd_table_count; 947 int ret; 948 949 if (!IS_GEN(engine->i915, 7) && !(IS_GEN(engine->i915, 9) && 950 engine->class == COPY_ENGINE_CLASS)) 951 return; 952 953 switch (engine->class) { 954 case RENDER_CLASS: 955 if (IS_HASWELL(engine->i915)) { 956 cmd_tables = hsw_render_ring_cmd_table; 957 cmd_table_count = 958 ARRAY_SIZE(hsw_render_ring_cmd_table); 959 } else { 960 cmd_tables = gen7_render_cmd_table; 961 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table); 962 } 963 964 if (IS_HASWELL(engine->i915)) { 965 engine->reg_tables = hsw_render_reg_tables; 966 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); 967 } else { 968 engine->reg_tables = ivb_render_reg_tables; 969 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); 970 } 971 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 972 break; 973 case VIDEO_DECODE_CLASS: 974 cmd_tables = gen7_video_cmd_table; 975 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table); 976 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 977 break; 978 case COPY_ENGINE_CLASS: 979 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 980 if (IS_GEN(engine->i915, 9)) { 981 cmd_tables = gen9_blt_cmd_table; 982 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table); 983 engine->get_cmd_length_mask = 984 gen9_blt_get_cmd_length_mask; 985 986 /* BCS Engine unsafe without parser */ 987 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER; 988 } else if (IS_HASWELL(engine->i915)) { 989 cmd_tables = hsw_blt_ring_cmd_table; 990 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table); 991 } else { 992 cmd_tables = gen7_blt_cmd_table; 993 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table); 994 } 995 996 if (IS_GEN(engine->i915, 9)) { 997 engine->reg_tables = gen9_blt_reg_tables; 998 engine->reg_table_count = 999 ARRAY_SIZE(gen9_blt_reg_tables); 1000 } else if (IS_HASWELL(engine->i915)) { 1001 engine->reg_tables = hsw_blt_reg_tables; 1002 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); 1003 } else { 1004 engine->reg_tables = ivb_blt_reg_tables; 1005 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); 1006 } 1007 break; 1008 case VIDEO_ENHANCEMENT_CLASS: 1009 cmd_tables = hsw_vebox_cmd_table; 1010 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table); 1011 /* VECS can use the same length_mask function as VCS */ 1012 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 1013 break; 1014 default: 1015 MISSING_CASE(engine->class); 1016 return; 1017 } 1018 1019 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) { 1020 DRM_ERROR("%s: command descriptions are not sorted\n", 1021 engine->name); 1022 return; 1023 } 1024 if (!validate_regs_sorted(engine)) { 1025 DRM_ERROR("%s: registers are not sorted\n", engine->name); 1026 return; 1027 } 1028 1029 ret = init_hash_table(engine, cmd_tables, cmd_table_count); 1030 if (ret) { 1031 DRM_ERROR("%s: initialised failed!\n", engine->name); 1032 fini_hash_table(engine); 1033 return; 1034 } 1035 1036 engine->flags |= I915_ENGINE_USING_CMD_PARSER; 1037 } 1038 1039 /** 1040 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields 1041 * @engine: the engine to clean up 1042 * 1043 * Releases any resources related to command parsing that may have been 1044 * initialized for the specified engine. 1045 */ 1046 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine) 1047 { 1048 if (!intel_engine_using_cmd_parser(engine)) 1049 return; 1050 1051 fini_hash_table(engine); 1052 } 1053 1054 static const struct drm_i915_cmd_descriptor* 1055 find_cmd_in_table(struct intel_engine_cs *engine, 1056 u32 cmd_header) 1057 { 1058 struct cmd_node *desc_node; 1059 1060 hash_for_each_possible(engine->cmd_hash, desc_node, node, 1061 cmd_header_key(cmd_header)) { 1062 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 1063 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 1064 return desc; 1065 } 1066 1067 return NULL; 1068 } 1069 1070 /* 1071 * Returns a pointer to a descriptor for the command specified by cmd_header. 1072 * 1073 * The caller must supply space for a default descriptor via the default_desc 1074 * parameter. If no descriptor for the specified command exists in the engine's 1075 * command parser tables, this function fills in default_desc based on the 1076 * engine's default length encoding and returns default_desc. 1077 */ 1078 static const struct drm_i915_cmd_descriptor* 1079 find_cmd(struct intel_engine_cs *engine, 1080 u32 cmd_header, 1081 const struct drm_i915_cmd_descriptor *desc, 1082 struct drm_i915_cmd_descriptor *default_desc) 1083 { 1084 u32 mask; 1085 1086 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 1087 return desc; 1088 1089 desc = find_cmd_in_table(engine, cmd_header); 1090 if (desc) 1091 return desc; 1092 1093 mask = engine->get_cmd_length_mask(cmd_header); 1094 if (!mask) 1095 return NULL; 1096 1097 default_desc->cmd.value = cmd_header; 1098 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; 1099 default_desc->length.mask = mask; 1100 default_desc->flags = CMD_DESC_SKIP; 1101 return default_desc; 1102 } 1103 1104 static const struct drm_i915_reg_descriptor * 1105 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr) 1106 { 1107 int start = 0, end = count; 1108 while (start < end) { 1109 int mid = start + (end - start) / 2; 1110 int ret = addr - i915_mmio_reg_offset(table[mid].addr); 1111 if (ret < 0) 1112 end = mid; 1113 else if (ret > 0) 1114 start = mid + 1; 1115 else 1116 return &table[mid]; 1117 } 1118 return NULL; 1119 } 1120 1121 static const struct drm_i915_reg_descriptor * 1122 find_reg(const struct intel_engine_cs *engine, u32 addr) 1123 { 1124 const struct drm_i915_reg_table *table = engine->reg_tables; 1125 const struct drm_i915_reg_descriptor *reg = NULL; 1126 int count = engine->reg_table_count; 1127 1128 for (; !reg && (count > 0); ++table, --count) 1129 reg = __find_reg(table->regs, table->num_regs, addr); 1130 1131 return reg; 1132 } 1133 1134 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */ 1135 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 1136 struct drm_i915_gem_object *src_obj, 1137 u32 offset, u32 length) 1138 { 1139 bool needs_clflush; 1140 void *dst, *src; 1141 int ret; 1142 1143 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB); 1144 if (IS_ERR(dst)) 1145 return dst; 1146 1147 ret = i915_gem_object_pin_pages(src_obj); 1148 if (ret) { 1149 i915_gem_object_unpin_map(dst_obj); 1150 return ERR_PTR(ret); 1151 } 1152 1153 needs_clflush = 1154 !(src_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ); 1155 1156 src = ERR_PTR(-ENODEV); 1157 if (needs_clflush && i915_has_memcpy_from_wc()) { 1158 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC); 1159 if (!IS_ERR(src)) { 1160 i915_unaligned_memcpy_from_wc(dst, 1161 src + offset, 1162 length); 1163 i915_gem_object_unpin_map(src_obj); 1164 } 1165 } 1166 if (IS_ERR(src)) { 1167 void *ptr; 1168 int x, n; 1169 1170 /* 1171 * We can avoid clflushing partial cachelines before the write 1172 * if we only every write full cache-lines. Since we know that 1173 * both the source and destination are in multiples of 1174 * PAGE_SIZE, we can simply round up to the next cacheline. 1175 * We don't care about copying too much here as we only 1176 * validate up to the end of the batch. 1177 */ 1178 if (!(dst_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) { 1179 #ifdef __NetBSD__ 1180 length = round_up(length, 1181 cpu_info_primary.ci_cflush_lsize); 1182 #else 1183 length = round_up(length, 1184 boot_cpu_data.x86_clflush_size); 1185 #endif 1186 } 1187 1188 ptr = dst; 1189 x = offset_in_page(offset); 1190 for (n = offset >> PAGE_SHIFT; length; n++) { 1191 int len = min_t(int, length, PAGE_SIZE - x); 1192 1193 src = kmap_atomic(i915_gem_object_get_page(src_obj, n)); 1194 if (needs_clflush) 1195 drm_clflush_virt_range(src + x, len); 1196 memcpy(ptr, src + x, len); 1197 kunmap_atomic(src); 1198 1199 ptr += len; 1200 length -= len; 1201 x = 0; 1202 } 1203 } 1204 1205 i915_gem_object_unpin_pages(src_obj); 1206 1207 /* dst_obj is returned with vmap pinned */ 1208 return dst; 1209 } 1210 1211 static bool check_cmd(const struct intel_engine_cs *engine, 1212 const struct drm_i915_cmd_descriptor *desc, 1213 const u32 *cmd, u32 length) 1214 { 1215 if (desc->flags & CMD_DESC_SKIP) 1216 return true; 1217 1218 if (desc->flags & CMD_DESC_REJECT) { 1219 DRM_DEBUG("CMD: Rejected command: 0x%08X\n", *cmd); 1220 return false; 1221 } 1222 1223 if (desc->flags & CMD_DESC_REGISTER) { 1224 /* 1225 * Get the distance between individual register offset 1226 * fields if the command can perform more than one 1227 * access at a time. 1228 */ 1229 const u32 step = desc->reg.step ? desc->reg.step : length; 1230 u32 offset; 1231 1232 for (offset = desc->reg.offset; offset < length; 1233 offset += step) { 1234 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1235 const struct drm_i915_reg_descriptor *reg = 1236 find_reg(engine, reg_addr); 1237 1238 if (!reg) { 1239 DRM_DEBUG("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n", 1240 reg_addr, *cmd, engine->name); 1241 return false; 1242 } 1243 1244 /* 1245 * Check the value written to the register against the 1246 * allowed mask/value pair given in the whitelist entry. 1247 */ 1248 if (reg->mask) { 1249 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1250 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n", 1251 reg_addr); 1252 return false; 1253 } 1254 1255 if (desc->cmd.value == MI_LOAD_REGISTER_REG) { 1256 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n", 1257 reg_addr); 1258 return false; 1259 } 1260 1261 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && 1262 (offset + 2 > length || 1263 (cmd[offset + 1] & reg->mask) != reg->value)) { 1264 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n", 1265 reg_addr); 1266 return false; 1267 } 1268 } 1269 } 1270 } 1271 1272 if (desc->flags & CMD_DESC_BITMASK) { 1273 int i; 1274 1275 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1276 u32 dword; 1277 1278 if (desc->bits[i].mask == 0) 1279 break; 1280 1281 if (desc->bits[i].condition_mask != 0) { 1282 u32 offset = 1283 desc->bits[i].condition_offset; 1284 u32 condition = cmd[offset] & 1285 desc->bits[i].condition_mask; 1286 1287 if (condition == 0) 1288 continue; 1289 } 1290 1291 if (desc->bits[i].offset >= length) { 1292 DRM_DEBUG("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n", 1293 *cmd, engine->name); 1294 return false; 1295 } 1296 1297 dword = cmd[desc->bits[i].offset] & 1298 desc->bits[i].mask; 1299 1300 if (dword != desc->bits[i].expected) { 1301 DRM_DEBUG("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n", 1302 *cmd, 1303 desc->bits[i].mask, 1304 desc->bits[i].expected, 1305 dword, engine->name); 1306 return false; 1307 } 1308 } 1309 } 1310 1311 return true; 1312 } 1313 1314 static int check_bbstart(u32 *cmd, u32 offset, u32 length, 1315 u32 batch_length, 1316 u64 batch_addr, 1317 u64 shadow_addr, 1318 const unsigned long *jump_whitelist) 1319 { 1320 u64 jump_offset, jump_target; 1321 u32 target_cmd_offset, target_cmd_index; 1322 1323 /* For igt compatibility on older platforms */ 1324 if (!jump_whitelist) { 1325 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n"); 1326 return -EACCES; 1327 } 1328 1329 if (length != 3) { 1330 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n", 1331 length); 1332 return -EINVAL; 1333 } 1334 1335 jump_target = *(u64 *)(cmd + 1); 1336 jump_offset = jump_target - batch_addr; 1337 1338 /* 1339 * Any underflow of jump_target is guaranteed to be outside the range 1340 * of a u32, so >= test catches both too large and too small 1341 */ 1342 if (jump_offset >= batch_length) { 1343 DRM_DEBUG("CMD: BB_START to 0x%"PRIx64" jumps out of BB\n", 1344 jump_target); 1345 return -EINVAL; 1346 } 1347 1348 /* 1349 * This cannot overflow a u32 because we already checked jump_offset 1350 * is within the BB, and the batch_length is a u32 1351 */ 1352 target_cmd_offset = lower_32_bits(jump_offset); 1353 target_cmd_index = target_cmd_offset / sizeof(u32); 1354 1355 *(u64 *)(cmd + 1) = shadow_addr + target_cmd_offset; 1356 1357 if (target_cmd_index == offset) 1358 return 0; 1359 1360 if (IS_ERR(jump_whitelist)) 1361 return PTR_ERR(jump_whitelist); 1362 1363 if (!test_bit(target_cmd_index, jump_whitelist)) { 1364 DRM_DEBUG("CMD: BB_START to 0x%"PRIx64" not a previously executed cmd\n", 1365 jump_target); 1366 return -EINVAL; 1367 } 1368 1369 return 0; 1370 } 1371 1372 static unsigned long *alloc_whitelist(u32 batch_length) 1373 { 1374 unsigned long *jmp; 1375 1376 /* 1377 * We expect batch_length to be less than 256KiB for known users, 1378 * i.e. we need at most an 8KiB bitmap allocation which should be 1379 * reasonably cheap due to kmalloc caches. 1380 */ 1381 1382 /* Prefer to report transient allocation failure rather than hit oom */ 1383 jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)), 1384 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); 1385 if (!jmp) 1386 return ERR_PTR(-ENOMEM); 1387 1388 return jmp; 1389 } 1390 1391 #define LENGTH_BIAS 2 1392 1393 static bool shadow_needs_clflush(struct drm_i915_gem_object *obj) 1394 { 1395 return !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE); 1396 } 1397 1398 /** 1399 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations 1400 * @engine: the engine on which the batch is to execute 1401 * @batch: the batch buffer in question 1402 * @batch_offset: byte offset in the batch at which execution starts 1403 * @batch_length: length of the commands in batch_obj 1404 * @shadow: validated copy of the batch buffer in question 1405 * @trampoline: whether to emit a conditional trampoline at the end of the batch 1406 * 1407 * Parses the specified batch buffer looking for privilege violations as 1408 * described in the overview. 1409 * 1410 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1411 * if the batch appears legal but should use hardware parsing 1412 */ 1413 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1414 struct i915_vma *batch, 1415 u32 batch_offset, 1416 u32 batch_length, 1417 struct i915_vma *shadow, 1418 bool trampoline) 1419 { 1420 u32 *cmd, *batch_end, offset = 0; 1421 struct drm_i915_cmd_descriptor default_desc = noop_desc; 1422 const struct drm_i915_cmd_descriptor *desc = &default_desc; 1423 unsigned long *jump_whitelist; 1424 u64 batch_addr, shadow_addr; 1425 int ret = 0; 1426 1427 GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd))); 1428 GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd))); 1429 GEM_BUG_ON(range_overflows_t(u64, batch_offset, batch_length, 1430 batch->size)); 1431 GEM_BUG_ON(!batch_length); 1432 1433 cmd = copy_batch(shadow->obj, batch->obj, batch_offset, batch_length); 1434 if (IS_ERR(cmd)) { 1435 DRM_DEBUG("CMD: Failed to copy batch\n"); 1436 return PTR_ERR(cmd); 1437 } 1438 1439 jump_whitelist = NULL; 1440 if (!trampoline) 1441 /* Defer failure until attempted use */ 1442 jump_whitelist = alloc_whitelist(batch_length); 1443 1444 shadow_addr = gen8_canonical_addr(shadow->node.start); 1445 batch_addr = gen8_canonical_addr(batch->node.start + batch_offset); 1446 1447 /* 1448 * We use the batch length as size because the shadow object is as 1449 * large or larger and copy_batch() will write MI_NOPs to the extra 1450 * space. Parsing should be faster in some cases this way. 1451 */ 1452 batch_end = cmd + batch_length / sizeof(*batch_end); 1453 do { 1454 u32 length; 1455 1456 if (*cmd == MI_BATCH_BUFFER_END) 1457 break; 1458 1459 desc = find_cmd(engine, *cmd, desc, &default_desc); 1460 if (!desc) { 1461 DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd); 1462 ret = -EINVAL; 1463 break; 1464 } 1465 1466 if (desc->flags & CMD_DESC_FIXED) 1467 length = desc->length.fixed; 1468 else 1469 length = (*cmd & desc->length.mask) + LENGTH_BIAS; 1470 1471 if ((batch_end - cmd) < length) { 1472 DRM_DEBUG("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1473 *cmd, 1474 length, 1475 batch_end - cmd); 1476 ret = -EINVAL; 1477 break; 1478 } 1479 1480 if (!check_cmd(engine, desc, cmd, length)) { 1481 ret = -EACCES; 1482 break; 1483 } 1484 1485 if (desc->cmd.value == MI_BATCH_BUFFER_START) { 1486 ret = check_bbstart(cmd, offset, length, batch_length, 1487 batch_addr, shadow_addr, 1488 jump_whitelist); 1489 break; 1490 } 1491 1492 if (!IS_ERR_OR_NULL(jump_whitelist)) 1493 __set_bit(offset, jump_whitelist); 1494 1495 cmd += length; 1496 offset += length; 1497 if (cmd >= batch_end) { 1498 DRM_DEBUG("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1499 ret = -EINVAL; 1500 break; 1501 } 1502 } while (1); 1503 1504 if (trampoline) { 1505 /* 1506 * With the trampoline, the shadow is executed twice. 1507 * 1508 * 1 - starting at offset 0, in privileged mode 1509 * 2 - starting at offset batch_len, as non-privileged 1510 * 1511 * Only if the batch is valid and safe to execute, do we 1512 * allow the first privileged execution to proceed. If not, 1513 * we terminate the first batch and use the second batchbuffer 1514 * entry to chain to the original unsafe non-privileged batch, 1515 * leaving it to the HW to validate. 1516 */ 1517 *batch_end = MI_BATCH_BUFFER_END; 1518 1519 if (ret) { 1520 /* Batch unsafe to execute with privileges, cancel! */ 1521 cmd = page_mask_bits(shadow->obj->mm.mapping); 1522 *cmd = MI_BATCH_BUFFER_END; 1523 1524 /* If batch is unsafe but valid, jump to the original */ 1525 if (ret == -EACCES) { 1526 unsigned int flags; 1527 1528 flags = MI_BATCH_NON_SECURE_I965; 1529 if (IS_HASWELL(engine->i915)) 1530 flags = MI_BATCH_NON_SECURE_HSW; 1531 1532 GEM_BUG_ON(!IS_GEN_RANGE(engine->i915, 6, 7)); 1533 __gen6_emit_bb_start(batch_end, 1534 batch_addr, 1535 flags); 1536 1537 ret = 0; /* allow execution */ 1538 } 1539 } 1540 1541 if (shadow_needs_clflush(shadow->obj)) 1542 drm_clflush_virt_range(batch_end, 8); 1543 } 1544 1545 if (shadow_needs_clflush(shadow->obj)) { 1546 void *ptr = page_mask_bits(shadow->obj->mm.mapping); 1547 1548 drm_clflush_virt_range(ptr, (void *)(cmd + 1) - ptr); 1549 } 1550 1551 if (!IS_ERR_OR_NULL(jump_whitelist)) 1552 kfree(jump_whitelist); 1553 i915_gem_object_unpin_map(shadow->obj); 1554 return ret; 1555 } 1556 1557 /** 1558 * i915_cmd_parser_get_version() - get the cmd parser version number 1559 * @dev_priv: i915 device private 1560 * 1561 * The cmd parser maintains a simple increasing integer version number suitable 1562 * for passing to userspace clients to determine what operations are permitted. 1563 * 1564 * Return: the current version number of the cmd parser 1565 */ 1566 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 1567 { 1568 struct intel_engine_cs *engine; 1569 bool active = false; 1570 1571 /* If the command parser is not enabled, report 0 - unsupported */ 1572 for_each_uabi_engine(engine, dev_priv) { 1573 if (intel_engine_using_cmd_parser(engine)) { 1574 active = true; 1575 break; 1576 } 1577 } 1578 if (!active) 1579 return 0; 1580 1581 /* 1582 * Command parser version history 1583 * 1584 * 1. Initial version. Checks batches and reports violations, but leaves 1585 * hardware parsing enabled (so does not allow new use cases). 1586 * 2. Allow access to the MI_PREDICATE_SRC0 and 1587 * MI_PREDICATE_SRC1 registers. 1588 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1589 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1590 * 5. GPGPU dispatch compute indirect registers. 1591 * 6. TIMESTAMP register and Haswell CS GPR registers 1592 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers. 1593 * 8. Don't report cmd_check() failures as EINVAL errors to userspace; 1594 * rely on the HW to NOOP disallowed commands as it would without 1595 * the parser enabled. 1596 * 9. Don't whitelist or handle oacontrol specially, as ownership 1597 * for oacontrol state is moving to i915-perf. 1598 * 10. Support for Gen9 BCS Parsing 1599 */ 1600 return 10; 1601 } 1602
Indexes created Sat Sep 20 22:09:52 GMT 2025