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      1 /*	$NetBSD: intel_guc_fw.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $	*/
      2 
      3 // SPDX-License-Identifier: MIT
      4 /*
      5  * Copyright  2014-2019 Intel Corporation
      6  *
      7  * Authors:
      8  *    Vinit Azad <vinit.azad (at) intel.com>
      9  *    Ben Widawsky <ben (at) bwidawsk.net>
     10  *    Dave Gordon <david.s.gordon (at) intel.com>
     11  *    Alex Dai <yu.dai (at) intel.com>
     12  */
     13 
     14 #include <sys/cdefs.h>
     15 __KERNEL_RCSID(0, "$NetBSD: intel_guc_fw.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $");
     16 
     17 #include "gt/intel_gt.h"
     18 #include "intel_guc_fw.h"
     19 #include "i915_drv.h"
     20 
     21 /**
     22  * intel_guc_fw_init_early() - initializes GuC firmware struct
     23  * @guc: intel_guc struct
     24  *
     25  * On platforms with GuC selects firmware for uploading
     26  */
     27 void intel_guc_fw_init_early(struct intel_guc *guc)
     28 {
     29 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
     30 
     31 	intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, HAS_GT_UC(i915),
     32 			       INTEL_INFO(i915)->platform, INTEL_REVID(i915));
     33 }
     34 
     35 static void guc_prepare_xfer(struct intel_uncore *uncore)
     36 {
     37 	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
     38 			 GUC_ENABLE_READ_CACHE_LOGIC |
     39 			 GUC_ENABLE_MIA_CACHING |
     40 			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
     41 			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
     42 			 GUC_ENABLE_MIA_CLOCK_GATING;
     43 
     44 	/* Must program this register before loading the ucode with DMA */
     45 	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
     46 
     47 	if (IS_GEN9_LP(uncore->i915))
     48 		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
     49 	else
     50 		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
     51 
     52 	if (IS_GEN(uncore->i915, 9)) {
     53 		/* DOP Clock Gating Enable for GuC clocks */
     54 		intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
     55 				 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
     56 
     57 		/* allows for 5us (in 10ns units) before GT can go to RC6 */
     58 		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
     59 	}
     60 }
     61 
     62 /* Copy RSA signature from the fw image to HW for verification */
     63 static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
     64 			 struct intel_uncore *uncore)
     65 {
     66 	u32 rsa[UOS_RSA_SCRATCH_COUNT];
     67 	size_t copied;
     68 	int i;
     69 
     70 	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
     71 	GEM_BUG_ON(copied < sizeof(rsa));
     72 
     73 	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
     74 		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
     75 }
     76 
     77 /*
     78  * Read the GuC status register (GUC_STATUS) and store it in the
     79  * specified location; then return a boolean indicating whether
     80  * the value matches either of two values representing completion
     81  * of the GuC boot process.
     82  *
     83  * This is used for polling the GuC status in a wait_for()
     84  * loop below.
     85  */
     86 static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
     87 {
     88 	u32 val = intel_uncore_read(uncore, GUC_STATUS);
     89 	u32 uk_val = val & GS_UKERNEL_MASK;
     90 
     91 	*status = val;
     92 	return (uk_val == GS_UKERNEL_READY) ||
     93 		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
     94 }
     95 
     96 static int guc_wait_ucode(struct intel_uncore *uncore)
     97 {
     98 	u32 status;
     99 	int ret;
    100 
    101 	/*
    102 	 * Wait for the GuC to start up.
    103 	 * NB: Docs recommend not using the interrupt for completion.
    104 	 * Measurements indicate this should take no more than 20ms, so a
    105 	 * timeout here indicates that the GuC has failed and is unusable.
    106 	 * (Higher levels of the driver may decide to reset the GuC and
    107 	 * attempt the ucode load again if this happens.)
    108 	 */
    109 	ret = wait_for(guc_ready(uncore, &status), 100);
    110 	DRM_DEBUG_DRIVER("GuC status %#x\n", status);
    111 
    112 	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
    113 		DRM_ERROR("GuC firmware signature verification failed\n");
    114 		ret = -ENOEXEC;
    115 	}
    116 
    117 	if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
    118 		DRM_ERROR("GuC firmware exception. EIP: %#x\n",
    119 			  intel_uncore_read(uncore, SOFT_SCRATCH(13)));
    120 		ret = -ENXIO;
    121 	}
    122 
    123 	return ret;
    124 }
    125 
    126 /**
    127  * intel_guc_fw_upload() - load GuC uCode to device
    128  * @guc: intel_guc structure
    129  *
    130  * Called from intel_uc_init_hw() during driver load, resume from sleep and
    131  * after a GPU reset.
    132  *
    133  * The firmware image should have already been fetched into memory, so only
    134  * check that fetch succeeded, and then transfer the image to the h/w.
    135  *
    136  * Return:	non-zero code on error
    137  */
    138 int intel_guc_fw_upload(struct intel_guc *guc)
    139 {
    140 	struct intel_gt *gt = guc_to_gt(guc);
    141 	struct intel_uncore *uncore = gt->uncore;
    142 	int ret;
    143 
    144 	guc_prepare_xfer(uncore);
    145 
    146 	/*
    147 	 * Note that GuC needs the CSS header plus uKernel code to be copied
    148 	 * by the DMA engine in one operation, whereas the RSA signature is
    149 	 * loaded via MMIO.
    150 	 */
    151 	guc_xfer_rsa(&guc->fw, uncore);
    152 
    153 	/*
    154 	 * Current uCode expects the code to be loaded at 8k; locations below
    155 	 * this are used for the stack.
    156 	 */
    157 	ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
    158 	if (ret)
    159 		goto out;
    160 
    161 	ret = guc_wait_ucode(uncore);
    162 	if (ret)
    163 		goto out;
    164 
    165 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
    166 	return 0;
    167 
    168 out:
    169 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL);
    170 	return ret;
    171 }
    172