1 /* $NetBSD: fb_decoder.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */ 2 3 /* 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Kevin Tian <kevin.tian (at) intel.com> 27 * 28 * Contributors: 29 * Bing Niu <bing.niu (at) intel.com> 30 * Xu Han <xu.han (at) intel.com> 31 * Ping Gao <ping.a.gao (at) intel.com> 32 * Xiaoguang Chen <xiaoguang.chen (at) intel.com> 33 * Yang Liu <yang2.liu (at) intel.com> 34 * Tina Zhang <tina.zhang (at) intel.com> 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: fb_decoder.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $"); 40 41 #include <uapi/drm/drm_fourcc.h> 42 #include "i915_drv.h" 43 #include "gvt.h" 44 #include "i915_pvinfo.h" 45 46 #define PRIMARY_FORMAT_NUM 16 47 struct pixel_format { 48 int drm_format; /* Pixel format in DRM definition */ 49 int bpp; /* Bits per pixel, 0 indicates invalid */ 50 char *desc; /* The description */ 51 }; 52 53 static struct pixel_format bdw_pixel_formats[] = { 54 {DRM_FORMAT_C8, 8, "8-bit Indexed"}, 55 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, 56 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, 57 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, 58 59 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, 60 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, 61 62 /* non-supported format has bpp default to 0 */ 63 {0, 0, NULL}, 64 }; 65 66 static struct pixel_format skl_pixel_formats[] = { 67 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"}, 68 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"}, 69 {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"}, 70 {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"}, 71 72 {DRM_FORMAT_C8, 8, "8-bit Indexed"}, 73 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, 74 {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"}, 75 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, 76 77 {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"}, 78 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, 79 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, 80 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, 81 82 /* non-supported format has bpp default to 0 */ 83 {0, 0, NULL}, 84 }; 85 86 static int bdw_format_to_drm(int format) 87 { 88 int bdw_pixel_formats_index = 6; 89 90 switch (format) { 91 case DISPPLANE_8BPP: 92 bdw_pixel_formats_index = 0; 93 break; 94 case DISPPLANE_BGRX565: 95 bdw_pixel_formats_index = 1; 96 break; 97 case DISPPLANE_BGRX888: 98 bdw_pixel_formats_index = 2; 99 break; 100 case DISPPLANE_RGBX101010: 101 bdw_pixel_formats_index = 3; 102 break; 103 case DISPPLANE_BGRX101010: 104 bdw_pixel_formats_index = 4; 105 break; 106 case DISPPLANE_RGBX888: 107 bdw_pixel_formats_index = 5; 108 break; 109 110 default: 111 break; 112 } 113 114 return bdw_pixel_formats_index; 115 } 116 117 static int skl_format_to_drm(int format, bool rgb_order, bool alpha, 118 int yuv_order) 119 { 120 int skl_pixel_formats_index = 12; 121 122 switch (format) { 123 case PLANE_CTL_FORMAT_INDEXED: 124 skl_pixel_formats_index = 4; 125 break; 126 case PLANE_CTL_FORMAT_RGB_565: 127 skl_pixel_formats_index = 5; 128 break; 129 case PLANE_CTL_FORMAT_XRGB_8888: 130 if (rgb_order) 131 skl_pixel_formats_index = alpha ? 6 : 7; 132 else 133 skl_pixel_formats_index = alpha ? 8 : 9; 134 break; 135 case PLANE_CTL_FORMAT_XRGB_2101010: 136 skl_pixel_formats_index = rgb_order ? 10 : 11; 137 break; 138 case PLANE_CTL_FORMAT_YUV422: 139 skl_pixel_formats_index = yuv_order >> 16; 140 if (skl_pixel_formats_index > 3) 141 return -EINVAL; 142 break; 143 144 default: 145 break; 146 } 147 148 return skl_pixel_formats_index; 149 } 150 151 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, 152 u32 tiled, int stride_mask, int bpp) 153 { 154 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 155 156 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; 157 u32 stride = stride_reg; 158 159 if (INTEL_GEN(dev_priv) >= 9) { 160 switch (tiled) { 161 case PLANE_CTL_TILED_LINEAR: 162 stride = stride_reg * 64; 163 break; 164 case PLANE_CTL_TILED_X: 165 stride = stride_reg * 512; 166 break; 167 case PLANE_CTL_TILED_Y: 168 stride = stride_reg * 128; 169 break; 170 case PLANE_CTL_TILED_YF: 171 if (bpp == 8) 172 stride = stride_reg * 64; 173 else if (bpp == 16 || bpp == 32 || bpp == 64) 174 stride = stride_reg * 128; 175 else 176 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp); 177 break; 178 default: 179 gvt_dbg_core("skl: unsupported tile format:%x\n", 180 tiled); 181 } 182 } 183 184 return stride; 185 } 186 187 static int get_active_pipe(struct intel_vgpu *vgpu) 188 { 189 int i; 190 191 for (i = 0; i < I915_MAX_PIPES; i++) 192 if (pipe_is_enabled(vgpu, i)) 193 break; 194 195 return i; 196 } 197 198 /** 199 * intel_vgpu_decode_primary_plane - Decode primary plane 200 * @vgpu: input vgpu 201 * @plane: primary plane to save decoded info 202 * This function is called for decoding plane 203 * 204 * Returns: 205 * 0 on success, non-zero if failed. 206 */ 207 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 208 struct intel_vgpu_primary_plane_format *plane) 209 { 210 u32 val, fmt; 211 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 212 int pipe; 213 214 pipe = get_active_pipe(vgpu); 215 if (pipe >= I915_MAX_PIPES) 216 return -ENODEV; 217 218 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); 219 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); 220 if (!plane->enabled) 221 return -ENODEV; 222 223 if (INTEL_GEN(dev_priv) >= 9) { 224 plane->tiled = val & PLANE_CTL_TILED_MASK; 225 fmt = skl_format_to_drm( 226 val & PLANE_CTL_FORMAT_MASK, 227 val & PLANE_CTL_ORDER_RGBX, 228 val & PLANE_CTL_ALPHA_MASK, 229 val & PLANE_CTL_YUV422_ORDER_MASK); 230 231 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) { 232 gvt_vgpu_err("Out-of-bounds pixel format index\n"); 233 return -EINVAL; 234 } 235 236 plane->bpp = skl_pixel_formats[fmt].bpp; 237 plane->drm_format = skl_pixel_formats[fmt].drm_format; 238 } else { 239 plane->tiled = val & DISPPLANE_TILED; 240 fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK); 241 plane->bpp = bdw_pixel_formats[fmt].bpp; 242 plane->drm_format = bdw_pixel_formats[fmt].drm_format; 243 } 244 245 if (!plane->bpp) { 246 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); 247 return -EINVAL; 248 } 249 250 plane->hw_format = fmt; 251 252 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; 253 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 254 return -EINVAL; 255 256 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 257 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 258 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", 259 plane->base); 260 return -EINVAL; 261 } 262 263 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, 264 (INTEL_GEN(dev_priv) >= 9) ? 265 (_PRI_PLANE_STRIDE_MASK >> 6) : 266 _PRI_PLANE_STRIDE_MASK, plane->bpp); 267 268 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> 269 _PIPE_H_SRCSZ_SHIFT; 270 plane->width += 1; 271 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & 272 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; 273 plane->height += 1; /* raw height is one minus the real value */ 274 275 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); 276 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> 277 _PRI_PLANE_X_OFF_SHIFT; 278 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> 279 _PRI_PLANE_Y_OFF_SHIFT; 280 281 return 0; 282 } 283 284 #define CURSOR_FORMAT_NUM (1 << 6) 285 struct cursor_mode_format { 286 int drm_format; /* Pixel format in DRM definition */ 287 u8 bpp; /* Bits per pixel; 0 indicates invalid */ 288 u32 width; /* In pixel */ 289 u32 height; /* In lines */ 290 char *desc; /* The description */ 291 }; 292 293 static struct cursor_mode_format cursor_pixel_formats[] = { 294 {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"}, 295 {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"}, 296 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, 297 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, 298 299 /* non-supported format has bpp default to 0 */ 300 {0, 0, 0, 0, NULL}, 301 }; 302 303 static int cursor_mode_to_drm(int mode) 304 { 305 int cursor_pixel_formats_index = 4; 306 307 switch (mode) { 308 case MCURSOR_MODE_128_ARGB_AX: 309 cursor_pixel_formats_index = 0; 310 break; 311 case MCURSOR_MODE_256_ARGB_AX: 312 cursor_pixel_formats_index = 1; 313 break; 314 case MCURSOR_MODE_64_ARGB_AX: 315 cursor_pixel_formats_index = 2; 316 break; 317 case MCURSOR_MODE_64_32B_AX: 318 cursor_pixel_formats_index = 3; 319 break; 320 321 default: 322 break; 323 } 324 325 return cursor_pixel_formats_index; 326 } 327 328 /** 329 * intel_vgpu_decode_cursor_plane - Decode sprite plane 330 * @vgpu: input vgpu 331 * @plane: cursor plane to save decoded info 332 * This function is called for decoding plane 333 * 334 * Returns: 335 * 0 on success, non-zero if failed. 336 */ 337 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 338 struct intel_vgpu_cursor_plane_format *plane) 339 { 340 u32 val, mode, index; 341 u32 alpha_plane, alpha_force; 342 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 343 int pipe; 344 345 pipe = get_active_pipe(vgpu); 346 if (pipe >= I915_MAX_PIPES) 347 return -ENODEV; 348 349 val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); 350 mode = val & MCURSOR_MODE; 351 plane->enabled = (mode != MCURSOR_MODE_DISABLE); 352 if (!plane->enabled) 353 return -ENODEV; 354 355 index = cursor_mode_to_drm(mode); 356 357 if (!cursor_pixel_formats[index].bpp) { 358 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode); 359 return -EINVAL; 360 } 361 plane->mode = mode; 362 plane->bpp = cursor_pixel_formats[index].bpp; 363 plane->drm_format = cursor_pixel_formats[index].drm_format; 364 plane->width = cursor_pixel_formats[index].width; 365 plane->height = cursor_pixel_formats[index].height; 366 367 alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >> 368 _CURSOR_ALPHA_PLANE_SHIFT; 369 alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >> 370 _CURSOR_ALPHA_FORCE_SHIFT; 371 if (alpha_plane || alpha_force) 372 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", 373 alpha_plane, alpha_force); 374 375 plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; 376 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 377 return -EINVAL; 378 379 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 380 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 381 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n", 382 plane->base); 383 return -EINVAL; 384 } 385 386 val = vgpu_vreg_t(vgpu, CURPOS(pipe)); 387 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; 388 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; 389 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; 390 plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; 391 392 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); 393 plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)); 394 return 0; 395 } 396 397 #define SPRITE_FORMAT_NUM (1 << 3) 398 399 static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = { 400 [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"}, 401 [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"}, 402 [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"}, 403 [0x4] = {DRM_FORMAT_AYUV, 32, 404 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"}, 405 }; 406 407 /** 408 * intel_vgpu_decode_sprite_plane - Decode sprite plane 409 * @vgpu: input vgpu 410 * @plane: sprite plane to save decoded info 411 * This function is called for decoding plane 412 * 413 * Returns: 414 * 0 on success, non-zero if failed. 415 */ 416 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 417 struct intel_vgpu_sprite_plane_format *plane) 418 { 419 u32 val, fmt; 420 u32 color_order, yuv_order; 421 int drm_format; 422 int pipe; 423 424 pipe = get_active_pipe(vgpu); 425 if (pipe >= I915_MAX_PIPES) 426 return -ENODEV; 427 428 val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); 429 plane->enabled = !!(val & SPRITE_ENABLE); 430 if (!plane->enabled) 431 return -ENODEV; 432 433 plane->tiled = !!(val & SPRITE_TILED); 434 color_order = !!(val & SPRITE_RGB_ORDER_RGBX); 435 yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >> 436 _SPRITE_YUV_ORDER_SHIFT; 437 438 fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT; 439 if (!sprite_pixel_formats[fmt].bpp) { 440 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); 441 return -EINVAL; 442 } 443 plane->hw_format = fmt; 444 plane->bpp = sprite_pixel_formats[fmt].bpp; 445 drm_format = sprite_pixel_formats[fmt].drm_format; 446 447 /* Order of RGB values in an RGBxxx buffer may be ordered RGB or 448 * BGR depending on the state of the color_order field 449 */ 450 if (!color_order) { 451 if (drm_format == DRM_FORMAT_XRGB2101010) 452 drm_format = DRM_FORMAT_XBGR2101010; 453 else if (drm_format == DRM_FORMAT_XRGB8888) 454 drm_format = DRM_FORMAT_XBGR8888; 455 } 456 457 if (drm_format == DRM_FORMAT_YUV422) { 458 switch (yuv_order) { 459 case 0: 460 drm_format = DRM_FORMAT_YUYV; 461 break; 462 case 1: 463 drm_format = DRM_FORMAT_UYVY; 464 break; 465 case 2: 466 drm_format = DRM_FORMAT_YVYU; 467 break; 468 case 3: 469 drm_format = DRM_FORMAT_VYUY; 470 break; 471 default: 472 /* yuv_order has only 2 bits */ 473 break; 474 } 475 } 476 477 plane->drm_format = drm_format; 478 479 plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; 480 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 481 return -EINVAL; 482 483 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 484 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 485 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", 486 plane->base); 487 return -EINVAL; 488 } 489 490 plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) & 491 _SPRITE_STRIDE_MASK; 492 493 val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); 494 plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> 495 _SPRITE_SIZE_HEIGHT_SHIFT; 496 plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> 497 _SPRITE_SIZE_WIDTH_SHIFT; 498 plane->height += 1; /* raw height is one minus the real value */ 499 plane->width += 1; /* raw width is one minus the real value */ 500 501 val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); 502 plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; 503 plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; 504 505 val = vgpu_vreg_t(vgpu, SPROFFSET(pipe)); 506 plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> 507 _SPRITE_OFFSET_START_X_SHIFT; 508 plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> 509 _SPRITE_OFFSET_START_Y_SHIFT; 510 511 return 0; 512 } 513
Indexes created Sun Sep 21 15:09:59 GMT 2025