1 /* $NetBSD: intel_wopcm.c,v 1.3 2021/12/19 11:49:11 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: MIT 4 /* 5 * Copyright 2017-2019 Intel Corporation 6 */ 7 8 #include <sys/cdefs.h> 9 __KERNEL_RCSID(0, "$NetBSD: intel_wopcm.c,v 1.3 2021/12/19 11:49:11 riastradh Exp $"); 10 11 #include "intel_wopcm.h" 12 #include "i915_drv.h" 13 14 #include <linux/nbsd-namespace.h> 15 16 /** 17 * DOC: WOPCM Layout 18 * 19 * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and 20 * offset registers whose values are calculated and determined by HuC/GuC 21 * firmware size and set of hardware requirements/restrictions as shown below: 22 * 23 * :: 24 * 25 * +=========> +====================+ <== WOPCM Top 26 * ^ | HW contexts RSVD | 27 * | +===> +====================+ <== GuC WOPCM Top 28 * | ^ | | 29 * | | | | 30 * | | | | 31 * | GuC | | 32 * | WOPCM | | 33 * | Size +--------------------+ 34 * WOPCM | | GuC FW RSVD | 35 * | | +--------------------+ 36 * | | | GuC Stack RSVD | 37 * | | +------------------- + 38 * | v | GuC WOPCM RSVD | 39 * | +===> +====================+ <== GuC WOPCM base 40 * | | WOPCM RSVD | 41 * | +------------------- + <== HuC Firmware Top 42 * v | HuC FW | 43 * +=========> +====================+ <== WOPCM Base 44 * 45 * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. 46 * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 47 * context). 48 */ 49 50 /* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */ 51 #define GEN11_WOPCM_SIZE SZ_2M 52 #define GEN9_WOPCM_SIZE SZ_1M 53 /* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */ 54 #define WOPCM_RESERVED_SIZE SZ_16K 55 56 /* 16KB reserved at the beginning of GuC WOPCM. */ 57 #define GUC_WOPCM_RESERVED SZ_16K 58 /* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */ 59 #define GUC_WOPCM_STACK_RESERVED SZ_8K 60 61 /* GuC WOPCM Offset value needs to be aligned to 16KB. */ 62 #define GUC_WOPCM_OFFSET_ALIGNMENT (1UL << GUC_WOPCM_OFFSET_SHIFT) 63 64 /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */ 65 #define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K) 66 /* 36KB WOPCM reserved at the end of WOPCM on CNL. */ 67 #define CNL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K) 68 69 /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */ 70 #define GEN9_GUC_FW_RESERVED SZ_128K 71 #define GEN9_GUC_WOPCM_OFFSET (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED) 72 73 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm) 74 { 75 return container_of(wopcm, struct drm_i915_private, wopcm); 76 } 77 78 /** 79 * intel_wopcm_init_early() - Early initialization of the WOPCM. 80 * @wopcm: pointer to intel_wopcm. 81 * 82 * Setup the size of WOPCM which will be used by later on WOPCM partitioning. 83 */ 84 void intel_wopcm_init_early(struct intel_wopcm *wopcm) 85 { 86 struct drm_i915_private *i915 = wopcm_to_i915(wopcm); 87 88 if (!HAS_GT_UC(i915)) 89 return; 90 91 if (INTEL_GEN(i915) >= 11) 92 wopcm->size = GEN11_WOPCM_SIZE; 93 else 94 wopcm->size = GEN9_WOPCM_SIZE; 95 96 DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "WOPCM: %uK\n", wopcm->size / 1024); 97 } 98 99 static inline u32 context_reserved_size(struct drm_i915_private *i915) 100 { 101 if (IS_GEN9_LP(i915)) 102 return BXT_WOPCM_RC6_CTX_RESERVED; 103 else if (INTEL_GEN(i915) >= 10) 104 return CNL_WOPCM_HW_CTX_RESERVED; 105 else 106 return 0; 107 } 108 109 static inline bool gen9_check_dword_gap(struct drm_i915_private *i915, 110 u32 guc_wopcm_base, u32 guc_wopcm_size) 111 { 112 u32 offset; 113 114 /* 115 * GuC WOPCM size shall be at least a dword larger than the offset from 116 * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET) 117 * due to hardware limitation on Gen9. 118 */ 119 offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET; 120 if (offset > guc_wopcm_size || 121 (guc_wopcm_size - offset) < sizeof(u32)) { 122 dev_err(i915->drm.dev, 123 "WOPCM: invalid GuC region size: %uK < %uK\n", 124 guc_wopcm_size / SZ_1K, 125 (u32)(offset + sizeof(u32)) / SZ_1K); 126 return false; 127 } 128 129 return true; 130 } 131 132 static inline bool gen9_check_huc_fw_fits(struct drm_i915_private *i915, 133 u32 guc_wopcm_size, u32 huc_fw_size) 134 { 135 /* 136 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM 137 * size to be larger than or equal to HuC firmware size. Otherwise, 138 * firmware uploading would fail. 139 */ 140 if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) { 141 dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", 142 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC), 143 (guc_wopcm_size - GUC_WOPCM_RESERVED) / SZ_1K, 144 huc_fw_size / 1024); 145 return false; 146 } 147 148 return true; 149 } 150 151 static inline bool check_hw_restrictions(struct drm_i915_private *i915, 152 u32 guc_wopcm_base, u32 guc_wopcm_size, 153 u32 huc_fw_size) 154 { 155 if (IS_GEN(i915, 9) && !gen9_check_dword_gap(i915, guc_wopcm_base, 156 guc_wopcm_size)) 157 return false; 158 159 if ((IS_GEN(i915, 9) || 160 IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)) && 161 !gen9_check_huc_fw_fits(i915, guc_wopcm_size, huc_fw_size)) 162 return false; 163 164 return true; 165 } 166 167 static inline bool __check_layout(struct drm_i915_private *i915, u32 wopcm_size, 168 u32 guc_wopcm_base, u32 guc_wopcm_size, 169 u32 guc_fw_size, u32 huc_fw_size) 170 { 171 const u32 ctx_rsvd = context_reserved_size(i915); 172 u32 size; 173 174 size = wopcm_size - ctx_rsvd; 175 if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) { 176 dev_err(i915->drm.dev, 177 "WOPCM: invalid GuC region layout: %uK + %uK > %uK\n", 178 guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K, 179 size / SZ_1K); 180 return false; 181 } 182 183 size = guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED; 184 if (unlikely(guc_wopcm_size < size)) { 185 dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", 186 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), 187 guc_wopcm_size / SZ_1K, size / SZ_1K); 188 return false; 189 } 190 191 size = huc_fw_size + WOPCM_RESERVED_SIZE; 192 if (unlikely(guc_wopcm_base < size)) { 193 dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", 194 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC), 195 guc_wopcm_base / SZ_1K, size / SZ_1K); 196 return false; 197 } 198 199 return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size, 200 huc_fw_size); 201 } 202 203 static bool __wopcm_regs_locked(struct intel_uncore *uncore, 204 u32 *guc_wopcm_base, u32 *guc_wopcm_size) 205 { 206 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); 207 u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE); 208 209 if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) || 210 !(reg_base & GUC_WOPCM_OFFSET_VALID)) 211 return false; 212 213 *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK; 214 *guc_wopcm_size = reg_size & GUC_WOPCM_SIZE_MASK; 215 return true; 216 } 217 218 /** 219 * intel_wopcm_init() - Initialize the WOPCM structure. 220 * @wopcm: pointer to intel_wopcm. 221 * 222 * This function will partition WOPCM space based on GuC and HuC firmware sizes 223 * and will allocate max remaining for use by GuC. This function will also 224 * enforce platform dependent hardware restrictions on GuC WOPCM offset and 225 * size. It will fail the WOPCM init if any of these checks fail, so that the 226 * following WOPCM registers setup and GuC firmware uploading would be aborted. 227 */ 228 void intel_wopcm_init(struct intel_wopcm *wopcm) 229 { 230 struct drm_i915_private *i915 = wopcm_to_i915(wopcm); 231 struct intel_gt *gt = &i915->gt; 232 u32 guc_fw_size = intel_uc_fw_get_upload_size(>->uc.guc.fw); 233 u32 huc_fw_size = intel_uc_fw_get_upload_size(>->uc.huc.fw); 234 u32 ctx_rsvd = context_reserved_size(i915); 235 u32 guc_wopcm_base; 236 u32 guc_wopcm_size; 237 238 if (!guc_fw_size) 239 return; 240 241 GEM_BUG_ON(!wopcm->size); 242 GEM_BUG_ON(wopcm->guc.base); 243 GEM_BUG_ON(wopcm->guc.size); 244 GEM_BUG_ON(guc_fw_size >= wopcm->size); 245 GEM_BUG_ON(huc_fw_size >= wopcm->size); 246 GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm->size); 247 248 if (i915_inject_probe_failure(i915)) 249 return; 250 251 if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) { 252 DRM_DEV_DEBUG_DRIVER(i915->drm.dev, 253 "GuC WOPCM is already locked [%uK, %uK)\n", 254 guc_wopcm_base / SZ_1K, 255 guc_wopcm_size / SZ_1K); 256 goto check; 257 } 258 259 /* 260 * Aligned value of guc_wopcm_base will determine available WOPCM space 261 * for HuC firmware and mandatory reserved area. 262 */ 263 guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE; 264 guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT); 265 266 /* 267 * Need to clamp guc_wopcm_base now to make sure the following math is 268 * correct. Formal check of whole WOPCM layout will be done below. 269 */ 270 guc_wopcm_base = min(guc_wopcm_base, wopcm->size - ctx_rsvd); 271 272 /* Aligned remainings of usable WOPCM space can be assigned to GuC. */ 273 guc_wopcm_size = wopcm->size - ctx_rsvd - guc_wopcm_base; 274 guc_wopcm_size &= GUC_WOPCM_SIZE_MASK; 275 276 DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "Calculated GuC WOPCM [%uK, %uK)\n", 277 guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K); 278 279 check: 280 if (__check_layout(i915, wopcm->size, guc_wopcm_base, guc_wopcm_size, 281 guc_fw_size, huc_fw_size)) { 282 wopcm->guc.base = guc_wopcm_base; 283 wopcm->guc.size = guc_wopcm_size; 284 GEM_BUG_ON(!wopcm->guc.base); 285 GEM_BUG_ON(!wopcm->guc.size); 286 } 287 } 288
Indexes created Sun Sep 21 20:09:37 GMT 2025