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      1 /*	$NetBSD: irq_types.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012-15 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: AMD
     25  *
     26  */
     27 
     28 #ifndef __DAL_IRQ_TYPES_H__
     29 #define __DAL_IRQ_TYPES_H__
     30 
     31 #include "os_types.h"
     32 
     33 struct dc_context;
     34 
     35 typedef void (*interrupt_handler)(void *);
     36 
     37 typedef void *irq_handler_idx;
     38 #define DAL_INVALID_IRQ_HANDLER_IDX NULL
     39 
     40 /* The order of the IRQ sources is important and MUST match the one's
     41 of base driver */
     42 enum dc_irq_source {
     43 	/* Use as mask to specify invalid irq source */
     44 	DC_IRQ_SOURCE_INVALID = 0,
     45 
     46 	DC_IRQ_SOURCE_HPD1,
     47 	DC_IRQ_SOURCE_HPD2,
     48 	DC_IRQ_SOURCE_HPD3,
     49 	DC_IRQ_SOURCE_HPD4,
     50 	DC_IRQ_SOURCE_HPD5,
     51 	DC_IRQ_SOURCE_HPD6,
     52 
     53 	DC_IRQ_SOURCE_HPD1RX,
     54 	DC_IRQ_SOURCE_HPD2RX,
     55 	DC_IRQ_SOURCE_HPD3RX,
     56 	DC_IRQ_SOURCE_HPD4RX,
     57 	DC_IRQ_SOURCE_HPD5RX,
     58 	DC_IRQ_SOURCE_HPD6RX,
     59 
     60 	DC_IRQ_SOURCE_I2C_DDC1,
     61 	DC_IRQ_SOURCE_I2C_DDC2,
     62 	DC_IRQ_SOURCE_I2C_DDC3,
     63 	DC_IRQ_SOURCE_I2C_DDC4,
     64 	DC_IRQ_SOURCE_I2C_DDC5,
     65 	DC_IRQ_SOURCE_I2C_DDC6,
     66 
     67 	DC_IRQ_SOURCE_DPSINK1,
     68 	DC_IRQ_SOURCE_DPSINK2,
     69 	DC_IRQ_SOURCE_DPSINK3,
     70 	DC_IRQ_SOURCE_DPSINK4,
     71 	DC_IRQ_SOURCE_DPSINK5,
     72 	DC_IRQ_SOURCE_DPSINK6,
     73 
     74 	DC_IRQ_SOURCE_TIMER,
     75 
     76 	DC_IRQ_SOURCE_PFLIP_FIRST,
     77 	DC_IRQ_SOURCE_PFLIP1 = DC_IRQ_SOURCE_PFLIP_FIRST,
     78 	DC_IRQ_SOURCE_PFLIP2,
     79 	DC_IRQ_SOURCE_PFLIP3,
     80 	DC_IRQ_SOURCE_PFLIP4,
     81 	DC_IRQ_SOURCE_PFLIP5,
     82 	DC_IRQ_SOURCE_PFLIP6,
     83 	DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
     84 	DC_IRQ_SOURCE_PFLIP_LAST = DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
     85 
     86 	DC_IRQ_SOURCE_GPIOPAD0,
     87 	DC_IRQ_SOURCE_GPIOPAD1,
     88 	DC_IRQ_SOURCE_GPIOPAD2,
     89 	DC_IRQ_SOURCE_GPIOPAD3,
     90 	DC_IRQ_SOURCE_GPIOPAD4,
     91 	DC_IRQ_SOURCE_GPIOPAD5,
     92 	DC_IRQ_SOURCE_GPIOPAD6,
     93 	DC_IRQ_SOURCE_GPIOPAD7,
     94 	DC_IRQ_SOURCE_GPIOPAD8,
     95 	DC_IRQ_SOURCE_GPIOPAD9,
     96 	DC_IRQ_SOURCE_GPIOPAD10,
     97 	DC_IRQ_SOURCE_GPIOPAD11,
     98 	DC_IRQ_SOURCE_GPIOPAD12,
     99 	DC_IRQ_SOURCE_GPIOPAD13,
    100 	DC_IRQ_SOURCE_GPIOPAD14,
    101 	DC_IRQ_SOURCE_GPIOPAD15,
    102 	DC_IRQ_SOURCE_GPIOPAD16,
    103 	DC_IRQ_SOURCE_GPIOPAD17,
    104 	DC_IRQ_SOURCE_GPIOPAD18,
    105 	DC_IRQ_SOURCE_GPIOPAD19,
    106 	DC_IRQ_SOURCE_GPIOPAD20,
    107 	DC_IRQ_SOURCE_GPIOPAD21,
    108 	DC_IRQ_SOURCE_GPIOPAD22,
    109 	DC_IRQ_SOURCE_GPIOPAD23,
    110 	DC_IRQ_SOURCE_GPIOPAD24,
    111 	DC_IRQ_SOURCE_GPIOPAD25,
    112 	DC_IRQ_SOURCE_GPIOPAD26,
    113 	DC_IRQ_SOURCE_GPIOPAD27,
    114 	DC_IRQ_SOURCE_GPIOPAD28,
    115 	DC_IRQ_SOURCE_GPIOPAD29,
    116 	DC_IRQ_SOURCE_GPIOPAD30,
    117 
    118 	DC_IRQ_SOURCE_DC1UNDERFLOW,
    119 	DC_IRQ_SOURCE_DC2UNDERFLOW,
    120 	DC_IRQ_SOURCE_DC3UNDERFLOW,
    121 	DC_IRQ_SOURCE_DC4UNDERFLOW,
    122 	DC_IRQ_SOURCE_DC5UNDERFLOW,
    123 	DC_IRQ_SOURCE_DC6UNDERFLOW,
    124 
    125 	DC_IRQ_SOURCE_DMCU_SCP,
    126 	DC_IRQ_SOURCE_VBIOS_SW,
    127 
    128 	DC_IRQ_SOURCE_VUPDATE1,
    129 	DC_IRQ_SOURCE_VUPDATE2,
    130 	DC_IRQ_SOURCE_VUPDATE3,
    131 	DC_IRQ_SOURCE_VUPDATE4,
    132 	DC_IRQ_SOURCE_VUPDATE5,
    133 	DC_IRQ_SOURCE_VUPDATE6,
    134 
    135 	DC_IRQ_SOURCE_VBLANK1,
    136 	DC_IRQ_SOURCE_VBLANK2,
    137 	DC_IRQ_SOURCE_VBLANK3,
    138 	DC_IRQ_SOURCE_VBLANK4,
    139 	DC_IRQ_SOURCE_VBLANK5,
    140 	DC_IRQ_SOURCE_VBLANK6,
    141 
    142 	DC_IRQ_SOURCE_DC1_VLINE0,
    143 	DC_IRQ_SOURCE_DC2_VLINE0,
    144 	DC_IRQ_SOURCE_DC3_VLINE0,
    145 	DC_IRQ_SOURCE_DC4_VLINE0,
    146 	DC_IRQ_SOURCE_DC5_VLINE0,
    147 	DC_IRQ_SOURCE_DC6_VLINE0,
    148 
    149 	DC_IRQ_SOURCE_DC1_VLINE1,
    150 	DC_IRQ_SOURCE_DC2_VLINE1,
    151 	DC_IRQ_SOURCE_DC3_VLINE1,
    152 	DC_IRQ_SOURCE_DC4_VLINE1,
    153 	DC_IRQ_SOURCE_DC5_VLINE1,
    154 	DC_IRQ_SOURCE_DC6_VLINE1,
    155 
    156 
    157 	DAL_IRQ_SOURCES_NUMBER
    158 };
    159 
    160 enum irq_type
    161 {
    162 	IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
    163 	IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
    164 	IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
    165 };
    166 
    167 #define DAL_VALID_IRQ_SRC_NUM(src) \
    168 	((src) <= DAL_IRQ_SOURCES_NUMBER && (src) > DC_IRQ_SOURCE_INVALID)
    169 
    170 /* Number of Page Flip IRQ Sources. */
    171 #define DAL_PFLIP_IRQ_SRC_NUM \
    172 	(DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1)
    173 
    174 /* the number of contexts may be expanded in the future based on needs */
    175 enum dc_interrupt_context {
    176 	INTERRUPT_LOW_IRQ_CONTEXT = 0,
    177 	INTERRUPT_HIGH_IRQ_CONTEXT,
    178 	INTERRUPT_CONTEXT_NUMBER
    179 };
    180 
    181 enum dc_interrupt_porlarity {
    182 	INTERRUPT_POLARITY_DEFAULT = 0,
    183 	INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
    184 	INTERRUPT_POLARITY_HIGH,
    185 	INTERRUPT_POLARITY_BOTH
    186 };
    187 
    188 #define DC_DECODE_INTERRUPT_POLARITY(int_polarity) \
    189 	(int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \
    190 	(int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \
    191 	(int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"
    192 
    193 struct dc_timer_interrupt_params {
    194 	uint32_t micro_sec_interval;
    195 	enum dc_interrupt_context int_context;
    196 };
    197 
    198 struct dc_interrupt_params {
    199 	/* The polarity *change* which will trigger an interrupt.
    200 	 * If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
    201 	 * 'current_polarity' must be initialised. */
    202 	enum dc_interrupt_porlarity requested_polarity;
    203 	/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
    204 	 * 'current_polarity' should contain the current state, which means
    205 	 * the interrupt will be triggered when state changes from what is,
    206 	 * in 'current_polarity'. */
    207 	enum dc_interrupt_porlarity current_polarity;
    208 	enum dc_irq_source irq_source;
    209 	enum dc_interrupt_context int_context;
    210 };
    211 
    212 #endif
    213