| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/ |
| mt8167.dtsi | 174 iommu: m4u@10203000 { label
179 #iommu-cells = <1>;
|
| mt8183.dtsi | 617 iommu: iommu@10205000 { label
623 #iommu-cells = <1>;
1241 iommus = <&iommu M4U_PORT_DISP_OVL0>;
1252 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
1263 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
1274 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1286 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
|
| mt8173.dtsi | 585 iommu: iommu@10205000 { label
593 #iommu-cells = <1>;
1011 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1022 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
1052 iommus = <&iommu M4U_PORT_MDP_WDMA>;
1061 iommus = <&iommu M4U_PORT_MDP_WROT0>;
1070 iommus = <&iommu M4U_PORT_MDP_WROT1>;
1080 iommus = <&iommu M4U_PORT_DISP_OVL0>;
1091 iommus = <&iommu M4U_PORT_DISP_OVL1>
[all...] |
| /src/sys/dev/fdt/ |
| fdt_iommu.c | 54 * Return the iommu registered with the specified node, or NULL if
60 struct fdtbus_iommu *iommu; local in function:fdtbus_get_iommu
62 LIST_FOREACH(iommu, &fdtbus_iommus, iommu_next) {
63 if (iommu->iommu_phandle == phandle) {
64 return iommu;
74 * Register an IOMMU on the specified node.
80 struct fdtbus_iommu *iommu; local in function:fdtbus_register_iommu
87 if (of_getprop_uint32(phandle, "#iommu-cells", &cells) != 0) {
95 iommu = kmem_alloc(sizeof(*iommu), KM_SLEEP)
117 struct fdtbus_iommu *iommu; local in function:fdtbus_iommu_map
158 struct fdtbus_iommu *iommu; local in function:fdtbus_iommu_map_pci
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/ |
| tegra.h | 31 } iommu; member in struct:nvkm_device_tegra
39 * If an IOMMU is used, indicates which address bit will trigger a
40 * IOMMU translation when set (when this bit is not set, IOMMU is
41 * bypassed). A value of 0 means an IOMMU is never used.
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| mt7623n.dtsi | 103 iommu: mmsys_iommu@10205000 { label
111 #iommu-cells = <1>;
125 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
126 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
146 iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
156 iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
166 iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
217 iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
|
| mt2701.dtsi | 219 iommu: mmsys_iommu@10205000 { label
226 #iommu-cells = <1>;
568 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
569 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
581 iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
582 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
|
| /src/sys/arch/sparc64/sparc64/ |
| sysioreg.h | 41 * sysio is the sun5/sun4u SBUS controller/DMA/IOMMU/etc. ASIC.
73 uint64_t iommu_cr; /* IOMMU control register */ /* 1fe.0000.2400 */
74 uint64_t iommu_tsb; /* IOMMU TSB base register */ /* 1fe.0000.2408 */
75 uint64_t iommu_flush; /* IOMMU flush register */ /* 1fe.0000.2410 */
76 } iommu; member in struct:sysioreg
107 uint64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/ |
| sun50i-h6.dtsi | 156 iommus = <&iommu 0>;
182 iommus = <&iommu 3>;
446 iommu: iommu@30f0000 { label
447 compatible = "allwinner,sun50i-h6-iommu";
452 #iommu-cells = <1>;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gpu_error.h | 169 int iommu; member in struct:i915_gpu_coredump
|
| /src/sys/arch/sparc64/dev/ |
| schizoreg.h | 33 struct iommureg2 iommu; /* 0x0200 - 0x03ff */ member in struct:schizo_pbm_regs
437 { 0x000200, 8, 0, 3, "IOMMU Control Register" },
439 /* WO { 0x000210, 8, 0, 3, "IOMMU Flush Page Register" }, */
440 /* WO { 0x000218, 8, 0, 3, "IOMMU Flush Context Register" }, */
444 /* Diag { 0x00a500, 8, 0x7f, 1, "IOMMU LRU Queue Diag Reg" }, */
|
