| /src/sys/dev/fdt/ |
| fdt_iommu.c | 54 * Return the iommu registered with the specified node, or NULL if
60 struct fdtbus_iommu *iommu; local
62 LIST_FOREACH(iommu, &fdtbus_iommus, iommu_next) {
63 if (iommu->iommu_phandle == phandle) {
64 return iommu;
74 * Register an IOMMU on the specified node.
80 struct fdtbus_iommu *iommu; local
87 if (of_getprop_uint32(phandle, "#iommu-cells", &cells) != 0) {
95 iommu = kmem_alloc(sizeof(*iommu), KM_SLEEP)
117 struct fdtbus_iommu *iommu; local
158 struct fdtbus_iommu *iommu; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/ |
| tegra.h | 31 } iommu; member in struct:nvkm_device_tegra
39 * If an IOMMU is used, indicates which address bit will trigger a
40 * IOMMU translation when set (when this bit is not set, IOMMU is
41 * bypassed). A value of 0 means an IOMMU is never used.
|
| /src/sys/arch/sparc64/sparc64/ |
| sysioreg.h | 41 * sysio is the sun5/sun4u SBUS controller/DMA/IOMMU/etc. ASIC.
73 uint64_t iommu_cr; /* IOMMU control register */ /* 1fe.0000.2400 */
74 uint64_t iommu_tsb; /* IOMMU TSB base register */ /* 1fe.0000.2408 */
75 uint64_t iommu_flush; /* IOMMU flush register */ /* 1fe.0000.2410 */
76 } iommu; member in struct:sysioreg
107 uint64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gpu_error.h | 169 int iommu; member in struct:i915_gpu_coredump
|
| /src/sys/arch/sparc64/dev/ |
| schizoreg.h | 33 struct iommureg2 iommu; /* 0x0200 - 0x03ff */ member in struct:schizo_pbm_regs
437 { 0x000200, 8, 0, 3, "IOMMU Control Register" },
439 /* WO { 0x000210, 8, 0, 3, "IOMMU Flush Page Register" }, */
440 /* WO { 0x000218, 8, 0, 3, "IOMMU Flush Context Register" }, */
444 /* Diag { 0x00a500, 8, 0x7f, 1, "IOMMU LRU Queue Diag Reg" }, */
|
