1 /* $NetBSD: iommu.h,v 1.9 2013/09/06 17:43:19 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Structure and definition of descriptors used in the I/O Mapper. 34 */ 35 #ifndef _SUN3X_IOMMU_H 36 #define _SUN3X_IOMMU_H 37 38 /* The I/O Mapper is a special type of MMU in the sun3x architecture 39 * (and supposedly in the sun4m as well) that translates an address used by a 40 * device during a DMA transfer into an address on the internal system bus. 41 * In other words, it is an MMU that stands between devices wishing to do DMA 42 * transfers and main memory. In this description, the address issued by a 43 * DMA device is called a ``DVMA address'', while the address as it is 44 * translated and output from the I/O mapper is called a ``system bus address'' 45 * (sometimes known as a ``physical address''). 46 * 47 * The DVMA address space in the sun3x architecture is 24 bits wide, in 48 * contrast with the system bus address space, which is 32. The mapping of a 49 * DVMA address to a system bus address is accomplished by dividing the DVMA 50 * address space into 2048 8K pages. Each DVMA page is then mapped to a 51 * system bus address using a mapping described by a page descriptor entry 52 * within the I/O Mapper. This 2048 entry, page descriptor table is located 53 * at physical address 0x60000000 in the sun3x architecture and can be 54 * manipulated by the CPU with normal read and write cycles. 55 * 56 * In addition to describing an address mapping, a page descriptor entry also 57 * indicates whether the DVMA page is read-only, should be inhibited from 58 * caching by system caches, and whether or not DMA write transfers to it will 59 * be completed in 16 byte aligned blocks. (This last item is used for cache 60 * optimization in sun3x systems with special DMA caches.) 61 * 62 * Since not every DMA device is capable of addressing all 24 bits of the 63 * DVMA address space, each is wired so that the end of its address space is 64 * always flush against the end of the DVMA address space. That is, a device 65 * with a 16 bit address space (and hence an address space size of 64k) is 66 * wired such that it accesses the top 64k of DVMA space. 67 */ 68 69 /** I/O MAPPER Page Descriptor Entry 70 * 31 16 71 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 72 * | PAGE PHYSICAL ADDRESS BITS (31..13) | 73 * +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+ 74 * | | UNUSED | CI| BX| M | U | WP| DT | 75 * +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+ 76 * 15 0 77 * 78 * <CI> CACHE INHIBIT - When set, prevents instructions and data from the 79 * page from being cached in any system cache. 80 * <BX> FULL BLOCK XFER - When set, acts as an indicator to the caching system 81 * that all DMA transfers to this DVMA page will fill 82 * complete I/O cache blocks, eliminating the need for 83 * the cache block to be filled from main memory first 84 * before the DMA write can proceed to it. 85 * <M> MODIFIED - Set when the cpu has modified (written to) the 86 * physical page. 87 * <U> USED - Set when the cpu has accessed the physical page. 88 * <WP> WRITE PROTECT - When set, prevents all DMA devices from writing to 89 * the page. 90 * <DT> DESCRIPTOR TYPE - One of the following values: 91 * 00 = Invalid page 92 * 01 = Valid page 93 * 1x = Invalid code for a page descriptor. 94 */ 95 struct iommu_pde_struct { 96 union { 97 struct { 98 u_int pa:19; /* Physical Address */ 99 u_int unused:6; /* Unused bits */ 100 u_int ci:1; /* Cache Inhibit */ 101 u_int bx:1; /* Full Block Xfer */ 102 u_int m:1; /* Modified bit */ 103 u_int u:1; /* Used bit */ 104 u_int wp:1; /* Write Protect bit */ 105 u_int dt:2; /* Descriptor type */ 106 /* Masks for the above fields. */ 107 #define IOMMU_PDE_PA 0xFFFFE000 108 #define IOMMU_PDE_UNUSED 0x00001F80 109 #define IOMMU_PDE_CI 0x00000040 110 #define IOMMU_PDE_BX 0x00000020 111 #define IOMMU_PDE_M 0x00000010 112 #define IOMMU_PDE_USED 0x00000008 113 #define IOMMU_PDE_WP 0x00000004 114 #define IOMMU_PDE_DT 0x00000003 115 /* The descriptor types */ 116 #define IOMMU_PDE_DT_INVALID 0x00000000 /* Invalid page */ 117 #define IOMMU_PDE_DT_VALID 0x00000001 /* Valid page */ 118 } stc; 119 uint32_t raw; /* For unstructured access to the above */ 120 } addr; 121 }; 122 typedef struct iommu_pde_struct iommu_pde_t; 123 124 /* Constants */ 125 #define IOMMU_PAGE_SIZE (8 * 1024) 126 #define IOMMU_PAGE_SHIFT 13 127 128 /* Useful macros */ 129 #define IOMMU_PA_PDE(pde) ((pde).addr.raw & IOMMU_PDE_PA) 130 #define IOMMU_VALID_DT(pde) ((pde).addr.raw & IOMMU_PDE_DT) /* X1 */ 131 #define IOMMU_BTOP(pa) (((u_int) pa) >> IOMMU_PAGE_SHIFT) 132 133 /* X1: This macro will incorrectly report the validity for entries which 134 * contain codes that are invalid. (Do not confuse this with the code for 135 * 'invalid entry', which means that the descriptor is properly formed, but 136 * just not used.) 137 */ 138 139 /* Constants for the I/O mapper as used in the sun3x */ 140 #define IOMMU_NENT 2048 /* Number of PTEs in the map */ 141 /* Similarly, the virtual address mask. */ 142 #define IOMMU_VA_MASK 0xFFffff /* 16MB */ 143 144 #ifdef _KERNEL 145 /* Interfaces for manipulating the I/O mapper */ 146 void iommu_enter(uint32_t, uint32_t); 147 void iommu_remove(uint32_t, uint32_t); 148 #endif /* _KERNEL */ 149 150 #endif /* _SUN3X_IOMMU_H */ 151
Indexes created Wed Sep 24 15:09:51 GMT 2025