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      1 /*	$NetBSD: gemini_ipmvar.h,v 1.2 2024/02/10 08:24:50 andvar Exp $	*/
      2 
      3 #ifndef _GEMINI_IPMVAR_H_
      4 #define _GEMINI_IPMVAR_H_
      5 
      6 /*
      7  * message queue
      8  *
      9  * - the queue gets located in memory shared between cores
     10  * - is mapped non-cached so SW coherency is not required.
     11  * - be sure ipm_queue_t starts on 32 bit (min) boundary to align descriptors
     12  * - note that indices are 8 bit and NIPMDESC < (1<<8)
     13  *   be sure to adjust typedef if size is increased
     14  * - current sizes, typedef, and padding make sizeof(ipm_queue_t) == 4096
     15  */
     16 typedef uint32_t ipmqindex_t;
     17 #define NIPMDESC	255
     18 #define IPMQPADSZ	(4096 - ((sizeof(ipm_desc_t) * NIPMDESC) + (2 * sizeof(ipmqindex_t))))
     19 typedef struct ipm_queue {
     20 	ipm_desc_t ipm_desc[NIPMDESC];
     21 	volatile ipmqindex_t ix_write; /* writer increments and inserts here  */
     22 	volatile ipmqindex_t ix_read;  /* reader extracts here and increments */
     23 	uint8_t pad[IPMQPADSZ];
     24 } ipm_queue_t;
     25 
     26 static inline ipmqindex_t
     27 ipmqnext(ipmqindex_t ix)
     28 {
     29 	if (++ix >= NIPMDESC)
     30 		ix = 0;
     31 	return ix;
     32 }
     33 
     34 static inline bool
     35 ipmqisempty(ipmqindex_t ixr, ipmqindex_t ixw)
     36 {
     37 	if (ixr == ixw)
     38 		return TRUE;
     39 	return FALSE;
     40 }
     41 
     42 static inline bool
     43 ipmqisfull(ipmqindex_t ixr, ipmqindex_t ixw)
     44 {
     45 	if (ipmqnext(ixw) == ixr)
     46 		return TRUE;
     47 	return FALSE;
     48 }
     49 
     50 #endif	/* _GEMINI_IPMVAR_H_ */
     51