| /src/sys/arch/evbppc/nintendo/ |
| pic_pi.c | 57 uint32_t irqmask; member in struct:pic_state
91 pic_s[cpu_num].irqmask |= __BIT(irq);
92 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
100 pic_s[cpu_num].irqmask &= ~__BIT(irq);
101 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
134 pend = raw & pic_s[cpu_num].irqmask;
141 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
152 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
174 pic_s[cpu_num].irqmask = 0;
|
| /src/sys/arch/mips/adm5120/ |
| adm5120_intr.c | 188 uint32_t irqmask; local
215 irqmask = 1 << irq;
220 REG_READ(ICU_MODE_REG) | irqmask);
223 REG_READ(ICU_MODE_REG) & ~irqmask);
226 REG_WRITE(ICU_ENABLE_REG, irqmask);
238 uint32_t irqmask; local
254 irqmask = 1 << irq; /* only used as a mask from here on */
257 REG_WRITE(ICU_DISABLE_REG, irqmask);
268 uint32_t irqmask, irqstat; local
281 irqmask = 1 << ih->ih_irq
[all...] |
| /src/sys/arch/mips/alchemy/ |
| au_icu.c | 316 uint32_t icu_base, irqstat, irqmask; local
355 irqmask = REGVAL(icu_base + IC_MASK_READ);
360 if (mask & irqmask & irqstat) {
|
| /src/sys/arch/powerpc/ibm4xx/ |
| pic_uic.c | 340 const uint32_t irqmask = IRQ_TO_MASK(irq); local
341 if ((uic->uic_intr_enable & irqmask) == 0)
343 uic->uic_intr_enable ^= irqmask;
347 pic->pic_name, irq, irqmask);
355 const uint32_t irqmask = IRQ_TO_MASK(irq); local
356 if ((uic->uic_intr_enable & irqmask) != 0)
358 uic->uic_intr_enable ^= irqmask;
362 pic->pic_name, irq, irqmask);
370 const uint32_t irqmask = IRQ_TO_MASK(irq); local
373 uic->uic_intr_status &= ~irqmask;
387 const uint32_t irqmask = uic->uic_intr_status; local
389 const uint32_t irqmask = (*uic->uic_mf_intr_status)(); local
[all...] |
| /src/sys/dev/pcmcia/ |
| pcmciavar.h | 99 u_int16_t irqmask; member in struct:pcmcia_config_entry
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