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    Searched defs:irqs (Results 1 - 25 of 29) sorted by relevancy

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  /src/sys/arch/x86/x86/
i8259.c 237 int irqs, irq; local in function:i8259_reinit_irqs
243 irqs = 0;
246 irqs |= 1 << irq;
247 if (irqs >= 0x100) /* any IRQs >= 8 in use */
248 irqs |= 1 << IRQ_SLAVE;
249 i8259_imen = ~irqs;
x86_softintr.c 185 /* Then figure out which IRQs use each level. */
187 uint64_t irqs = 0; local in function:x86_intr_calculatemasks
190 irqs |= 1ULL << irq;
191 ci->ci_imask[level] = irqs | unusedirqs;
  /src/sys/arch/arm/sa11x0/
sa11x0_irqhandler.c 128 /* Then figure out which IRQs use each level. */
130 int irqs = 0; local in function:intr_calculatemasks
133 irqs |= 1 << irq;
137 irqmasks[i] |= irqs;
141 irqmasks[i] &= ~irqs;
  /src/sys/arch/i386/pci/
piix.c 327 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); local in function:piix_pir_dump
334 irq = PIIX_PIRQ(irqs, i);
355 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ2); local in function:ich_pir_dump
358 irq = PIIX_PIRQ(irqs, i);
  /src/sys/arch/shark/isa/
isa_irqhandler.c 285 /* Then figure out which IRQs use each level. */
287 int irqs = 0; local in function:irq_calculatemasks
290 irqs |= 1 << irq;
291 irqmasks[level] = ~irqs;
  /src/sys/arch/arm/footbridge/
footbridge_irqhandler.c 69 /* Software copy of the IRQs we have enabled. */
126 /* Next, figure out which IRQs are used by each IPL. */
128 int irqs = 0; local in function:footbridge_intr_calculate_masks
131 irqs |= (1U << irq);
133 footbridge_imask[ipl] = irqs;
155 int irqs = (1U << irq); local in function:footbridge_intr_calculate_masks
159 irqs |= footbridge_imask[ih->ih_ipl];
162 iq->iq_mask = irqs;
  /src/sys/arch/arm/footbridge/isa/
isa_machdep.c 197 /* Then figure out which IRQs use each level. */
199 int irqs = 0; local in function:intr_calculatemasks
202 irqs |= (1U << irq);
203 imask[level] = irqs;
211 int irqs = 1 << irq; local in function:intr_calculatemasks
215 irqs |= imask[ih->ih_ipl];
216 iq->iq_mask = irqs;
219 /* Lastly, determine which IRQs are actually in use. */
221 int irqs = 0; local in function:intr_calculatemasks
224 irqs |= (1U << irq)
    [all...]
  /src/sys/arch/arm/ixp12x0/
ixp12x0_intr.c 69 /* Software copy of the IRQs we have enabled. */
108 ixp12x0_set_intrmask(uint32_t irqs, uint32_t pci_irqs)
110 if (irqs & (1U << IXP12X0_INTR_UART)) {
185 /* Next, figure out which IRQs are used by each IPL. */
187 int irqs = 0; local in function:ixp12x0_intr_calculate_masks
191 irqs |= (1U << irq);
193 imask[ipl] = irqs;
228 * Now compute which IRQs must be blocked when servicing any
232 int irqs; local in function:ixp12x0_intr_calculate_masks
236 irqs = (1U << irq)
    [all...]
  /src/sys/arch/arm/xscale/
becc_icu.c 75 /* Software copy of the IRQs we have enabled. */
182 /* Next, figure out which IRQs are used by each IPL. */
184 int irqs = 0; local in function:becc_intr_calculate_masks
187 irqs |= (1U << irq);
189 becc_imask[ipl] = irqs;
204 * Now compute which IRQs must be blocked when servicing any
208 int irqs = (1U << irq); local in function:becc_intr_calculate_masks
214 irqs |= becc_imask[ih->ih_ipl];
215 iq->iq_mask = irqs;
282 /* Enable IRQs (don't yet use FIQs). *
    [all...]
ixp425_intr.c 96 /* Software copy of the IRQs we have enabled. */
207 /* Next, figure out which IRQs are used by each IPL. */
209 int irqs = 0; local in function:ixp425_intr_calculate_masks
212 irqs |= (1U << irq);
214 ixp425_imask[ipl] = irqs;
243 * Now compute which IRQs must be blocked when servicing any
247 int irqs = (1U << irq); local in function:ixp425_intr_calculate_masks
253 irqs |= ixp425_imask[ih->ih_ipl];
254 iq->iq_mask = irqs;
315 /* Enable IRQs (don't yet use FIQs). *
    [all...]
  /src/sys/arch/evbarm/ifpga/
ifpga_intr.c 66 /* Software copy of the IRQs we have enabled. */
158 /* Next, figure out which IRQs are used by each IPL. */
160 int irqs = 0; local in function:ifpga_intr_calculate_masks
163 irqs |= (1U << irq);
165 ifpga_imask[ipl] = irqs;
180 * Now compute which IRQs must be blocked when servicing any
184 int irqs = (1U << irq); local in function:ifpga_intr_calculate_masks
190 irqs |= ifpga_imask[ih->ih_ipl];
191 iq->iq_mask = irqs;
244 /* Enable IRQs (don't yet use FIQs). *
    [all...]
  /src/sys/arch/evbarm/iq80310/
iq80310_intr.c 74 /* Software copy of the IRQs we have enabled. */
162 /* Next, figure out which IRQs are used by each IPL. */
164 int irqs = 0; local in function:iq80310_intr_calculate_masks
167 irqs |= (1U << irq);
169 iq80310_imask[ipl] = irqs;
235 * Now compute which IRQs must be blocked when servicing any
239 int irqs = (1U << irq); local in function:iq80310_intr_calculate_masks
245 irqs |= iq80310_imask[ih->ih_ipl];
246 iq->iq_mask = irqs;
349 /* Enable IRQs (don't yet use FIQs). *
    [all...]
  /src/sys/arch/macppc/macppc/
pic_heathrow.c 198 uint32_t irqs, events, levels; local in function:heathrow_read_events
200 /* first the low 32 IRQs */
201 irqs = in32rb(INT_STATE_REG_L);
202 events = irqs & ~heathrow->level_mask_l;
206 out32rb(INT_CLEAR_REG_L, events | irqs);
210 irqs = in32rb(INT_STATE_REG_H);
211 events = irqs & ~heathrow->level_mask_h;
pic_ohare.c 59 uint32_t irqs[NIPL]; /* per priority level */ member in struct:ohare_ops
144 ohare->irqs[i] = 0;
204 uint32_t irqs, events, levels; local in function:ohare_read_events
206 irqs = in32rb(INT_STATE_REG);
207 events = irqs & ~ohare->level_mask;
211 out32rb(INT_CLEAR_REG, events | irqs);
264 evt = ohare->pending_events & ohare->irqs[lvl];
309 ohare->irqs[i] = 0;
315 ohare->irqs[level] |= (1 << i);
  /src/sys/external/bsd/drm/dist/shared-core/
radeon_irq.c 140 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS); local in function:radeon_acknowledge_irqs
147 if (irqs & R500_DISPLAY_INT_STATUS) {
165 irqs &= irq_mask;
167 if (irqs)
168 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
170 return irqs;
  /src/sys/dev/ic/
cpc700.c 245 u_int32_t irqs; local in function:cpc700_read_irq
247 irqs = INL(CPC_UIC_MSR);
249 if (irqs & CPC_INTR_MASK(irq))
  /src/sys/arch/powerpc/pci/
pci_machdep_ofw.c 271 uint32_t irqs[4], reg[5]; local in function:genofw_setup_pciintr_map
277 if (OF_getprop(node, "AAPL,interrupts", irqs, 4) > 0) {
295 intr_num = prop_number_create_integer(irqs[0]);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_gt_irq.c 200 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
215 const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT; local in function:gen11_gt_irq_postinstall
217 const u32 dmask = irqs << 16 | irqs;
218 const u32 smask = irqs << 16;
220 BUILD_BUG_ON(irqs & 0xffff0000);
226 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
  /src/sys/arch/arc/isa/
isabus.c 268 /* Then figure out which IRQs use each level. */
270 int irqs = 0; local in function:intr_calculatemasks
273 irqs |= 1 << irq;
274 imask[level] = irqs;
296 int irqs = 1 << irq; local in function:intr_calculatemasks
298 irqs |= imask[q->ih_level];
299 intrmask[irq] = irqs;
302 /* Lastly, determine which IRQs are actually in use. */
304 int irqs = 0; local in function:intr_calculatemasks
307 irqs |= 1 << irq
    [all...]
  /src/sys/arch/powerpc/pic/
picvar.h 40 int pic_numintrs; /* how many IRQs do we handle? */
86 uint32_t irqs; member in struct:i8259_ops
  /src/sys/arch/macppc/pci/
pci_machdep.c 161 int32_t irqs[4]; local in function:fixpci
258 len = OF_getprop(node, "AAPL,interrupts", irqs, 4);
271 len = find_node_intr(node, &iaddr.phys_hi, irqs);
281 len = find_node_intr(node, &addr[0].phys_hi, irqs);
301 irqs[0] = 60;
308 intr |= irqs[0] & PCI_INTERRUPT_LINE_MASK;
  /src/sys/arch/arm/amlogic/
meson_sdio.c 277 const u_int irqs = SDIO_READ(sc, SDIO_IRQS_REG); local in function:meson_sdio_intr
278 if (irqs & SDIO_IRQS_CLEAR) {
279 SDIO_WRITE(sc, SDIO_IRQS_REG, irqs);
280 sc->sc_intr_irqs |= irqs;
598 const uint32_t irqs = SDIO_READ(sc, SDIO_IRQS_REG); local in function:meson_sdio_exec_command
599 if ((irqs & SDIO_IRQS_CMD_BUSY) == 0)
612 const uint32_t irqs = SDIO_READ(sc, SDIO_IRQS_REG); local in function:meson_sdio_exec_command
614 if ((irqs & SDIO_IRQS_RESPONSE_CRC7_OK) == 0) {
623 if ((irqs & crcmask) == 0) {
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_guc_submission.c 564 u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; local in function:guc_interrupts_capture
565 u32 dmask = irqs << 16 | irqs;
577 u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; local in function:guc_interrupts_release
578 u32 dmask = irqs << 16 | irqs;
  /src/sys/dev/acpi/
acpi_pci_link.c 225 * systems return multiple IRQs (which is nonsense for _CRS)
253 * Populate the set of possible IRQs for each device.
261 uint8_t *irqs = NULL; local in function:link_add_prs
330 irqs = res->Data.Irq.Interrupts;
336 * Save a list of the valid IRQs. Also, if all of the
337 * valid IRQs are ISA IRQs, then mark this link as
349 link->l_irqs[i] = irqs[i];
350 if (irqs[i] >= NUM_ISA_INTERRUPTS)
410 printf("Index IRQ Rtd Ref IRQs\n")
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rs600.c 738 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); local in function:rs600_irq_ack
742 if (G_000044_DISPLAY_INT_STAT(irqs)) {
777 if (irqs) {
778 WREG32(R_000044_GEN_INT_STATUS, irqs);
780 return irqs & irq_mask;

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