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      1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
      2 //
      3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
      4 // See https://llvm.org/LICENSE.txt for license information.
      5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
      6 //
      7 //===----------------------------------------------------------------------===//
      8 //
      9 // This file declares the AArch64 specific subclass of TargetSubtarget.
     10 //
     11 //===----------------------------------------------------------------------===//
     12 
     13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
     14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
     15 
     16 #include "AArch64FrameLowering.h"
     17 #include "AArch64ISelLowering.h"
     18 #include "AArch64InstrInfo.h"
     19 #include "AArch64RegisterInfo.h"
     20 #include "AArch64SelectionDAGInfo.h"
     21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
     22 #include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
     23 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
     24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
     25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
     26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
     27 #include "llvm/IR/DataLayout.h"
     28 #include <string>
     29 
     30 #define GET_SUBTARGETINFO_HEADER
     31 #include "AArch64GenSubtargetInfo.inc"
     32 
     33 namespace llvm {
     34 class GlobalValue;
     35 class StringRef;
     36 class Triple;
     37 
     38 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
     39 public:
     40   enum ARMProcFamilyEnum : uint8_t {
     41     Others,
     42     A64FX,
     43     AppleA7,
     44     AppleA10,
     45     AppleA11,
     46     AppleA12,
     47     AppleA13,
     48     AppleA14,
     49     Carmel,
     50     CortexA35,
     51     CortexA53,
     52     CortexA55,
     53     CortexA57,
     54     CortexA65,
     55     CortexA72,
     56     CortexA73,
     57     CortexA75,
     58     CortexA76,
     59     CortexA77,
     60     CortexA78,
     61     CortexA78C,
     62     CortexR82,
     63     CortexX1,
     64     ExynosM3,
     65     Falkor,
     66     Kryo,
     67     NeoverseE1,
     68     NeoverseN1,
     69     NeoverseN2,
     70     NeoverseV1,
     71     Saphira,
     72     ThunderX2T99,
     73     ThunderX,
     74     ThunderXT81,
     75     ThunderXT83,
     76     ThunderXT88,
     77     ThunderX3T110,
     78     TSV110
     79   };
     80 
     81 protected:
     82   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
     83   ARMProcFamilyEnum ARMProcFamily = Others;
     84 
     85   bool HasV8_1aOps = false;
     86   bool HasV8_2aOps = false;
     87   bool HasV8_3aOps = false;
     88   bool HasV8_4aOps = false;
     89   bool HasV8_5aOps = false;
     90   bool HasV8_6aOps = false;
     91   bool HasV8_7aOps = false;
     92 
     93   bool HasV8_0rOps = false;
     94   bool HasCONTEXTIDREL2 = false;
     95 
     96   bool HasFPARMv8 = false;
     97   bool HasNEON = false;
     98   bool HasCrypto = false;
     99   bool HasDotProd = false;
    100   bool HasCRC = false;
    101   bool HasLSE = false;
    102   bool HasRAS = false;
    103   bool HasRDM = false;
    104   bool HasPerfMon = false;
    105   bool HasFullFP16 = false;
    106   bool HasFP16FML = false;
    107   bool HasSPE = false;
    108 
    109   // ARMv8.1 extensions
    110   bool HasVH = false;
    111   bool HasPAN = false;
    112   bool HasLOR = false;
    113 
    114   // ARMv8.2 extensions
    115   bool HasPsUAO = false;
    116   bool HasPAN_RWV = false;
    117   bool HasCCPP = false;
    118 
    119   // SVE extensions
    120   bool HasSVE = false;
    121   bool UseExperimentalZeroingPseudos = false;
    122 
    123   // Armv8.2 Crypto extensions
    124   bool HasSM4 = false;
    125   bool HasSHA3 = false;
    126   bool HasSHA2 = false;
    127   bool HasAES = false;
    128 
    129   // ARMv8.3 extensions
    130   bool HasPAuth = false;
    131   bool HasJS = false;
    132   bool HasCCIDX = false;
    133   bool HasComplxNum = false;
    134 
    135   // ARMv8.4 extensions
    136   bool HasNV = false;
    137   bool HasMPAM = false;
    138   bool HasDIT = false;
    139   bool HasTRACEV8_4 = false;
    140   bool HasAM = false;
    141   bool HasSEL2 = false;
    142   bool HasPMU = false;
    143   bool HasTLB_RMI = false;
    144   bool HasFlagM = false;
    145   bool HasRCPC_IMMO = false;
    146 
    147   bool HasLSLFast = false;
    148   bool HasRCPC = false;
    149   bool HasAggressiveFMA = false;
    150 
    151   // Armv8.5-A Extensions
    152   bool HasAlternativeNZCV = false;
    153   bool HasFRInt3264 = false;
    154   bool HasSpecRestrict = false;
    155   bool HasSSBS = false;
    156   bool HasSB = false;
    157   bool HasPredRes = false;
    158   bool HasCCDP = false;
    159   bool HasBTI = false;
    160   bool HasRandGen = false;
    161   bool HasMTE = false;
    162   bool HasTME = false;
    163 
    164   // Armv8.6-A Extensions
    165   bool HasBF16 = false;
    166   bool HasMatMulInt8 = false;
    167   bool HasMatMulFP32 = false;
    168   bool HasMatMulFP64 = false;
    169   bool HasAMVS = false;
    170   bool HasFineGrainedTraps = false;
    171   bool HasEnhancedCounterVirtualization = false;
    172 
    173   // Armv8.7-A Extensions
    174   bool HasXS = false;
    175   bool HasWFxT = false;
    176   bool HasHCX = false;
    177   bool HasLS64 = false;
    178 
    179   // Arm SVE2 extensions
    180   bool HasSVE2 = false;
    181   bool HasSVE2AES = false;
    182   bool HasSVE2SM4 = false;
    183   bool HasSVE2SHA3 = false;
    184   bool HasSVE2BitPerm = false;
    185 
    186   // Future architecture extensions.
    187   bool HasETE = false;
    188   bool HasTRBE = false;
    189   bool HasBRBE = false;
    190   bool HasPAUTH = false;
    191   bool HasSPE_EEF = false;
    192 
    193   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
    194   bool HasZeroCycleRegMove = false;
    195 
    196   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
    197   bool HasZeroCycleZeroing = false;
    198   bool HasZeroCycleZeroingGP = false;
    199   bool HasZeroCycleZeroingFPWorkaround = false;
    200 
    201   // It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
    202   // as movi is more efficient across all cores. Newer cores can eliminate
    203   // fmovs early and there is no difference with movi, but this not true for
    204   // all implementations.
    205   bool HasZeroCycleZeroingFP = true;
    206 
    207   // StrictAlign - Disallow unaligned memory accesses.
    208   bool StrictAlign = false;
    209 
    210   // NegativeImmediates - transform instructions with negative immediates
    211   bool NegativeImmediates = true;
    212 
    213   // Enable 64-bit vectorization in SLP.
    214   unsigned MinVectorRegisterBitWidth = 64;
    215 
    216   bool OutlineAtomics = false;
    217   bool PredictableSelectIsExpensive = false;
    218   bool BalanceFPOps = false;
    219   bool CustomAsCheapAsMove = false;
    220   bool ExynosAsCheapAsMove = false;
    221   bool UsePostRAScheduler = false;
    222   bool Misaligned128StoreIsSlow = false;
    223   bool Paired128IsSlow = false;
    224   bool STRQroIsSlow = false;
    225   bool UseAlternateSExtLoadCVTF32Pattern = false;
    226   bool HasArithmeticBccFusion = false;
    227   bool HasArithmeticCbzFusion = false;
    228   bool HasCmpBccFusion = false;
    229   bool HasFuseAddress = false;
    230   bool HasFuseAES = false;
    231   bool HasFuseArithmeticLogic = false;
    232   bool HasFuseCCSelect = false;
    233   bool HasFuseCryptoEOR = false;
    234   bool HasFuseLiterals = false;
    235   bool DisableLatencySchedHeuristic = false;
    236   bool UseRSqrt = false;
    237   bool Force32BitJumpTables = false;
    238   bool UseEL1ForTP = false;
    239   bool UseEL2ForTP = false;
    240   bool UseEL3ForTP = false;
    241   bool AllowTaggedGlobals = false;
    242   bool HardenSlsRetBr = false;
    243   bool HardenSlsBlr = false;
    244   bool HardenSlsNoComdat = false;
    245   uint8_t MaxInterleaveFactor = 2;
    246   uint8_t VectorInsertExtractBaseCost = 3;
    247   uint16_t CacheLineSize = 0;
    248   uint16_t PrefetchDistance = 0;
    249   uint16_t MinPrefetchStride = 1;
    250   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
    251   unsigned PrefFunctionLogAlignment = 0;
    252   unsigned PrefLoopLogAlignment = 0;
    253   unsigned MaxJumpTableSize = 0;
    254   unsigned WideningBaseCost = 0;
    255 
    256   // ReserveXRegister[i] - X#i is not available as a general purpose register.
    257   BitVector ReserveXRegister;
    258 
    259   // CustomCallUsedXRegister[i] - X#i call saved.
    260   BitVector CustomCallSavedXRegs;
    261 
    262   bool IsLittle;
    263 
    264   /// TargetTriple - What processor and OS we're targeting.
    265   Triple TargetTriple;
    266 
    267   AArch64FrameLowering FrameLowering;
    268   AArch64InstrInfo InstrInfo;
    269   AArch64SelectionDAGInfo TSInfo;
    270   AArch64TargetLowering TLInfo;
    271 
    272   /// GlobalISel related APIs.
    273   std::unique_ptr<CallLowering> CallLoweringInfo;
    274   std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
    275   std::unique_ptr<InstructionSelector> InstSelector;
    276   std::unique_ptr<LegalizerInfo> Legalizer;
    277   std::unique_ptr<RegisterBankInfo> RegBankInfo;
    278 
    279 private:
    280   /// initializeSubtargetDependencies - Initializes using CPUString and the
    281   /// passed in feature string so that we can use initializer lists for
    282   /// subtarget initialization.
    283   AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
    284                                                     StringRef CPUString);
    285 
    286   /// Initialize properties based on the selected processor family.
    287   void initializeProperties();
    288 
    289 public:
    290   /// This constructor initializes the data members to match that
    291   /// of the specified triple.
    292   AArch64Subtarget(const Triple &TT, const std::string &CPU,
    293                    const std::string &FS, const TargetMachine &TM,
    294                    bool LittleEndian);
    295 
    296   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
    297     return &TSInfo;
    298   }
    299   const AArch64FrameLowering *getFrameLowering() const override {
    300     return &FrameLowering;
    301   }
    302   const AArch64TargetLowering *getTargetLowering() const override {
    303     return &TLInfo;
    304   }
    305   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
    306   const AArch64RegisterInfo *getRegisterInfo() const override {
    307     return &getInstrInfo()->getRegisterInfo();
    308   }
    309   const CallLowering *getCallLowering() const override;
    310   const InlineAsmLowering *getInlineAsmLowering() const override;
    311   InstructionSelector *getInstructionSelector() const override;
    312   const LegalizerInfo *getLegalizerInfo() const override;
    313   const RegisterBankInfo *getRegBankInfo() const override;
    314   const Triple &getTargetTriple() const { return TargetTriple; }
    315   bool enableMachineScheduler() const override { return true; }
    316   bool enablePostRAScheduler() const override {
    317     return UsePostRAScheduler;
    318   }
    319 
    320   /// Returns ARM processor family.
    321   /// Avoid this function! CPU specifics should be kept local to this class
    322   /// and preferably modeled with SubtargetFeatures or properties in
    323   /// initializeProperties().
    324   ARMProcFamilyEnum getProcFamily() const {
    325     return ARMProcFamily;
    326   }
    327 
    328   bool hasV8_1aOps() const { return HasV8_1aOps; }
    329   bool hasV8_2aOps() const { return HasV8_2aOps; }
    330   bool hasV8_3aOps() const { return HasV8_3aOps; }
    331   bool hasV8_4aOps() const { return HasV8_4aOps; }
    332   bool hasV8_5aOps() const { return HasV8_5aOps; }
    333   bool hasV8_0rOps() const { return HasV8_0rOps; }
    334 
    335   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
    336 
    337   bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
    338 
    339   bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
    340 
    341   bool hasZeroCycleZeroingFPWorkaround() const {
    342     return HasZeroCycleZeroingFPWorkaround;
    343   }
    344 
    345   bool requiresStrictAlign() const { return StrictAlign; }
    346 
    347   bool isXRaySupported() const override { return true; }
    348 
    349   unsigned getMinVectorRegisterBitWidth() const {
    350     return MinVectorRegisterBitWidth;
    351   }
    352 
    353   bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
    354   unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
    355   bool isXRegCustomCalleeSaved(size_t i) const {
    356     return CustomCallSavedXRegs[i];
    357   }
    358   bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
    359   bool hasFPARMv8() const { return HasFPARMv8; }
    360   bool hasNEON() const { return HasNEON; }
    361   bool hasCrypto() const { return HasCrypto; }
    362   bool hasDotProd() const { return HasDotProd; }
    363   bool hasCRC() const { return HasCRC; }
    364   bool hasLSE() const { return HasLSE; }
    365   bool hasRAS() const { return HasRAS; }
    366   bool hasRDM() const { return HasRDM; }
    367   bool hasSM4() const { return HasSM4; }
    368   bool hasSHA3() const { return HasSHA3; }
    369   bool hasSHA2() const { return HasSHA2; }
    370   bool hasAES() const { return HasAES; }
    371   bool hasCONTEXTIDREL2() const { return HasCONTEXTIDREL2; }
    372   bool balanceFPOps() const { return BalanceFPOps; }
    373   bool predictableSelectIsExpensive() const {
    374     return PredictableSelectIsExpensive;
    375   }
    376   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
    377   bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
    378   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
    379   bool isPaired128Slow() const { return Paired128IsSlow; }
    380   bool isSTRQroSlow() const { return STRQroIsSlow; }
    381   bool useAlternateSExtLoadCVTF32Pattern() const {
    382     return UseAlternateSExtLoadCVTF32Pattern;
    383   }
    384   bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
    385   bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
    386   bool hasCmpBccFusion() const { return HasCmpBccFusion; }
    387   bool hasFuseAddress() const { return HasFuseAddress; }
    388   bool hasFuseAES() const { return HasFuseAES; }
    389   bool hasFuseArithmeticLogic() const { return HasFuseArithmeticLogic; }
    390   bool hasFuseCCSelect() const { return HasFuseCCSelect; }
    391   bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
    392   bool hasFuseLiterals() const { return HasFuseLiterals; }
    393 
    394   /// Return true if the CPU supports any kind of instruction fusion.
    395   bool hasFusion() const {
    396     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
    397            hasFuseAES() || hasFuseArithmeticLogic() ||
    398            hasFuseCCSelect() || hasFuseLiterals();
    399   }
    400 
    401   bool hardenSlsRetBr() const { return HardenSlsRetBr; }
    402   bool hardenSlsBlr() const { return HardenSlsBlr; }
    403   bool hardenSlsNoComdat() const { return HardenSlsNoComdat; }
    404 
    405   bool useEL1ForTP() const { return UseEL1ForTP; }
    406   bool useEL2ForTP() const { return UseEL2ForTP; }
    407   bool useEL3ForTP() const { return UseEL3ForTP; }
    408 
    409   bool useRSqrt() const { return UseRSqrt; }
    410   bool force32BitJumpTables() const { return Force32BitJumpTables; }
    411   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
    412   unsigned getVectorInsertExtractBaseCost() const {
    413     return VectorInsertExtractBaseCost;
    414   }
    415   unsigned getCacheLineSize() const override { return CacheLineSize; }
    416   unsigned getPrefetchDistance() const override { return PrefetchDistance; }
    417   unsigned getMinPrefetchStride(unsigned NumMemAccesses,
    418                                 unsigned NumStridedMemAccesses,
    419                                 unsigned NumPrefetches,
    420                                 bool HasCall) const override {
    421     return MinPrefetchStride;
    422   }
    423   unsigned getMaxPrefetchIterationsAhead() const override {
    424     return MaxPrefetchIterationsAhead;
    425   }
    426   unsigned getPrefFunctionLogAlignment() const {
    427     return PrefFunctionLogAlignment;
    428   }
    429   unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
    430 
    431   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
    432 
    433   unsigned getWideningBaseCost() const { return WideningBaseCost; }
    434 
    435   bool useExperimentalZeroingPseudos() const {
    436     return UseExperimentalZeroingPseudos;
    437   }
    438 
    439   /// CPU has TBI (top byte of addresses is ignored during HW address
    440   /// translation) and OS enables it.
    441   bool supportsAddressTopByteIgnored() const;
    442 
    443   bool hasPerfMon() const { return HasPerfMon; }
    444   bool hasFullFP16() const { return HasFullFP16; }
    445   bool hasFP16FML() const { return HasFP16FML; }
    446   bool hasSPE() const { return HasSPE; }
    447   bool hasLSLFast() const { return HasLSLFast; }
    448   bool hasSVE() const { return HasSVE; }
    449   bool hasSVE2() const { return HasSVE2; }
    450   bool hasRCPC() const { return HasRCPC; }
    451   bool hasAggressiveFMA() const { return HasAggressiveFMA; }
    452   bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
    453   bool hasFRInt3264() const { return HasFRInt3264; }
    454   bool hasSpecRestrict() const { return HasSpecRestrict; }
    455   bool hasSSBS() const { return HasSSBS; }
    456   bool hasSB() const { return HasSB; }
    457   bool hasPredRes() const { return HasPredRes; }
    458   bool hasCCDP() const { return HasCCDP; }
    459   bool hasBTI() const { return HasBTI; }
    460   bool hasRandGen() const { return HasRandGen; }
    461   bool hasMTE() const { return HasMTE; }
    462   bool hasTME() const { return HasTME; }
    463   bool hasPAUTH() const { return HasPAUTH; }
    464   // Arm SVE2 extensions
    465   bool hasSVE2AES() const { return HasSVE2AES; }
    466   bool hasSVE2SM4() const { return HasSVE2SM4; }
    467   bool hasSVE2SHA3() const { return HasSVE2SHA3; }
    468   bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
    469   bool hasMatMulInt8() const { return HasMatMulInt8; }
    470   bool hasMatMulFP32() const { return HasMatMulFP32; }
    471   bool hasMatMulFP64() const { return HasMatMulFP64; }
    472 
    473   // Armv8.6-A Extensions
    474   bool hasBF16() const { return HasBF16; }
    475   bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
    476   bool hasEnhancedCounterVirtualization() const {
    477     return HasEnhancedCounterVirtualization;
    478   }
    479 
    480   bool isLittleEndian() const { return IsLittle; }
    481 
    482   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
    483   bool isTargetIOS() const { return TargetTriple.isiOS(); }
    484   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
    485   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
    486   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
    487   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
    488 
    489   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
    490   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
    491   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
    492 
    493   bool isTargetILP32() const {
    494     return TargetTriple.isArch32Bit() ||
    495            TargetTriple.getEnvironment() == Triple::GNUILP32;
    496   }
    497 
    498   bool useAA() const override;
    499 
    500   bool outlineAtomics() const { return OutlineAtomics; }
    501 
    502   bool hasVH() const { return HasVH; }
    503   bool hasPAN() const { return HasPAN; }
    504   bool hasLOR() const { return HasLOR; }
    505 
    506   bool hasPsUAO() const { return HasPsUAO; }
    507   bool hasPAN_RWV() const { return HasPAN_RWV; }
    508   bool hasCCPP() const { return HasCCPP; }
    509 
    510   bool hasPAuth() const { return HasPAuth; }
    511   bool hasJS() const { return HasJS; }
    512   bool hasCCIDX() const { return HasCCIDX; }
    513   bool hasComplxNum() const { return HasComplxNum; }
    514 
    515   bool hasNV() const { return HasNV; }
    516   bool hasMPAM() const { return HasMPAM; }
    517   bool hasDIT() const { return HasDIT; }
    518   bool hasTRACEV8_4() const { return HasTRACEV8_4; }
    519   bool hasAM() const { return HasAM; }
    520   bool hasAMVS() const { return HasAMVS; }
    521   bool hasXS() const { return HasXS; }
    522   bool hasWFxT() const { return HasWFxT; }
    523   bool hasHCX() const { return HasHCX; }
    524   bool hasLS64() const { return HasLS64; }
    525   bool hasSEL2() const { return HasSEL2; }
    526   bool hasPMU() const { return HasPMU; }
    527   bool hasTLB_RMI() const { return HasTLB_RMI; }
    528   bool hasFlagM() const { return HasFlagM; }
    529   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
    530 
    531   bool addrSinkUsingGEPs() const override {
    532     // Keeping GEPs inbounds is important for exploiting AArch64
    533     // addressing-modes in ILP32 mode.
    534     return useAA() || isTargetILP32();
    535   }
    536 
    537   bool useSmallAddressing() const {
    538     switch (TLInfo.getTargetMachine().getCodeModel()) {
    539       case CodeModel::Kernel:
    540         // Kernel is currently allowed only for Fuchsia targets,
    541         // where it is the same as Small for almost all purposes.
    542       case CodeModel::Small:
    543         return true;
    544       default:
    545         return false;
    546     }
    547   }
    548 
    549   /// ParseSubtargetFeatures - Parses features string setting specified
    550   /// subtarget options.  Definition of function is auto generated by tblgen.
    551   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
    552 
    553   /// ClassifyGlobalReference - Find the target operand flags that describe
    554   /// how a global value should be referenced for the current subtarget.
    555   unsigned ClassifyGlobalReference(const GlobalValue *GV,
    556                                    const TargetMachine &TM) const;
    557 
    558   unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
    559                                            const TargetMachine &TM) const;
    560 
    561   void overrideSchedPolicy(MachineSchedPolicy &Policy,
    562                            unsigned NumRegionInstrs) const override;
    563 
    564   bool enableEarlyIfConversion() const override;
    565 
    566   bool enableAdvancedRASplitCost() const override { return false; }
    567 
    568   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
    569 
    570   bool isCallingConvWin64(CallingConv::ID CC) const {
    571     switch (CC) {
    572     case CallingConv::C:
    573     case CallingConv::Fast:
    574     case CallingConv::Swift:
    575       return isTargetWindows();
    576     case CallingConv::Win64:
    577       return true;
    578     default:
    579       return false;
    580     }
    581   }
    582 
    583   void mirFileLoaded(MachineFunction &MF) const override;
    584 
    585   // Return the known range for the bit length of SVE data registers. A value
    586   // of 0 means nothing is known about that particular limit beyong what's
    587   // implied by the architecture.
    588   unsigned getMaxSVEVectorSizeInBits() const;
    589   unsigned getMinSVEVectorSizeInBits() const;
    590   bool useSVEForFixedLengthVectors() const;
    591 };
    592 } // End llvm namespace
    593 
    594 #endif
    595