1 /* $NetBSD: mmio_context.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */ 2 3 /* 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Eddie Dong <eddie.dong (at) intel.com> 27 * Kevin Tian <kevin.tian (at) intel.com> 28 * 29 * Contributors: 30 * Zhi Wang <zhi.a.wang (at) intel.com> 31 * Changbin Du <changbin.du (at) intel.com> 32 * Zhenyu Wang <zhenyuw (at) linux.intel.com> 33 * Tina Zhang <tina.zhang (at) intel.com> 34 * Bing Niu <bing.niu (at) intel.com> 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: mmio_context.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $"); 40 41 #include "i915_drv.h" 42 #include "gt/intel_context.h" 43 #include "gt/intel_ring.h" 44 #include "gvt.h" 45 #include "trace.h" 46 47 #define GEN9_MOCS_SIZE 64 48 49 /* Raw offset is appened to each line for convenience. */ 50 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { 51 {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 52 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 53 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 54 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 60 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 61 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 62 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 63 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 64 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 65 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 66 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 67 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 68 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 69 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 70 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 71 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 72 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 73 74 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 75 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 76 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 77 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 78 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 79 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 80 }; 81 82 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 83 {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 84 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 85 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 86 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 87 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 88 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 89 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 90 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 91 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 92 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 93 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 94 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 95 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 96 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 97 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 98 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 99 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 100 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 101 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 102 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 103 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 104 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 105 106 {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ 107 {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ 108 {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ 109 {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ 110 {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ 111 {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */ 112 {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ 113 {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ 114 {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ 115 {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */ 116 {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */ 117 {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */ 118 {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */ 119 {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */ 120 {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */ 121 {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */ 122 {RCS0, TRVADR, 0, true}, /* 0x4df0 */ 123 {RCS0, TRTTE, 0, true}, /* 0x4df4 */ 124 {RCS0, _MMIO(0x4dfc), 0, true}, 125 126 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 127 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 128 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 129 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 130 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 131 132 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */ 133 134 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */ 135 136 {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ 137 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 138 {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ 139 {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ 140 141 {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ 142 {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */ 143 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */ 144 145 {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ 146 {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ 147 {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ 148 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 149 }; 150 151 static struct { 152 bool initialized; 153 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE]; 154 u32 l3cc_table[GEN9_MOCS_SIZE / 2]; 155 } gen9_render_mocs; 156 157 static u32 gen9_mocs_mmio_offset_list[] = { 158 [RCS0] = 0xc800, 159 [VCS0] = 0xc900, 160 [VCS1] = 0xca00, 161 [BCS0] = 0xcc00, 162 [VECS0] = 0xcb00, 163 }; 164 165 static void load_render_mocs(struct drm_i915_private *dev_priv) 166 { 167 struct intel_gvt *gvt = dev_priv->gvt; 168 i915_reg_t offset; 169 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; 170 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; 171 int ring_id, i; 172 173 /* Platform doesn't have mocs mmios. */ 174 if (!regs) 175 return; 176 177 for (ring_id = 0; ring_id < cnt; ring_id++) { 178 if (!HAS_ENGINE(dev_priv, ring_id)) 179 continue; 180 offset.reg = regs[ring_id]; 181 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 182 gen9_render_mocs.control_table[ring_id][i] = 183 I915_READ_FW(offset); 184 offset.reg += 4; 185 } 186 } 187 188 offset.reg = 0xb020; 189 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 190 gen9_render_mocs.l3cc_table[i] = 191 I915_READ_FW(offset); 192 offset.reg += 4; 193 } 194 gen9_render_mocs.initialized = true; 195 } 196 197 static int 198 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu, 199 struct i915_request *req) 200 { 201 u32 *cs; 202 int ret; 203 struct engine_mmio *mmio; 204 struct intel_gvt *gvt = vgpu->gvt; 205 int ring_id = req->engine->id; 206 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; 207 208 if (count == 0) 209 return 0; 210 211 ret = req->engine->emit_flush(req, EMIT_BARRIER); 212 if (ret) 213 return ret; 214 215 cs = intel_ring_begin(req, count * 2 + 2); 216 if (IS_ERR(cs)) 217 return PTR_ERR(cs); 218 219 *cs++ = MI_LOAD_REGISTER_IMM(count); 220 for (mmio = gvt->engine_mmio_list.mmio; 221 i915_mmio_reg_valid(mmio->reg); mmio++) { 222 if (mmio->ring_id != ring_id || 223 !mmio->in_context) 224 continue; 225 226 *cs++ = i915_mmio_reg_offset(mmio->reg); 227 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | 228 (mmio->mask << 16); 229 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 230 *(cs-2), *(cs-1), vgpu->id, ring_id); 231 } 232 233 *cs++ = MI_NOOP; 234 intel_ring_advance(req, cs); 235 236 ret = req->engine->emit_flush(req, EMIT_BARRIER); 237 if (ret) 238 return ret; 239 240 return 0; 241 } 242 243 static int 244 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu, 245 struct i915_request *req) 246 { 247 unsigned int index; 248 u32 *cs; 249 250 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2); 251 if (IS_ERR(cs)) 252 return PTR_ERR(cs); 253 254 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); 255 256 for (index = 0; index < GEN9_MOCS_SIZE; index++) { 257 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); 258 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); 259 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 260 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 261 262 } 263 264 *cs++ = MI_NOOP; 265 intel_ring_advance(req, cs); 266 267 return 0; 268 } 269 270 static int 271 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu, 272 struct i915_request *req) 273 { 274 unsigned int index; 275 u32 *cs; 276 277 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2); 278 if (IS_ERR(cs)) 279 return PTR_ERR(cs); 280 281 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); 282 283 for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) { 284 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); 285 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); 286 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 287 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 288 289 } 290 291 *cs++ = MI_NOOP; 292 intel_ring_advance(req, cs); 293 294 return 0; 295 } 296 297 /* 298 * Use lri command to initialize the mmio which is in context state image for 299 * inhibit context, it contains tracked engine mmio, render_mocs and 300 * render_mocs_l3cc. 301 */ 302 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 303 struct i915_request *req) 304 { 305 int ret; 306 u32 *cs; 307 308 cs = intel_ring_begin(req, 2); 309 if (IS_ERR(cs)) 310 return PTR_ERR(cs); 311 312 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 313 *cs++ = MI_NOOP; 314 intel_ring_advance(req, cs); 315 316 ret = restore_context_mmio_for_inhibit(vgpu, req); 317 if (ret) 318 goto out; 319 320 /* no MOCS register in context except render engine */ 321 if (req->engine->id != RCS0) 322 goto out; 323 324 ret = restore_render_mocs_control_for_inhibit(vgpu, req); 325 if (ret) 326 goto out; 327 328 ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req); 329 if (ret) 330 goto out; 331 332 out: 333 cs = intel_ring_begin(req, 2); 334 if (IS_ERR(cs)) 335 return PTR_ERR(cs); 336 337 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 338 *cs++ = MI_NOOP; 339 intel_ring_advance(req, cs); 340 341 return ret; 342 } 343 344 static u32 gen8_tlb_mmio_offset_list[] = { 345 [RCS0] = 0x4260, 346 [VCS0] = 0x4264, 347 [VCS1] = 0x4268, 348 [BCS0] = 0x426c, 349 [VECS0] = 0x4270, 350 }; 351 352 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 353 { 354 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 355 struct intel_uncore *uncore = &dev_priv->uncore; 356 struct intel_vgpu_submission *s = &vgpu->submission; 357 u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list; 358 u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt; 359 enum forcewake_domains fw; 360 i915_reg_t reg; 361 362 if (!regs) 363 return; 364 365 if (WARN_ON(ring_id >= cnt)) 366 return; 367 368 if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending)) 369 return; 370 371 reg = _MMIO(regs[ring_id]); 372 373 /* WaForceWakeRenderDuringMmioTLBInvalidate:skl 374 * we need to put a forcewake when invalidating RCS TLB caches, 375 * otherwise device can go to RC6 state and interrupt invalidation 376 * process 377 */ 378 fw = intel_uncore_forcewake_for_reg(uncore, reg, 379 FW_REG_READ | FW_REG_WRITE); 380 if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9) 381 fw |= FORCEWAKE_RENDER; 382 383 intel_uncore_forcewake_get(uncore, fw); 384 385 intel_uncore_write_fw(uncore, reg, 0x1); 386 387 if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50)) 388 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id); 389 else 390 vgpu_vreg_t(vgpu, reg) = 0; 391 392 intel_uncore_forcewake_put(uncore, fw); 393 394 gvt_dbg_core("invalidate TLB for ring %d\n", ring_id); 395 } 396 397 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 398 int ring_id) 399 { 400 struct drm_i915_private *dev_priv; 401 i915_reg_t offset, l3_offset; 402 u32 old_v, new_v; 403 404 u32 regs[] = { 405 [RCS0] = 0xc800, 406 [VCS0] = 0xc900, 407 [VCS1] = 0xca00, 408 [BCS0] = 0xcc00, 409 [VECS0] = 0xcb00, 410 }; 411 int i; 412 413 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 414 if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) 415 return; 416 417 if (ring_id == RCS0 && IS_GEN(dev_priv, 9)) 418 return; 419 420 if (!pre && !gen9_render_mocs.initialized) 421 load_render_mocs(dev_priv); 422 423 offset.reg = regs[ring_id]; 424 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 425 if (pre) 426 old_v = vgpu_vreg_t(pre, offset); 427 else 428 old_v = gen9_render_mocs.control_table[ring_id][i]; 429 if (next) 430 new_v = vgpu_vreg_t(next, offset); 431 else 432 new_v = gen9_render_mocs.control_table[ring_id][i]; 433 434 if (old_v != new_v) 435 I915_WRITE_FW(offset, new_v); 436 437 offset.reg += 4; 438 } 439 440 if (ring_id == RCS0) { 441 l3_offset.reg = 0xb020; 442 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 443 if (pre) 444 old_v = vgpu_vreg_t(pre, l3_offset); 445 else 446 old_v = gen9_render_mocs.l3cc_table[i]; 447 if (next) 448 new_v = vgpu_vreg_t(next, l3_offset); 449 else 450 new_v = gen9_render_mocs.l3cc_table[i]; 451 452 if (old_v != new_v) 453 I915_WRITE_FW(l3_offset, new_v); 454 455 l3_offset.reg += 4; 456 } 457 } 458 } 459 460 #define CTX_CONTEXT_CONTROL_VAL 0x03 461 462 bool is_inhibit_context(struct intel_context *ce) 463 { 464 const u32 *reg_state = ce->lrc_reg_state; 465 u32 inhibit_mask = 466 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 467 468 return inhibit_mask == 469 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); 470 } 471 472 /* Switch ring mmio values (context). */ 473 static void switch_mmio(struct intel_vgpu *pre, 474 struct intel_vgpu *next, 475 int ring_id) 476 { 477 struct drm_i915_private *dev_priv; 478 struct intel_vgpu_submission *s; 479 struct engine_mmio *mmio; 480 u32 old_v, new_v; 481 482 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 483 if (INTEL_GEN(dev_priv) >= 9) 484 switch_mocs(pre, next, ring_id); 485 486 for (mmio = dev_priv->gvt->engine_mmio_list.mmio; 487 i915_mmio_reg_valid(mmio->reg); mmio++) { 488 if (mmio->ring_id != ring_id) 489 continue; 490 /* 491 * No need to do save or restore of the mmio which is in context 492 * state image on gen9, it's initialized by lri command and 493 * save or restore with context together. 494 */ 495 if (IS_GEN(dev_priv, 9) && mmio->in_context) 496 continue; 497 498 // save 499 if (pre) { 500 vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); 501 if (mmio->mask) 502 vgpu_vreg_t(pre, mmio->reg) &= 503 ~(mmio->mask << 16); 504 old_v = vgpu_vreg_t(pre, mmio->reg); 505 } else 506 old_v = mmio->value = I915_READ_FW(mmio->reg); 507 508 // restore 509 if (next) { 510 s = &next->submission; 511 /* 512 * No need to restore the mmio which is in context state 513 * image if it's not inhibit context, it will restore 514 * itself. 515 */ 516 if (mmio->in_context && 517 !is_inhibit_context(s->shadow[ring_id])) 518 continue; 519 520 if (mmio->mask) 521 new_v = vgpu_vreg_t(next, mmio->reg) | 522 (mmio->mask << 16); 523 else 524 new_v = vgpu_vreg_t(next, mmio->reg); 525 } else { 526 if (mmio->in_context) 527 continue; 528 if (mmio->mask) 529 new_v = mmio->value | (mmio->mask << 16); 530 else 531 new_v = mmio->value; 532 } 533 534 I915_WRITE_FW(mmio->reg, new_v); 535 536 trace_render_mmio(pre ? pre->id : 0, 537 next ? next->id : 0, 538 "switch", 539 i915_mmio_reg_offset(mmio->reg), 540 old_v, new_v); 541 } 542 543 if (next) 544 handle_tlb_pending_event(next, ring_id); 545 } 546 547 /** 548 * intel_gvt_switch_render_mmio - switch mmio context of specific engine 549 * @pre: the last vGPU that own the engine 550 * @next: the vGPU to switch to 551 * @ring_id: specify the engine 552 * 553 * If pre is null indicates that host own the engine. If next is null 554 * indicates that we are switching to host workload. 555 */ 556 void intel_gvt_switch_mmio(struct intel_vgpu *pre, 557 struct intel_vgpu *next, int ring_id) 558 { 559 struct drm_i915_private *dev_priv; 560 561 if (WARN_ON(!pre && !next)) 562 return; 563 564 gvt_dbg_render("switch ring %d from %s to %s\n", ring_id, 565 pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); 566 567 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 568 569 /** 570 * We are using raw mmio access wrapper to improve the 571 * performace for batch mmio read/write, so we need 572 * handle forcewake mannually. 573 */ 574 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 575 switch_mmio(pre, next, ring_id); 576 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 577 } 578 579 /** 580 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list 581 * @gvt: GVT device 582 * 583 */ 584 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) 585 { 586 struct engine_mmio *mmio; 587 588 if (INTEL_GEN(gvt->dev_priv) >= 9) { 589 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list; 590 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 591 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 592 gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list; 593 gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list); 594 } else { 595 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list; 596 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 597 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 598 } 599 600 for (mmio = gvt->engine_mmio_list.mmio; 601 i915_mmio_reg_valid(mmio->reg); mmio++) { 602 if (mmio->in_context) { 603 gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++; 604 intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg); 605 } 606 } 607 } 608
Indexes created Sat Sep 20 22:09:52 GMT 2025