1 /* $NetBSD: dvo_ivch.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2006 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric (at) anholt.net> 27 * Thomas Richter <thor (at) math.tu-berlin.de> 28 * 29 * Minor modifications (Dithering enable): 30 * Thomas Richter <thor (at) math.tu-berlin.de> 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: dvo_ivch.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $"); 36 37 #include "intel_display_types.h" 38 #include "intel_dvo_dev.h" 39 40 /* 41 * register definitions for the i82807aa. 42 * 43 * Documentation on this chipset can be found in datasheet #29069001 at 44 * intel.com. 45 */ 46 47 /* 48 * VCH Revision & GMBus Base Addr 49 */ 50 #define VR00 0x00 51 # define VR00_BASE_ADDRESS_MASK 0x007f 52 53 /* 54 * Functionality Enable 55 */ 56 #define VR01 0x01 57 58 /* 59 * Enable the panel fitter 60 */ 61 # define VR01_PANEL_FIT_ENABLE (1 << 3) 62 /* 63 * Enables the LCD display. 64 * 65 * This must not be set while VR01_DVO_BYPASS_ENABLE is set. 66 */ 67 # define VR01_LCD_ENABLE (1 << 2) 68 /* Enables the DVO repeater. */ 69 # define VR01_DVO_BYPASS_ENABLE (1 << 1) 70 /* Enables the DVO clock */ 71 # define VR01_DVO_ENABLE (1 << 0) 72 /* Enable dithering for 18bpp panels. Not documented. */ 73 # define VR01_DITHER_ENABLE (1 << 4) 74 75 /* 76 * LCD Interface Format 77 */ 78 #define VR10 0x10 79 /* Enables LVDS output instead of CMOS */ 80 # define VR10_LVDS_ENABLE (1 << 4) 81 /* Enables 18-bit LVDS output. */ 82 # define VR10_INTERFACE_1X18 (0 << 2) 83 /* Enables 24-bit LVDS or CMOS output */ 84 # define VR10_INTERFACE_1X24 (1 << 2) 85 /* Enables 2x18-bit LVDS or CMOS output. */ 86 # define VR10_INTERFACE_2X18 (2 << 2) 87 /* Enables 2x24-bit LVDS output */ 88 # define VR10_INTERFACE_2X24 (3 << 2) 89 /* Mask that defines the depth of the pipeline */ 90 # define VR10_INTERFACE_DEPTH_MASK (3 << 2) 91 92 /* 93 * VR20 LCD Horizontal Display Size 94 */ 95 #define VR20 0x20 96 97 /* 98 * LCD Vertical Display Size 99 */ 100 #define VR21 0x21 101 102 /* 103 * Panel power down status 104 */ 105 #define VR30 0x30 106 /* Read only bit indicating that the panel is not in a safe poweroff state. */ 107 # define VR30_PANEL_ON (1 << 15) 108 109 #define VR40 0x40 110 # define VR40_STALL_ENABLE (1 << 13) 111 # define VR40_VERTICAL_INTERP_ENABLE (1 << 12) 112 # define VR40_ENHANCED_PANEL_FITTING (1 << 11) 113 # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10) 114 # define VR40_AUTO_RATIO_ENABLE (1 << 9) 115 # define VR40_CLOCK_GATING_ENABLE (1 << 8) 116 117 /* 118 * Panel Fitting Vertical Ratio 119 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 120 */ 121 #define VR41 0x41 122 123 /* 124 * Panel Fitting Horizontal Ratio 125 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 126 */ 127 #define VR42 0x42 128 129 /* 130 * Horizontal Image Size 131 */ 132 #define VR43 0x43 133 134 /* VR80 GPIO 0 135 */ 136 #define VR80 0x80 137 #define VR81 0x81 138 #define VR82 0x82 139 #define VR83 0x83 140 #define VR84 0x84 141 #define VR85 0x85 142 #define VR86 0x86 143 #define VR87 0x87 144 145 /* VR88 GPIO 8 146 */ 147 #define VR88 0x88 148 149 /* Graphics BIOS scratch 0 150 */ 151 #define VR8E 0x8E 152 # define VR8E_PANEL_TYPE_MASK (0xf << 0) 153 # define VR8E_PANEL_INTERFACE_CMOS (0 << 4) 154 # define VR8E_PANEL_INTERFACE_LVDS (1 << 4) 155 # define VR8E_FORCE_DEFAULT_PANEL (1 << 5) 156 157 /* Graphics BIOS scratch 1 158 */ 159 #define VR8F 0x8F 160 # define VR8F_VCH_PRESENT (1 << 0) 161 # define VR8F_DISPLAY_CONN (1 << 1) 162 # define VR8F_POWER_MASK (0x3c) 163 # define VR8F_POWER_POS (2) 164 165 /* Some Bios implementations do not restore the DVO state upon 166 * resume from standby. Thus, this driver has to handle it 167 * instead. The following list contains all registers that 168 * require saving. 169 */ 170 static const u16 backup_addresses[] = { 171 0x11, 0x12, 172 0x18, 0x19, 0x1a, 0x1f, 173 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 174 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 175 0x8e, 0x8f, 176 0x10 /* this must come last */ 177 }; 178 179 180 struct ivch_priv { 181 bool quiet; 182 183 u16 width, height; 184 185 /* Register backup */ 186 187 u16 reg_backup[ARRAY_SIZE(backup_addresses)]; 188 }; 189 190 191 static void ivch_dump_regs(struct intel_dvo_device *dvo); 192 /* 193 * Reads a register on the ivch. 194 * 195 * Each of the 256 registers are 16 bits long. 196 */ 197 static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data) 198 { 199 struct ivch_priv *priv = dvo->dev_priv; 200 struct i2c_adapter *adapter = dvo->i2c_bus; 201 u8 out_buf[1]; 202 u8 in_buf[2]; 203 204 struct i2c_msg msgs[] = { 205 { 206 .addr = dvo->slave_addr, 207 .flags = I2C_M_RD, 208 .len = 0, 209 }, 210 { 211 .addr = 0, 212 .flags = I2C_M_NOSTART, 213 .len = 1, 214 .buf = out_buf, 215 }, 216 { 217 .addr = dvo->slave_addr, 218 .flags = I2C_M_RD | I2C_M_NOSTART, 219 .len = 2, 220 .buf = in_buf, 221 } 222 }; 223 224 out_buf[0] = addr; 225 226 if (i2c_transfer(adapter, msgs, 3) == 3) { 227 *data = (in_buf[1] << 8) | in_buf[0]; 228 return true; 229 } 230 231 if (!priv->quiet) { 232 DRM_DEBUG_KMS("Unable to read register 0x%02x from " 233 "%s:%02x.\n", 234 addr, adapter->name, dvo->slave_addr); 235 } 236 return false; 237 } 238 239 /* Writes a 16-bit register on the ivch */ 240 static bool ivch_write(struct intel_dvo_device *dvo, int addr, u16 data) 241 { 242 struct ivch_priv *priv = dvo->dev_priv; 243 struct i2c_adapter *adapter = dvo->i2c_bus; 244 u8 out_buf[3]; 245 struct i2c_msg msg = { 246 .addr = dvo->slave_addr, 247 .flags = 0, 248 .len = 3, 249 .buf = out_buf, 250 }; 251 252 out_buf[0] = addr; 253 out_buf[1] = data & 0xff; 254 out_buf[2] = data >> 8; 255 256 if (i2c_transfer(adapter, &msg, 1) == 1) 257 return true; 258 259 if (!priv->quiet) { 260 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 261 addr, adapter->name, dvo->slave_addr); 262 } 263 264 return false; 265 } 266 267 /* Probes the given bus and slave address for an ivch */ 268 static bool ivch_init(struct intel_dvo_device *dvo, 269 struct i2c_adapter *adapter) 270 { 271 struct ivch_priv *priv; 272 u16 temp; 273 int i; 274 275 priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL); 276 if (priv == NULL) 277 return false; 278 279 dvo->i2c_bus = adapter; 280 dvo->dev_priv = priv; 281 priv->quiet = true; 282 283 if (!ivch_read(dvo, VR00, &temp)) 284 goto out; 285 priv->quiet = false; 286 287 /* Since the identification bits are probably zeroes, which doesn't seem 288 * very unique, check that the value in the base address field matches 289 * the address it's responding on. 290 */ 291 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { 292 DRM_DEBUG_KMS("ivch detect failed due to address mismatch " 293 "(%d vs %d)\n", 294 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); 295 goto out; 296 } 297 298 ivch_read(dvo, VR20, &priv->width); 299 ivch_read(dvo, VR21, &priv->height); 300 301 /* Make a backup of the registers to be able to restore them 302 * upon suspend. 303 */ 304 for (i = 0; i < ARRAY_SIZE(backup_addresses); i++) 305 ivch_read(dvo, backup_addresses[i], priv->reg_backup + i); 306 307 ivch_dump_regs(dvo); 308 309 return true; 310 311 out: 312 kfree(priv); 313 return false; 314 } 315 316 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) 317 { 318 return connector_status_connected; 319 } 320 321 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, 322 struct drm_display_mode *mode) 323 { 324 if (mode->clock > 112000) 325 return MODE_CLOCK_HIGH; 326 327 return MODE_OK; 328 } 329 330 /* Restore the DVO registers after a resume 331 * from RAM. Registers have been saved during 332 * the initialization. 333 */ 334 static void ivch_reset(struct intel_dvo_device *dvo) 335 { 336 struct ivch_priv *priv = dvo->dev_priv; 337 int i; 338 339 DRM_DEBUG_KMS("Resetting the IVCH registers\n"); 340 341 ivch_write(dvo, VR10, 0x0000); 342 343 for (i = 0; i < ARRAY_SIZE(backup_addresses); i++) 344 ivch_write(dvo, backup_addresses[i], priv->reg_backup[i]); 345 } 346 347 /* Sets the power state of the panel connected to the ivch */ 348 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) 349 { 350 int i; 351 u16 vr01, vr30, backlight; 352 353 ivch_reset(dvo); 354 355 /* Set the new power state of the panel. */ 356 if (!ivch_read(dvo, VR01, &vr01)) 357 return; 358 359 if (enable) 360 backlight = 1; 361 else 362 backlight = 0; 363 364 ivch_write(dvo, VR80, backlight); 365 366 if (enable) 367 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE; 368 else 369 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE); 370 371 ivch_write(dvo, VR01, vr01); 372 373 /* Wait for the panel to make its state transition */ 374 for (i = 0; i < 100; i++) { 375 if (!ivch_read(dvo, VR30, &vr30)) 376 break; 377 378 if (((vr30 & VR30_PANEL_ON) != 0) == enable) 379 break; 380 udelay(1000); 381 } 382 /* wait some more; vch may fail to resync sometimes without this */ 383 udelay(16 * 1000); 384 } 385 386 static bool ivch_get_hw_state(struct intel_dvo_device *dvo) 387 { 388 u16 vr01; 389 390 ivch_reset(dvo); 391 392 /* Set the new power state of the panel. */ 393 if (!ivch_read(dvo, VR01, &vr01)) 394 return false; 395 396 if (vr01 & VR01_LCD_ENABLE) 397 return true; 398 else 399 return false; 400 } 401 402 static void ivch_mode_set(struct intel_dvo_device *dvo, 403 const struct drm_display_mode *mode, 404 const struct drm_display_mode *adjusted_mode) 405 { 406 struct ivch_priv *priv = dvo->dev_priv; 407 u16 vr40 = 0; 408 u16 vr01 = 0; 409 u16 vr10; 410 411 ivch_reset(dvo); 412 413 vr10 = priv->reg_backup[ARRAY_SIZE(backup_addresses) - 1]; 414 415 /* Enable dithering for 18 bpp pipelines */ 416 vr10 &= VR10_INTERFACE_DEPTH_MASK; 417 if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18) 418 vr01 = VR01_DITHER_ENABLE; 419 420 vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | 421 VR40_HORIZONTAL_INTERP_ENABLE); 422 423 if (mode->hdisplay != adjusted_mode->crtc_hdisplay || 424 mode->vdisplay != adjusted_mode->crtc_vdisplay) { 425 u16 x_ratio, y_ratio; 426 427 vr01 |= VR01_PANEL_FIT_ENABLE; 428 vr40 |= VR40_CLOCK_GATING_ENABLE; 429 x_ratio = (((mode->hdisplay - 1) << 16) / 430 (adjusted_mode->crtc_hdisplay - 1)) >> 2; 431 y_ratio = (((mode->vdisplay - 1) << 16) / 432 (adjusted_mode->crtc_vdisplay - 1)) >> 2; 433 ivch_write(dvo, VR42, x_ratio); 434 ivch_write(dvo, VR41, y_ratio); 435 } else { 436 vr01 &= ~VR01_PANEL_FIT_ENABLE; 437 vr40 &= ~VR40_CLOCK_GATING_ENABLE; 438 } 439 vr40 &= ~VR40_AUTO_RATIO_ENABLE; 440 441 ivch_write(dvo, VR01, vr01); 442 ivch_write(dvo, VR40, vr40); 443 } 444 445 static void ivch_dump_regs(struct intel_dvo_device *dvo) 446 { 447 u16 val; 448 449 ivch_read(dvo, VR00, &val); 450 DRM_DEBUG_KMS("VR00: 0x%04x\n", val); 451 ivch_read(dvo, VR01, &val); 452 DRM_DEBUG_KMS("VR01: 0x%04x\n", val); 453 ivch_read(dvo, VR10, &val); 454 DRM_DEBUG_KMS("VR10: 0x%04x\n", val); 455 ivch_read(dvo, VR30, &val); 456 DRM_DEBUG_KMS("VR30: 0x%04x\n", val); 457 ivch_read(dvo, VR40, &val); 458 DRM_DEBUG_KMS("VR40: 0x%04x\n", val); 459 460 /* GPIO registers */ 461 ivch_read(dvo, VR80, &val); 462 DRM_DEBUG_KMS("VR80: 0x%04x\n", val); 463 ivch_read(dvo, VR81, &val); 464 DRM_DEBUG_KMS("VR81: 0x%04x\n", val); 465 ivch_read(dvo, VR82, &val); 466 DRM_DEBUG_KMS("VR82: 0x%04x\n", val); 467 ivch_read(dvo, VR83, &val); 468 DRM_DEBUG_KMS("VR83: 0x%04x\n", val); 469 ivch_read(dvo, VR84, &val); 470 DRM_DEBUG_KMS("VR84: 0x%04x\n", val); 471 ivch_read(dvo, VR85, &val); 472 DRM_DEBUG_KMS("VR85: 0x%04x\n", val); 473 ivch_read(dvo, VR86, &val); 474 DRM_DEBUG_KMS("VR86: 0x%04x\n", val); 475 ivch_read(dvo, VR87, &val); 476 DRM_DEBUG_KMS("VR87: 0x%04x\n", val); 477 ivch_read(dvo, VR88, &val); 478 DRM_DEBUG_KMS("VR88: 0x%04x\n", val); 479 480 /* Scratch register 0 - AIM Panel type */ 481 ivch_read(dvo, VR8E, &val); 482 DRM_DEBUG_KMS("VR8E: 0x%04x\n", val); 483 484 /* Scratch register 1 - Status register */ 485 ivch_read(dvo, VR8F, &val); 486 DRM_DEBUG_KMS("VR8F: 0x%04x\n", val); 487 } 488 489 static void ivch_destroy(struct intel_dvo_device *dvo) 490 { 491 struct ivch_priv *priv = dvo->dev_priv; 492 493 if (priv) { 494 kfree(priv); 495 dvo->dev_priv = NULL; 496 } 497 } 498 499 const struct intel_dvo_dev_ops ivch_ops = { 500 .init = ivch_init, 501 .dpms = ivch_dpms, 502 .get_hw_state = ivch_get_hw_state, 503 .mode_valid = ivch_mode_valid, 504 .mode_set = ivch_mode_set, 505 .detect = ivch_detect, 506 .dump_regs = ivch_dump_regs, 507 .destroy = ivch_destroy, 508 }; 509
Indexes created Sat Sep 20 22:09:52 GMT 2025