Home | History | Annotate | Line # | Download | only in ixgbe 
      1 /* $NetBSD: ixgbe_osdep.c,v 1.9 2023/10/06 14:37:04 msaitoh Exp $ */
      2 
      3 /******************************************************************************
      4 
      5   Copyright (c) 2001-2020, Intel Corporation
      6   All rights reserved.
      7 
      8   Redistribution and use in source and binary forms, with or without
      9   modification, are permitted provided that the following conditions are met:
     10 
     11    1. Redistributions of source code must retain the above copyright notice,
     12       this list of conditions and the following disclaimer.
     13 
     14    2. Redistributions in binary form must reproduce the above copyright
     15       notice, this list of conditions and the following disclaimer in the
     16       documentation and/or other materials provided with the distribution.
     17 
     18    3. Neither the name of the Intel Corporation nor the names of its
     19       contributors may be used to endorse or promote products derived from
     20       this software without specific prior written permission.
     21 
     22   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     23   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     26   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     27   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     28   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     29   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     30   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     31   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     32   POSSIBILITY OF SUCH DAMAGE.
     33 
     34 ******************************************************************************/
     35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.c 327031 2017-12-20 18:15:06Z erj $*/
     36 
     37 #include <sys/cdefs.h>
     38 __KERNEL_RCSID(0, "$NetBSD: ixgbe_osdep.c,v 1.9 2023/10/06 14:37:04 msaitoh Exp $");
     39 
     40 #include "ixgbe_osdep.h"
     41 #include "ixgbe.h"
     42 
     43 inline device_t
     44 ixgbe_dev_from_hw(struct ixgbe_hw *hw)
     45 {
     46 	return ((struct ixgbe_softc *)hw->back)->dev;
     47 }
     48 
     49 u16
     50 ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
     51 {
     52 	pci_chipset_tag_t  pc = hw->back->osdep.pc;
     53 	pcitag_t           tag = hw->back->osdep.tag;
     54 
     55 	switch (reg % 4) {
     56 	case 0:
     57 		return pci_conf_read(pc, tag, reg) & __BITS(15, 0);
     58 	case 2:
     59 		return __SHIFTOUT(pci_conf_read(pc, tag, reg - 2),
     60 		    __BITS(31, 16));
     61 	default:
     62 		panic("%s: invalid register (%" PRIx32, __func__, reg);
     63 		break;
     64 	}
     65 }
     66 
     67 void
     68 ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)
     69 {
     70 	pci_chipset_tag_t  pc = hw->back->osdep.pc;
     71 	pcitag_t           tag = hw->back->osdep.tag;
     72 	pcireg_t old;
     73 
     74 	switch (reg % 4) {
     75 	case 0:
     76 		old = pci_conf_read(pc, tag, reg) & __BITS(31, 16);
     77 		pci_conf_write(pc, tag, reg, value | old);
     78 		break;
     79 	case 2:
     80 		old = pci_conf_read(pc, tag, reg - 2) & __BITS(15, 0);
     81 		pci_conf_write(pc, tag, reg - 2,
     82 		    __SHIFTIN(value, __BITS(31, 16)) | old);
     83 		break;
     84 	default:
     85 		panic("%s: invalid register (%" PRIx32, __func__, reg);
     86 		break;
     87 	}
     88 
     89 	return;
     90 }
     91 
     92 inline u32
     93 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
     94 {
     95 	return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
     96 	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle, reg);
     97 }
     98 
     99 inline void
    100 ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)
    101 {
    102 	bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
    103 	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
    104 	    reg, val);
    105 }
    106 
    107 inline u32
    108 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)
    109 {
    110 	return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
    111 	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
    112 	    reg + (offset << 2));
    113 }
    114 
    115 inline void
    116 ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)
    117 {
    118 	bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
    119 	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
    120 	    reg + (offset << 2), val);
    121 }
    122 
    123 inline void
    124 ixgbe_write_barrier(struct ixgbe_hw *hw)
    125 {
    126 	bus_space_barrier(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
    127 	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
    128 	    0, ((struct ixgbe_softc *)hw->back)->osdep.mem_size,
    129 	    BUS_SPACE_BARRIER_WRITE);
    130 }
    131