1 /* $NetBSD: ixp12x0.c,v 1.22 2025/06/25 06:21:28 andvar Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ixp12x0.c,v 1.22 2025/06/25 06:21:28 andvar Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <uvm/uvm.h> 36 37 #include <sys/bus.h> 38 39 #include <arm/ixp12x0/ixp12x0reg.h> 40 #include <arm/ixp12x0/ixp12x0var.h> 41 #include <arm/ixp12x0/ixp12x0_pcireg.h> 42 43 static struct ixp12x0_softc *ixp12x0_softc; 44 45 void 46 ixp12x0_attach(struct ixp12x0_softc *sc) 47 { 48 struct pcibus_attach_args pba; 49 pcireg_t reg; 50 51 ixp12x0_softc = sc; 52 53 printf("\n"); 54 55 sc->sc_iot = &ixp12x0_bs_tag; 56 57 /* 58 * Mapping for PCI Configuration Space Registers 59 */ 60 if (bus_space_map(sc->sc_iot, IXP12X0_PCI_HWBASE, IXP12X0_PCI_SIZE, 61 0, &sc->sc_pci_ioh)) 62 panic("%s: unable to map PCI registers", device_xname(sc->sc_dev)); 63 if (bus_space_map(sc->sc_iot, IXP12X0_PCI_TYPE0_HWBASE, 64 IXP12X0_PCI_TYPE0_SIZE, 0, &sc->sc_conf0_ioh)) 65 panic("%s: unable to map PCI Configutation 0\n", 66 device_xname(sc->sc_dev)); 67 if (bus_space_map(sc->sc_iot, IXP12X0_PCI_TYPE1_HWBASE, 68 IXP12X0_PCI_TYPE0_SIZE, 1, &sc->sc_conf1_ioh)) 69 panic("%s: unable to map PCI Configutation 1\n", 70 device_xname(sc->sc_dev)); 71 72 /* 73 * PCI bus reset 74 */ 75 /* disable PCI command */ 76 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 77 PCI_COMMAND_STATUS_REG, 0xffff0000); 78 /* XXX assert PCI reset Mode */ 79 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 80 SA_CONTROL) &~ SA_CONTROL_PNR; 81 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 82 SA_CONTROL, reg); 83 DELAY(10); 84 85 /* XXX Disable door bell and outbound interrupt */ 86 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 87 PCI_CAP_PTR, 0xc); 88 /* Disable door bell int to PCI */ 89 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 90 DBELL_PCI_MASK, 0x0); 91 /* Disable door bell int to SA-core */ 92 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 93 DBELL_SA_MASK, 0x0); 94 95 /* We setup a 1:1 memory map of bus<->physical addresses */ 96 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 97 PCI_ADDR_EXT, 98 PCI_ADDR_EXT_PMSA(IXP12X0_PCI_MEM_HWBASE)); 99 100 /* XXX Negate PCI reset */ 101 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 102 SA_CONTROL) | SA_CONTROL_PNR; 103 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 104 SA_CONTROL, reg); 105 DELAY(10); 106 /* 107 * specify window size of memory access and SDRAM. 108 */ 109 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR, 110 IXP1200_PCI_MEM_BAR & IXP_PCI_MEM_BAR_MASK); 111 112 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR, 113 IXP1200_PCI_IO_BAR & IXP_PCI_IO_BAR_MASK); 114 115 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR, 116 IXP1200_PCI_DRAM_BAR & IXP_PCI_DRAM_BAR_MASK); 117 118 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 119 CSR_BASE_ADDR_MASK, CSR_BASE_ADDR_MASK_1M); 120 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 121 DRAM_BASE_ADDR_MASK, DRAM_BASE_ADDR_MASK_256MB); 122 123 #ifdef PCI_DEBUG 124 printf("IXP_PCI_MEM_BAR = 0x%08x\nIXP_PCI_IO_BAR = 0x%08x\nIXP_PCI_DRAM_BAR = 0x%08x\nPCI_ADDR_EXT = 0x%08x\nCSR_BASE_ADDR_MASK = 0x%08x\nDRAM_BASE_ADDR_MASK = 0x%08x\n", 125 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR), 126 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR), 127 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR), 128 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_ADDR_EXT), 129 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, CSR_BASE_ADDR_MASK), 130 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, DRAM_BASE_ADDR_MASK)); 131 #endif 132 /* Initialize complete */ 133 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 134 SA_CONTROL) | 0x1; 135 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 136 SA_CONTROL, reg); 137 #ifdef PCI_DEBUG 138 printf("SA_CONTROL = 0x%08x\n", 139 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, SA_CONTROL)); 140 #endif 141 /* 142 * Enable bus mastering and I/O,memory access 143 */ 144 /* host only */ 145 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 146 PCI_COMMAND_STATUS_REG) | 147 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 148 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE | 149 PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 150 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 151 PCI_COMMAND_STATUS_REG, reg); 152 #ifdef PCI_DEBUG 153 printf("PCI_COMMAND_STATUS_REG = 0x%08x\n", 154 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_COMMAND_STATUS_REG)); 155 #endif 156 /* 157 * Initialize the PCI chipset tag. 158 */ 159 ixp12x0_pci_init(&sc->ia_pci_chipset, sc); 160 161 /* 162 * Initialize the DMA tags. 163 */ 164 ixp12x0_pci_dma_init(sc); 165 166 /* 167 * Attach the PCI bus. 168 */ 169 pba.pba_pc = &sc->ia_pci_chipset; 170 pba.pba_iot = &ixp12x0_bs_tag; 171 pba.pba_memt = &ixp12x0_bs_tag; 172 pba.pba_dmat = &sc->ia_pci_dmat; 173 pba.pba_dmat64 = NULL; 174 pba.pba_bus = 0; /* bus number = 0 */ 175 pba.pba_intrswiz = 0; /* XXX */ 176 pba.pba_intrtag = 0; 177 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 178 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 179 config_found(sc->sc_dev, &pba, pcibusprint, CFARGS_NONE); 180 } 181 182 void 183 ixp12x0_reset(void) 184 { 185 bus_space_write_4(ixp12x0_softc->sc_iot, ixp12x0_softc->sc_pci_ioh, 186 IXPPCI_IXP1200_RESET, RESET_FULL); 187 } 188
Indexes created Tue Sep 30 06:09:59 GMT 2025