1 /* $NetBSD: kfd_device.c,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: kfd_device.c,v 1.3 2021/12/18 23:44:59 riastradh Exp $"); 27 28 #include <linux/bsearch.h> 29 #include <linux/pci.h> 30 #include <linux/slab.h> 31 #include "kfd_priv.h" 32 #include "kfd_device_queue_manager.h" 33 #include "kfd_pm4_headers_vi.h" 34 #include "cwsr_trap_handler.h" 35 #include "kfd_iommu.h" 36 #include "amdgpu_amdkfd.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 54 55 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { 56 #ifdef KFD_SUPPORT_IOMMU_V2 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 [CHIP_KAVERI] = &gfx_v7_kfd2kgd, 59 #endif 60 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd, 61 [CHIP_RAVEN] = &gfx_v9_kfd2kgd, 62 #endif 63 #ifdef CONFIG_DRM_AMDGPU_CIK 64 [CHIP_HAWAII] = &gfx_v7_kfd2kgd, 65 #endif 66 [CHIP_TONGA] = &gfx_v8_kfd2kgd, 67 [CHIP_FIJI] = &gfx_v8_kfd2kgd, 68 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd, 69 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd, 70 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd, 71 [CHIP_VEGAM] = &gfx_v8_kfd2kgd, 72 [CHIP_VEGA10] = &gfx_v9_kfd2kgd, 73 [CHIP_VEGA12] = &gfx_v9_kfd2kgd, 74 [CHIP_VEGA20] = &gfx_v9_kfd2kgd, 75 [CHIP_RENOIR] = &gfx_v9_kfd2kgd, 76 [CHIP_ARCTURUS] = &arcturus_kfd2kgd, 77 [CHIP_NAVI10] = &gfx_v10_kfd2kgd, 78 [CHIP_NAVI12] = &gfx_v10_kfd2kgd, 79 [CHIP_NAVI14] = &gfx_v10_kfd2kgd, 80 }; 81 82 #ifdef KFD_SUPPORT_IOMMU_V2 83 static const struct kfd_device_info kaveri_device_info = { 84 .asic_family = CHIP_KAVERI, 85 .asic_name = "kaveri", 86 .max_pasid_bits = 16, 87 /* max num of queues for KV.TODO should be a dynamic value */ 88 .max_no_of_hqd = 24, 89 .doorbell_size = 4, 90 .ih_ring_entry_size = 4 * sizeof(uint32_t), 91 .event_interrupt_class = &event_interrupt_class_cik, 92 .num_of_watch_points = 4, 93 .mqd_size_aligned = MQD_SIZE_ALIGNED, 94 .supports_cwsr = false, 95 .needs_iommu_device = true, 96 .needs_pci_atomics = false, 97 .num_sdma_engines = 2, 98 .num_xgmi_sdma_engines = 0, 99 .num_sdma_queues_per_engine = 2, 100 }; 101 102 static const struct kfd_device_info carrizo_device_info = { 103 .asic_family = CHIP_CARRIZO, 104 .asic_name = "carrizo", 105 .max_pasid_bits = 16, 106 /* max num of queues for CZ.TODO should be a dynamic value */ 107 .max_no_of_hqd = 24, 108 .doorbell_size = 4, 109 .ih_ring_entry_size = 4 * sizeof(uint32_t), 110 .event_interrupt_class = &event_interrupt_class_cik, 111 .num_of_watch_points = 4, 112 .mqd_size_aligned = MQD_SIZE_ALIGNED, 113 .supports_cwsr = true, 114 .needs_iommu_device = true, 115 .needs_pci_atomics = false, 116 .num_sdma_engines = 2, 117 .num_xgmi_sdma_engines = 0, 118 .num_sdma_queues_per_engine = 2, 119 }; 120 121 static const struct kfd_device_info raven_device_info = { 122 .asic_family = CHIP_RAVEN, 123 .asic_name = "raven", 124 .max_pasid_bits = 16, 125 .max_no_of_hqd = 24, 126 .doorbell_size = 8, 127 .ih_ring_entry_size = 8 * sizeof(uint32_t), 128 .event_interrupt_class = &event_interrupt_class_v9, 129 .num_of_watch_points = 4, 130 .mqd_size_aligned = MQD_SIZE_ALIGNED, 131 .supports_cwsr = true, 132 .needs_iommu_device = true, 133 .needs_pci_atomics = true, 134 .num_sdma_engines = 1, 135 .num_xgmi_sdma_engines = 0, 136 .num_sdma_queues_per_engine = 2, 137 }; 138 #endif 139 140 static const struct kfd_device_info hawaii_device_info = { 141 .asic_family = CHIP_HAWAII, 142 .asic_name = "hawaii", 143 .max_pasid_bits = 16, 144 /* max num of queues for KV.TODO should be a dynamic value */ 145 .max_no_of_hqd = 24, 146 .doorbell_size = 4, 147 .ih_ring_entry_size = 4 * sizeof(uint32_t), 148 .event_interrupt_class = &event_interrupt_class_cik, 149 .num_of_watch_points = 4, 150 .mqd_size_aligned = MQD_SIZE_ALIGNED, 151 .supports_cwsr = false, 152 .needs_iommu_device = false, 153 .needs_pci_atomics = false, 154 .num_sdma_engines = 2, 155 .num_xgmi_sdma_engines = 0, 156 .num_sdma_queues_per_engine = 2, 157 }; 158 159 static const struct kfd_device_info tonga_device_info = { 160 .asic_family = CHIP_TONGA, 161 .asic_name = "tonga", 162 .max_pasid_bits = 16, 163 .max_no_of_hqd = 24, 164 .doorbell_size = 4, 165 .ih_ring_entry_size = 4 * sizeof(uint32_t), 166 .event_interrupt_class = &event_interrupt_class_cik, 167 .num_of_watch_points = 4, 168 .mqd_size_aligned = MQD_SIZE_ALIGNED, 169 .supports_cwsr = false, 170 .needs_iommu_device = false, 171 .needs_pci_atomics = true, 172 .num_sdma_engines = 2, 173 .num_xgmi_sdma_engines = 0, 174 .num_sdma_queues_per_engine = 2, 175 }; 176 177 static const struct kfd_device_info fiji_device_info = { 178 .asic_family = CHIP_FIJI, 179 .asic_name = "fiji", 180 .max_pasid_bits = 16, 181 .max_no_of_hqd = 24, 182 .doorbell_size = 4, 183 .ih_ring_entry_size = 4 * sizeof(uint32_t), 184 .event_interrupt_class = &event_interrupt_class_cik, 185 .num_of_watch_points = 4, 186 .mqd_size_aligned = MQD_SIZE_ALIGNED, 187 .supports_cwsr = true, 188 .needs_iommu_device = false, 189 .needs_pci_atomics = true, 190 .num_sdma_engines = 2, 191 .num_xgmi_sdma_engines = 0, 192 .num_sdma_queues_per_engine = 2, 193 }; 194 195 static const struct kfd_device_info fiji_vf_device_info = { 196 .asic_family = CHIP_FIJI, 197 .asic_name = "fiji", 198 .max_pasid_bits = 16, 199 .max_no_of_hqd = 24, 200 .doorbell_size = 4, 201 .ih_ring_entry_size = 4 * sizeof(uint32_t), 202 .event_interrupt_class = &event_interrupt_class_cik, 203 .num_of_watch_points = 4, 204 .mqd_size_aligned = MQD_SIZE_ALIGNED, 205 .supports_cwsr = true, 206 .needs_iommu_device = false, 207 .needs_pci_atomics = false, 208 .num_sdma_engines = 2, 209 .num_xgmi_sdma_engines = 0, 210 .num_sdma_queues_per_engine = 2, 211 }; 212 213 214 static const struct kfd_device_info polaris10_device_info = { 215 .asic_family = CHIP_POLARIS10, 216 .asic_name = "polaris10", 217 .max_pasid_bits = 16, 218 .max_no_of_hqd = 24, 219 .doorbell_size = 4, 220 .ih_ring_entry_size = 4 * sizeof(uint32_t), 221 .event_interrupt_class = &event_interrupt_class_cik, 222 .num_of_watch_points = 4, 223 .mqd_size_aligned = MQD_SIZE_ALIGNED, 224 .supports_cwsr = true, 225 .needs_iommu_device = false, 226 .needs_pci_atomics = true, 227 .num_sdma_engines = 2, 228 .num_xgmi_sdma_engines = 0, 229 .num_sdma_queues_per_engine = 2, 230 }; 231 232 static const struct kfd_device_info polaris10_vf_device_info = { 233 .asic_family = CHIP_POLARIS10, 234 .asic_name = "polaris10", 235 .max_pasid_bits = 16, 236 .max_no_of_hqd = 24, 237 .doorbell_size = 4, 238 .ih_ring_entry_size = 4 * sizeof(uint32_t), 239 .event_interrupt_class = &event_interrupt_class_cik, 240 .num_of_watch_points = 4, 241 .mqd_size_aligned = MQD_SIZE_ALIGNED, 242 .supports_cwsr = true, 243 .needs_iommu_device = false, 244 .needs_pci_atomics = false, 245 .num_sdma_engines = 2, 246 .num_xgmi_sdma_engines = 0, 247 .num_sdma_queues_per_engine = 2, 248 }; 249 250 static const struct kfd_device_info polaris11_device_info = { 251 .asic_family = CHIP_POLARIS11, 252 .asic_name = "polaris11", 253 .max_pasid_bits = 16, 254 .max_no_of_hqd = 24, 255 .doorbell_size = 4, 256 .ih_ring_entry_size = 4 * sizeof(uint32_t), 257 .event_interrupt_class = &event_interrupt_class_cik, 258 .num_of_watch_points = 4, 259 .mqd_size_aligned = MQD_SIZE_ALIGNED, 260 .supports_cwsr = true, 261 .needs_iommu_device = false, 262 .needs_pci_atomics = true, 263 .num_sdma_engines = 2, 264 .num_xgmi_sdma_engines = 0, 265 .num_sdma_queues_per_engine = 2, 266 }; 267 268 static const struct kfd_device_info polaris12_device_info = { 269 .asic_family = CHIP_POLARIS12, 270 .asic_name = "polaris12", 271 .max_pasid_bits = 16, 272 .max_no_of_hqd = 24, 273 .doorbell_size = 4, 274 .ih_ring_entry_size = 4 * sizeof(uint32_t), 275 .event_interrupt_class = &event_interrupt_class_cik, 276 .num_of_watch_points = 4, 277 .mqd_size_aligned = MQD_SIZE_ALIGNED, 278 .supports_cwsr = true, 279 .needs_iommu_device = false, 280 .needs_pci_atomics = true, 281 .num_sdma_engines = 2, 282 .num_xgmi_sdma_engines = 0, 283 .num_sdma_queues_per_engine = 2, 284 }; 285 286 static const struct kfd_device_info vegam_device_info = { 287 .asic_family = CHIP_VEGAM, 288 .asic_name = "vegam", 289 .max_pasid_bits = 16, 290 .max_no_of_hqd = 24, 291 .doorbell_size = 4, 292 .ih_ring_entry_size = 4 * sizeof(uint32_t), 293 .event_interrupt_class = &event_interrupt_class_cik, 294 .num_of_watch_points = 4, 295 .mqd_size_aligned = MQD_SIZE_ALIGNED, 296 .supports_cwsr = true, 297 .needs_iommu_device = false, 298 .needs_pci_atomics = true, 299 .num_sdma_engines = 2, 300 .num_xgmi_sdma_engines = 0, 301 .num_sdma_queues_per_engine = 2, 302 }; 303 304 static const struct kfd_device_info vega10_device_info = { 305 .asic_family = CHIP_VEGA10, 306 .asic_name = "vega10", 307 .max_pasid_bits = 16, 308 .max_no_of_hqd = 24, 309 .doorbell_size = 8, 310 .ih_ring_entry_size = 8 * sizeof(uint32_t), 311 .event_interrupt_class = &event_interrupt_class_v9, 312 .num_of_watch_points = 4, 313 .mqd_size_aligned = MQD_SIZE_ALIGNED, 314 .supports_cwsr = true, 315 .needs_iommu_device = false, 316 .needs_pci_atomics = false, 317 .num_sdma_engines = 2, 318 .num_xgmi_sdma_engines = 0, 319 .num_sdma_queues_per_engine = 2, 320 }; 321 322 static const struct kfd_device_info vega10_vf_device_info = { 323 .asic_family = CHIP_VEGA10, 324 .asic_name = "vega10", 325 .max_pasid_bits = 16, 326 .max_no_of_hqd = 24, 327 .doorbell_size = 8, 328 .ih_ring_entry_size = 8 * sizeof(uint32_t), 329 .event_interrupt_class = &event_interrupt_class_v9, 330 .num_of_watch_points = 4, 331 .mqd_size_aligned = MQD_SIZE_ALIGNED, 332 .supports_cwsr = true, 333 .needs_iommu_device = false, 334 .needs_pci_atomics = false, 335 .num_sdma_engines = 2, 336 .num_xgmi_sdma_engines = 0, 337 .num_sdma_queues_per_engine = 2, 338 }; 339 340 static const struct kfd_device_info vega12_device_info = { 341 .asic_family = CHIP_VEGA12, 342 .asic_name = "vega12", 343 .max_pasid_bits = 16, 344 .max_no_of_hqd = 24, 345 .doorbell_size = 8, 346 .ih_ring_entry_size = 8 * sizeof(uint32_t), 347 .event_interrupt_class = &event_interrupt_class_v9, 348 .num_of_watch_points = 4, 349 .mqd_size_aligned = MQD_SIZE_ALIGNED, 350 .supports_cwsr = true, 351 .needs_iommu_device = false, 352 .needs_pci_atomics = false, 353 .num_sdma_engines = 2, 354 .num_xgmi_sdma_engines = 0, 355 .num_sdma_queues_per_engine = 2, 356 }; 357 358 static const struct kfd_device_info vega20_device_info = { 359 .asic_family = CHIP_VEGA20, 360 .asic_name = "vega20", 361 .max_pasid_bits = 16, 362 .max_no_of_hqd = 24, 363 .doorbell_size = 8, 364 .ih_ring_entry_size = 8 * sizeof(uint32_t), 365 .event_interrupt_class = &event_interrupt_class_v9, 366 .num_of_watch_points = 4, 367 .mqd_size_aligned = MQD_SIZE_ALIGNED, 368 .supports_cwsr = true, 369 .needs_iommu_device = false, 370 .needs_pci_atomics = false, 371 .num_sdma_engines = 2, 372 .num_xgmi_sdma_engines = 0, 373 .num_sdma_queues_per_engine = 8, 374 }; 375 376 static const struct kfd_device_info arcturus_device_info = { 377 .asic_family = CHIP_ARCTURUS, 378 .asic_name = "arcturus", 379 .max_pasid_bits = 16, 380 .max_no_of_hqd = 24, 381 .doorbell_size = 8, 382 .ih_ring_entry_size = 8 * sizeof(uint32_t), 383 .event_interrupt_class = &event_interrupt_class_v9, 384 .num_of_watch_points = 4, 385 .mqd_size_aligned = MQD_SIZE_ALIGNED, 386 .supports_cwsr = true, 387 .needs_iommu_device = false, 388 .needs_pci_atomics = false, 389 .num_sdma_engines = 2, 390 .num_xgmi_sdma_engines = 6, 391 .num_sdma_queues_per_engine = 8, 392 }; 393 394 static const struct kfd_device_info renoir_device_info = { 395 .asic_family = CHIP_RENOIR, 396 .asic_name = "renoir", 397 .max_pasid_bits = 16, 398 .max_no_of_hqd = 24, 399 .doorbell_size = 8, 400 .ih_ring_entry_size = 8 * sizeof(uint32_t), 401 .event_interrupt_class = &event_interrupt_class_v9, 402 .num_of_watch_points = 4, 403 .mqd_size_aligned = MQD_SIZE_ALIGNED, 404 .supports_cwsr = true, 405 .needs_iommu_device = false, 406 .needs_pci_atomics = false, 407 .num_sdma_engines = 1, 408 .num_xgmi_sdma_engines = 0, 409 .num_sdma_queues_per_engine = 2, 410 }; 411 412 static const struct kfd_device_info navi10_device_info = { 413 .asic_family = CHIP_NAVI10, 414 .asic_name = "navi10", 415 .max_pasid_bits = 16, 416 .max_no_of_hqd = 24, 417 .doorbell_size = 8, 418 .ih_ring_entry_size = 8 * sizeof(uint32_t), 419 .event_interrupt_class = &event_interrupt_class_v9, 420 .num_of_watch_points = 4, 421 .mqd_size_aligned = MQD_SIZE_ALIGNED, 422 .needs_iommu_device = false, 423 .supports_cwsr = true, 424 .needs_pci_atomics = false, 425 .num_sdma_engines = 2, 426 .num_xgmi_sdma_engines = 0, 427 .num_sdma_queues_per_engine = 8, 428 }; 429 430 static const struct kfd_device_info navi12_device_info = { 431 .asic_family = CHIP_NAVI12, 432 .asic_name = "navi12", 433 .max_pasid_bits = 16, 434 .max_no_of_hqd = 24, 435 .doorbell_size = 8, 436 .ih_ring_entry_size = 8 * sizeof(uint32_t), 437 .event_interrupt_class = &event_interrupt_class_v9, 438 .num_of_watch_points = 4, 439 .mqd_size_aligned = MQD_SIZE_ALIGNED, 440 .needs_iommu_device = false, 441 .supports_cwsr = true, 442 .needs_pci_atomics = false, 443 .num_sdma_engines = 2, 444 .num_xgmi_sdma_engines = 0, 445 .num_sdma_queues_per_engine = 8, 446 }; 447 448 static const struct kfd_device_info navi14_device_info = { 449 .asic_family = CHIP_NAVI14, 450 .asic_name = "navi14", 451 .max_pasid_bits = 16, 452 .max_no_of_hqd = 24, 453 .doorbell_size = 8, 454 .ih_ring_entry_size = 8 * sizeof(uint32_t), 455 .event_interrupt_class = &event_interrupt_class_v9, 456 .num_of_watch_points = 4, 457 .mqd_size_aligned = MQD_SIZE_ALIGNED, 458 .needs_iommu_device = false, 459 .supports_cwsr = true, 460 .needs_pci_atomics = false, 461 .num_sdma_engines = 2, 462 .num_xgmi_sdma_engines = 0, 463 .num_sdma_queues_per_engine = 8, 464 }; 465 466 /* For each entry, [0] is regular and [1] is virtualisation device. */ 467 static const struct kfd_device_info *kfd_supported_devices[][2] = { 468 #ifdef KFD_SUPPORT_IOMMU_V2 469 [CHIP_KAVERI] = {&kaveri_device_info, NULL}, 470 [CHIP_CARRIZO] = {&carrizo_device_info, NULL}, 471 [CHIP_RAVEN] = {&raven_device_info, NULL}, 472 #endif 473 [CHIP_HAWAII] = {&hawaii_device_info, NULL}, 474 [CHIP_TONGA] = {&tonga_device_info, NULL}, 475 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info}, 476 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info}, 477 [CHIP_POLARIS11] = {&polaris11_device_info, NULL}, 478 [CHIP_POLARIS12] = {&polaris12_device_info, NULL}, 479 [CHIP_VEGAM] = {&vegam_device_info, NULL}, 480 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info}, 481 [CHIP_VEGA12] = {&vega12_device_info, NULL}, 482 [CHIP_VEGA20] = {&vega20_device_info, NULL}, 483 [CHIP_RENOIR] = {&renoir_device_info, NULL}, 484 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, 485 [CHIP_NAVI10] = {&navi10_device_info, NULL}, 486 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, 487 [CHIP_NAVI14] = {&navi14_device_info, NULL}, 488 }; 489 490 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 491 unsigned int chunk_size); 492 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 493 494 static int kfd_resume(struct kfd_dev *kfd); 495 496 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 497 struct pci_dev *pdev, unsigned int asic_type, bool vf) 498 { 499 struct kfd_dev *kfd; 500 const struct kfd_device_info *device_info; 501 const struct kfd2kgd_calls *f2g; 502 503 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2) 504 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) { 505 dev_err(kfd_device, "asic_type %d out of range\n", asic_type); 506 return NULL; /* asic_type out of range */ 507 } 508 509 device_info = kfd_supported_devices[asic_type][vf]; 510 f2g = kfd2kgd_funcs[asic_type]; 511 512 if (!device_info || !f2g) { 513 dev_err(kfd_device, "%s %s not supported in kfd\n", 514 amdgpu_asic_name[asic_type], vf ? "VF" : ""); 515 return NULL; 516 } 517 518 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 519 if (!kfd) 520 return NULL; 521 522 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 523 * 32 and 64-bit requests are possible and must be 524 * supported. 525 */ 526 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd); 527 if (device_info->needs_pci_atomics && 528 !kfd->pci_atomic_requested) { 529 dev_info(kfd_device, 530 "skipped device %x:%x, PCI rejects atomics\n", 531 pdev->vendor, pdev->device); 532 kfree(kfd); 533 return NULL; 534 } 535 536 kfd->kgd = kgd; 537 kfd->device_info = device_info; 538 kfd->pdev = pdev; 539 kfd->init_complete = false; 540 kfd->kfd2kgd = f2g; 541 atomic_set(&kfd->compute_profile, 0); 542 543 mutex_init(&kfd->doorbell_mutex); 544 memset(&kfd->doorbell_available_index, 0, 545 sizeof(kfd->doorbell_available_index)); 546 547 atomic_set(&kfd->sram_ecc_flag, 0); 548 549 return kfd; 550 } 551 552 static void kfd_cwsr_init(struct kfd_dev *kfd) 553 { 554 if (cwsr_enable && kfd->device_info->supports_cwsr) { 555 if (kfd->device_info->asic_family < CHIP_VEGA10) { 556 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 557 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 558 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 559 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 560 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 561 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 562 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 563 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 564 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 565 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 566 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 567 } else { 568 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 569 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 570 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 571 } 572 573 kfd->cwsr_enabled = true; 574 } 575 } 576 577 bool kgd2kfd_device_init(struct kfd_dev *kfd, 578 struct drm_device *ddev, 579 const struct kgd2kfd_shared_resources *gpu_resources) 580 { 581 unsigned int size; 582 583 kfd->ddev = ddev; 584 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 585 KGD_ENGINE_MEC1); 586 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 587 KGD_ENGINE_SDMA1); 588 kfd->shared_resources = *gpu_resources; 589 590 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 591 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 592 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 593 - kfd->vm_info.first_vmid_kfd + 1; 594 595 /* Verify module parameters regarding mapped process number*/ 596 if ((hws_max_conc_proc < 0) 597 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 598 dev_err(kfd_device, 599 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 600 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 601 kfd->vm_info.vmid_num_kfd); 602 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 603 } else 604 kfd->max_proc_per_quantum = hws_max_conc_proc; 605 606 /* Allocate global GWS that is shared by all KFD processes */ 607 if (hws_gws_support && amdgpu_amdkfd_alloc_gws(kfd->kgd, 608 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws)) { 609 dev_err(kfd_device, "Could not allocate %d gws\n", 610 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 611 goto out; 612 } 613 /* calculate max size of mqds needed for queues */ 614 size = max_num_of_queues_per_device * 615 kfd->device_info->mqd_size_aligned; 616 617 /* 618 * calculate max size of runlist packet. 619 * There can be only 2 packets at once 620 */ 621 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 622 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 623 + sizeof(struct pm4_mes_runlist)) * 2; 624 625 /* Add size of HIQ & DIQ */ 626 size += KFD_KERNEL_QUEUE_SIZE * 2; 627 628 /* add another 512KB for all other allocations on gart (HPD, fences) */ 629 size += 512 * 1024; 630 631 if (amdgpu_amdkfd_alloc_gtt_mem( 632 kfd->kgd, size, &kfd->gtt_mem, 633 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 634 false)) { 635 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 636 goto alloc_gtt_mem_failure; 637 } 638 639 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 640 641 /* Initialize GTT sa with 512 byte chunk size */ 642 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 643 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 644 goto kfd_gtt_sa_init_error; 645 } 646 647 if (kfd_doorbell_init(kfd)) { 648 dev_err(kfd_device, 649 "Error initializing doorbell aperture\n"); 650 goto kfd_doorbell_error; 651 } 652 653 if (kfd->kfd2kgd->get_hive_id) 654 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 655 656 if (kfd_interrupt_init(kfd)) { 657 dev_err(kfd_device, "Error initializing interrupts\n"); 658 goto kfd_interrupt_error; 659 } 660 661 kfd->dqm = device_queue_manager_init(kfd); 662 if (!kfd->dqm) { 663 dev_err(kfd_device, "Error initializing queue manager\n"); 664 goto device_queue_manager_error; 665 } 666 667 if (kfd_iommu_device_init(kfd)) { 668 dev_err(kfd_device, "Error initializing iommuv2\n"); 669 goto device_iommu_error; 670 } 671 672 kfd_cwsr_init(kfd); 673 674 if (kfd_resume(kfd)) 675 goto kfd_resume_error; 676 677 kfd->dbgmgr = NULL; 678 679 if (kfd_topology_add_device(kfd)) { 680 dev_err(kfd_device, "Error adding device to topology\n"); 681 goto kfd_topology_add_device_error; 682 } 683 684 kfd->init_complete = true; 685 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 686 kfd->pdev->device); 687 688 pr_debug("Starting kfd with the following scheduling policy %d\n", 689 kfd->dqm->sched_policy); 690 691 goto out; 692 693 kfd_topology_add_device_error: 694 kfd_resume_error: 695 device_iommu_error: 696 device_queue_manager_uninit(kfd->dqm); 697 device_queue_manager_error: 698 kfd_interrupt_exit(kfd); 699 kfd_interrupt_error: 700 kfd_doorbell_fini(kfd); 701 kfd_doorbell_error: 702 kfd_gtt_sa_fini(kfd); 703 kfd_gtt_sa_init_error: 704 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 705 alloc_gtt_mem_failure: 706 if (hws_gws_support) 707 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 708 dev_err(kfd_device, 709 "device %x:%x NOT added due to errors\n", 710 kfd->pdev->vendor, kfd->pdev->device); 711 out: 712 return kfd->init_complete; 713 } 714 715 void kgd2kfd_device_exit(struct kfd_dev *kfd) 716 { 717 if (kfd->init_complete) { 718 kgd2kfd_suspend(kfd); 719 device_queue_manager_uninit(kfd->dqm); 720 kfd_interrupt_exit(kfd); 721 kfd_topology_remove_device(kfd); 722 kfd_doorbell_fini(kfd); 723 kfd_gtt_sa_fini(kfd); 724 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 725 if (hws_gws_support) 726 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 727 } 728 729 kfree(kfd); 730 } 731 732 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 733 { 734 if (!kfd->init_complete) 735 return 0; 736 737 kfd->dqm->ops.pre_reset(kfd->dqm); 738 739 kgd2kfd_suspend(kfd); 740 741 kfd_signal_reset_event(kfd); 742 return 0; 743 } 744 745 /* 746 * Fix me. KFD won't be able to resume existing process for now. 747 * We will keep all existing process in a evicted state and 748 * wait the process to be terminated. 749 */ 750 751 int kgd2kfd_post_reset(struct kfd_dev *kfd) 752 { 753 int ret; 754 755 if (!kfd->init_complete) 756 return 0; 757 758 ret = kfd_resume(kfd); 759 if (ret) 760 return ret; 761 atomic_dec(&kfd_locked); 762 763 atomic_set(&kfd->sram_ecc_flag, 0); 764 765 return 0; 766 } 767 768 bool kfd_is_locked(void) 769 { 770 return (atomic_read(&kfd_locked) > 0); 771 } 772 773 void kgd2kfd_suspend(struct kfd_dev *kfd) 774 { 775 if (!kfd->init_complete) 776 return; 777 778 /* For first KFD device suspend all the KFD processes */ 779 if (atomic_inc_return(&kfd_locked) == 1) 780 kfd_suspend_all_processes(); 781 782 kfd->dqm->ops.stop(kfd->dqm); 783 784 kfd_iommu_suspend(kfd); 785 } 786 787 int kgd2kfd_resume(struct kfd_dev *kfd) 788 { 789 int ret, count; 790 791 if (!kfd->init_complete) 792 return 0; 793 794 ret = kfd_resume(kfd); 795 if (ret) 796 return ret; 797 798 count = atomic_dec_return(&kfd_locked); 799 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 800 if (count == 0) 801 ret = kfd_resume_all_processes(); 802 803 return ret; 804 } 805 806 static int kfd_resume(struct kfd_dev *kfd) 807 { 808 int err = 0; 809 810 err = kfd_iommu_resume(kfd); 811 if (err) { 812 dev_err(kfd_device, 813 "Failed to resume IOMMU for device %x:%x\n", 814 kfd->pdev->vendor, kfd->pdev->device); 815 return err; 816 } 817 818 err = kfd->dqm->ops.start(kfd->dqm); 819 if (err) { 820 dev_err(kfd_device, 821 "Error starting queue manager for device %x:%x\n", 822 kfd->pdev->vendor, kfd->pdev->device); 823 goto dqm_start_error; 824 } 825 826 return err; 827 828 dqm_start_error: 829 kfd_iommu_suspend(kfd); 830 return err; 831 } 832 833 static inline void kfd_queue_work(struct workqueue_struct *wq, 834 struct work_struct *work) 835 { 836 int cpu, new_cpu; 837 838 cpu = new_cpu = smp_processor_id(); 839 do { 840 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 841 if (cpu_to_node(new_cpu) == numa_node_id()) 842 break; 843 } while (cpu != new_cpu); 844 845 queue_work_on(new_cpu, wq, work); 846 } 847 848 /* This is called directly from KGD at ISR. */ 849 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 850 { 851 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 852 bool is_patched = false; 853 unsigned long flags; 854 855 if (!kfd->init_complete) 856 return; 857 858 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 859 dev_err_once(kfd_device, "Ring entry too small\n"); 860 return; 861 } 862 863 spin_lock_irqsave(&kfd->interrupt_lock, flags); 864 865 if (kfd->interrupts_active 866 && interrupt_is_wanted(kfd, ih_ring_entry, 867 patched_ihre, &is_patched) 868 && enqueue_ih_ring_entry(kfd, 869 is_patched ? patched_ihre : ih_ring_entry)) 870 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 871 872 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 873 } 874 875 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 876 { 877 struct kfd_process *p; 878 int r; 879 880 /* Because we are called from arbitrary context (workqueue) as opposed 881 * to process context, kfd_process could attempt to exit while we are 882 * running so the lookup function increments the process ref count. 883 */ 884 p = kfd_lookup_process_by_mm(mm); 885 if (!p) 886 return -ESRCH; 887 888 r = kfd_process_evict_queues(p); 889 890 kfd_unref_process(p); 891 return r; 892 } 893 894 int kgd2kfd_resume_mm(struct mm_struct *mm) 895 { 896 struct kfd_process *p; 897 int r; 898 899 /* Because we are called from arbitrary context (workqueue) as opposed 900 * to process context, kfd_process could attempt to exit while we are 901 * running so the lookup function increments the process ref count. 902 */ 903 p = kfd_lookup_process_by_mm(mm); 904 if (!p) 905 return -ESRCH; 906 907 r = kfd_process_restore_queues(p); 908 909 kfd_unref_process(p); 910 return r; 911 } 912 913 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 914 * prepare for safe eviction of KFD BOs that belong to the specified 915 * process. 916 * 917 * @mm: mm_struct that identifies the specified KFD process 918 * @fence: eviction fence attached to KFD process BOs 919 * 920 */ 921 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 922 struct dma_fence *fence) 923 { 924 struct kfd_process *p; 925 unsigned long active_time; 926 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 927 928 if (!fence) 929 return -EINVAL; 930 931 if (dma_fence_is_signaled(fence)) 932 return 0; 933 934 p = kfd_lookup_process_by_mm(mm); 935 if (!p) 936 return -ENODEV; 937 938 if (fence->seqno == p->last_eviction_seqno) 939 goto out; 940 941 p->last_eviction_seqno = fence->seqno; 942 943 /* Avoid KFD process starvation. Wait for at least 944 * PROCESS_ACTIVE_TIME_MS before evicting the process again 945 */ 946 active_time = get_jiffies_64() - p->last_restore_timestamp; 947 if (delay_jiffies > active_time) 948 delay_jiffies -= active_time; 949 else 950 delay_jiffies = 0; 951 952 /* During process initialization eviction_work.dwork is initialized 953 * to kfd_evict_bo_worker 954 */ 955 schedule_delayed_work(&p->eviction_work, delay_jiffies); 956 out: 957 kfd_unref_process(p); 958 return 0; 959 } 960 961 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 962 unsigned int chunk_size) 963 { 964 unsigned int num_of_longs; 965 966 if (WARN_ON(buf_size < chunk_size)) 967 return -EINVAL; 968 if (WARN_ON(buf_size == 0)) 969 return -EINVAL; 970 if (WARN_ON(chunk_size == 0)) 971 return -EINVAL; 972 973 kfd->gtt_sa_chunk_size = chunk_size; 974 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 975 976 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 977 BITS_PER_LONG; 978 979 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 980 981 if (!kfd->gtt_sa_bitmap) 982 return -ENOMEM; 983 984 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 985 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 986 987 mutex_init(&kfd->gtt_sa_lock); 988 989 return 0; 990 991 } 992 993 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 994 { 995 mutex_destroy(&kfd->gtt_sa_lock); 996 kfree(kfd->gtt_sa_bitmap); 997 } 998 999 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1000 unsigned int bit_num, 1001 unsigned int chunk_size) 1002 { 1003 return start_addr + bit_num * chunk_size; 1004 } 1005 1006 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1007 unsigned int bit_num, 1008 unsigned int chunk_size) 1009 { 1010 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1011 } 1012 1013 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1014 struct kfd_mem_obj **mem_obj) 1015 { 1016 unsigned int found, start_search, cur_size; 1017 1018 if (size == 0) 1019 return -EINVAL; 1020 1021 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1022 return -ENOMEM; 1023 1024 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1025 if (!(*mem_obj)) 1026 return -ENOMEM; 1027 1028 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1029 1030 start_search = 0; 1031 1032 mutex_lock(&kfd->gtt_sa_lock); 1033 1034 kfd_gtt_restart_search: 1035 /* Find the first chunk that is free */ 1036 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1037 kfd->gtt_sa_num_of_chunks, 1038 start_search); 1039 1040 pr_debug("Found = %d\n", found); 1041 1042 /* If there wasn't any free chunk, bail out */ 1043 if (found == kfd->gtt_sa_num_of_chunks) 1044 goto kfd_gtt_no_free_chunk; 1045 1046 /* Update fields of mem_obj */ 1047 (*mem_obj)->range_start = found; 1048 (*mem_obj)->range_end = found; 1049 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1050 kfd->gtt_start_gpu_addr, 1051 found, 1052 kfd->gtt_sa_chunk_size); 1053 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1054 kfd->gtt_start_cpu_ptr, 1055 found, 1056 kfd->gtt_sa_chunk_size); 1057 1058 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1059 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1060 1061 /* If we need only one chunk, mark it as allocated and get out */ 1062 if (size <= kfd->gtt_sa_chunk_size) { 1063 pr_debug("Single bit\n"); 1064 set_bit(found, kfd->gtt_sa_bitmap); 1065 goto kfd_gtt_out; 1066 } 1067 1068 /* Otherwise, try to see if we have enough contiguous chunks */ 1069 cur_size = size - kfd->gtt_sa_chunk_size; 1070 do { 1071 (*mem_obj)->range_end = 1072 find_next_zero_bit(kfd->gtt_sa_bitmap, 1073 kfd->gtt_sa_num_of_chunks, ++found); 1074 /* 1075 * If next free chunk is not contiguous than we need to 1076 * restart our search from the last free chunk we found (which 1077 * wasn't contiguous to the previous ones 1078 */ 1079 if ((*mem_obj)->range_end != found) { 1080 start_search = found; 1081 goto kfd_gtt_restart_search; 1082 } 1083 1084 /* 1085 * If we reached end of buffer, bail out with error 1086 */ 1087 if (found == kfd->gtt_sa_num_of_chunks) 1088 goto kfd_gtt_no_free_chunk; 1089 1090 /* Check if we don't need another chunk */ 1091 if (cur_size <= kfd->gtt_sa_chunk_size) 1092 cur_size = 0; 1093 else 1094 cur_size -= kfd->gtt_sa_chunk_size; 1095 1096 } while (cur_size > 0); 1097 1098 pr_debug("range_start = %d, range_end = %d\n", 1099 (*mem_obj)->range_start, (*mem_obj)->range_end); 1100 1101 /* Mark the chunks as allocated */ 1102 for (found = (*mem_obj)->range_start; 1103 found <= (*mem_obj)->range_end; 1104 found++) 1105 set_bit(found, kfd->gtt_sa_bitmap); 1106 1107 kfd_gtt_out: 1108 mutex_unlock(&kfd->gtt_sa_lock); 1109 return 0; 1110 1111 kfd_gtt_no_free_chunk: 1112 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 1113 mutex_unlock(&kfd->gtt_sa_lock); 1114 kfree(mem_obj); 1115 return -ENOMEM; 1116 } 1117 1118 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1119 { 1120 unsigned int bit; 1121 1122 /* Act like kfree when trying to free a NULL object */ 1123 if (!mem_obj) 1124 return 0; 1125 1126 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1127 mem_obj, mem_obj->range_start, mem_obj->range_end); 1128 1129 mutex_lock(&kfd->gtt_sa_lock); 1130 1131 /* Mark the chunks as free */ 1132 for (bit = mem_obj->range_start; 1133 bit <= mem_obj->range_end; 1134 bit++) 1135 clear_bit(bit, kfd->gtt_sa_bitmap); 1136 1137 mutex_unlock(&kfd->gtt_sa_lock); 1138 1139 kfree(mem_obj); 1140 return 0; 1141 } 1142 1143 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1144 { 1145 if (kfd) 1146 atomic_inc(&kfd->sram_ecc_flag); 1147 } 1148 1149 void kfd_inc_compute_active(struct kfd_dev *kfd) 1150 { 1151 if (atomic_inc_return(&kfd->compute_profile) == 1) 1152 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1153 } 1154 1155 void kfd_dec_compute_active(struct kfd_dev *kfd) 1156 { 1157 int count = atomic_dec_return(&kfd->compute_profile); 1158 1159 if (count == 0) 1160 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1161 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1162 } 1163 1164 #if defined(CONFIG_DEBUG_FS) 1165 1166 /* This function will send a package to HIQ to hang the HWS 1167 * which will trigger a GPU reset and bring the HWS back to normal state 1168 */ 1169 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1170 { 1171 int r = 0; 1172 1173 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1174 pr_err("HWS is not enabled"); 1175 return -EINVAL; 1176 } 1177 1178 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1179 if (!r) 1180 r = dqm_debugfs_execute_queues(dev->dqm); 1181 1182 return r; 1183 } 1184 1185 #endif 1186
Indexes created Mon Sep 22 10:09:38 GMT 2025