| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v10.c | 349 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; local in function:kgd_hiq_mqd_load
365 r = amdgpu_ring_alloc(kiq_ring, 7);
371 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
372 amdgpu_ring_write(kiq_ring,
382 amdgpu_ring_write(kiq_ring,
384 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
385 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
386 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
387 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
388 amdgpu_ring_commit(kiq_ring);
[all...] |
| amdgpu_amdkfd_gfx_v9.c | 337 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; local in function:kgd_gfx_v9_hiq_mqd_load
353 r = amdgpu_ring_alloc(kiq_ring, 7);
359 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
360 amdgpu_ring_write(kiq_ring,
370 amdgpu_ring_write(kiq_ring,
372 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
373 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
374 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
375 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
376 amdgpu_ring_commit(kiq_ring);
[all...] |
| amdgpu_gfx.c | 472 struct amdgpu_ring *kiq_ring = &kiq->ring; local in function:amdgpu_gfx_disable_kcq
478 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
483 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
486 return amdgpu_ring_test_ring(kiq_ring);
492 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; local in function:amdgpu_gfx_enable_kcq
514 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
515 kiq_ring->queue);
517 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
525 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask)
[all...] |
| amdgpu_gfx_v10_0.c | 268 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
270 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
271 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
273 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
274 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
275 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
276 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
277 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
278 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
281 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3158 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; local in function:gfx_v10_0_kiq_enable_kgq
3781 struct amdgpu_ring *kiq_ring = &kiq->ring; local in function:gfx_v10_0_kiq_disable_kgq
4641 struct amdgpu_ring *kiq_ring = &kiq->ring; local in function:gfx_v10_0_ring_preempt_ib
[all...] |
| amdgpu_gfx_v8_0.c | 4352 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; local in function:gfx_v8_0_kiq_kcq_enable
4371 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4377 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4378 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4379 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4380 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4381 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4382 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4383 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4384 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 *
4830 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; local in function:gfx_v8_0_kcq_disable
[all...] |
