| /src/sys/external/isc/libsodium/dist/test/default/ |
| pwhash_argon2i.c | 19 unsigned int lanes; member in struct:tv::__anon0e6d55c50108
116 unsigned int lanes; member in struct:tv2::__anon0e6d55c50208
|
| pwhash_argon2id.c | 19 unsigned int lanes; member in struct:tv::__anondc18eda90108
116 unsigned int lanes; member in struct:tv2::__anondc18eda90208
|
| /src/sys/arch/mac68k/nubus/ |
| nubus.c | 108 u_int8_t lanes; local in function:nubus_attach
139 lanes = fmtblock.bytelanes;
173 lanes, entry);
176 entry = nubus_adjust_ptr(lanes,
179 rsrcid = nubus_read_1(bst, bsh, lanes, entry);
322 * and X is a bitmask of the lanes to ignore. Hence, (X ^ Y) == 0
336 u_int8_t lanes; local in function:nubus_probe_slot
355 lanes = 0xf;
359 for (i = j; i > 0; i--, lanes--) {
361 lanes -= i
611 u_int8_t byte, lanes = fmt->bytelanes; local in function:nubus_find_rsrc
649 u_int8_t lanes = fmt->bytelanes; local in function:nubus_get_ind_data
673 u_int8_t lanes = fmt->bytelanes; local in function:nubus_get_c_string
705 u_int8_t lanes = fmt->bytelanes; local in function:nubus_get_smem_addr_rangelist
[all...] |
| /src/sys/arch/mips/rmi/ |
| rmixl_pcievar.h | 44 u_int lanes; member in struct:rmixl_pcie_lnkcfg
|
| rmixl_pcie.c | 588 u_int lanes; local in function:rmixl_pcie_errata
627 lanes = sc->sc_pcie_lnktab.cfg[0].lanes;
629 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) {
644 if (lanes == 4) {
|
| /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_pwhash/argon2/ |
| argon2-core.h | 103 uint32_t lanes; member in struct:Argon2_instance_t
147 * Other lanes : all already finished segments
151 * Other lanes : (SYNC_POINTS - 1) last segments
|
| argon2.h | 23 /* Minimum and maximum number of lanes (degree of parallelism) */
31 /* Number of synchronization points between lanes per pass */
156 *lanes.
181 uint32_t lanes; /* number of lanes */ member in struct:Argon2_Context
201 * @param parallelism Number of threads and compute lanes
222 * @param parallelism Number of threads and compute lanes
243 * @param parallelism Number of threads and compute lanes
262 * @param parallelism Number of threads and compute lanes
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| ior.h | 75 u8 lanes[4]; member in struct:nvkm_ior_func::__anonfa17732f0508
|
| /src/sys/arch/arm/nvidia/ |
| tegra_pcie.c | 429 uint32_t val, cfg, lanes; local in function:tegra_pcie_setup
449 lanes = 0;
457 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0)
459 lanes |= (val << (index << 3));
463 switch (lanes) {
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv770.c | 2032 u32 link_width_cntl, lanes, speed_cntl, tmp; local in function:rv770_pcie_gen2_enable
2060 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2063 link_width_cntl |= lanes | LC_RECONFIG_NOW |
|
| radeon_r600.c | 4457 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4473 switch (lanes) {
4497 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4549 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; local in function:r600_pcie_gen2_enable
4591 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4594 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| power_state.h | 93 unsigned int lanes; member in struct:PP_StatePcieBlock
|
| amdgpu_smu.h | 86 unsigned int lanes; member in struct:smu_state_pcie_block
|
| /src/sys/arch/powerpc/booke/pci/ |
| pq3pci.c | 757 u_int lanes = e500_truth_decode(cnl->cnl_instance, pordevsr, local in function:pq3pci_cpunode_attach
759 if (lanes == 0) {
763 snprintf(buf, sizeof(buf), "PCI-Express x%u", lanes);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_vbt_defs.h | 643 u8 lanes:4; member in struct:edp_fast_link_params
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 687 int lanes; member in struct:intel_vbt_data::__anon6c72b20e0a08
|
