1 /* 2 * Copyright 2015 Vishnu Patekar 3 * 4 * Vishnu Patekar <vishnupatekar0510 (at) gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45 #include <dt-bindings/interrupt-controller/arm-gic.h> 46 47 #include <dt-bindings/clock/sun8i-a83t-ccu.h> 48 #include <dt-bindings/clock/sun8i-de2.h> 49 #include <dt-bindings/clock/sun8i-r-ccu.h> 50 #include <dt-bindings/reset/sun8i-a83t-ccu.h> 51 #include <dt-bindings/reset/sun8i-de2.h> 52 #include <dt-bindings/reset/sun8i-r-ccu.h> 53 #include <dt-bindings/thermal/thermal.h> 54 55 / { 56 interrupt-parent = <&gic>; 57 #address-cells = <1>; 58 #size-cells = <1>; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 cpu0: cpu@0 { 65 compatible = "arm,cortex-a7"; 66 device_type = "cpu"; 67 clocks = <&ccu CLK_C0CPUX>; 68 operating-points-v2 = <&cpu0_opp_table>; 69 cci-control-port = <&cci_control0>; 70 enable-method = "allwinner,sun8i-a83t-smp"; 71 reg = <0>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu1: cpu@1 { 76 compatible = "arm,cortex-a7"; 77 device_type = "cpu"; 78 clocks = <&ccu CLK_C0CPUX>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 cci-control-port = <&cci_control0>; 81 enable-method = "allwinner,sun8i-a83t-smp"; 82 reg = <1>; 83 #cooling-cells = <2>; 84 }; 85 86 cpu2: cpu@2 { 87 compatible = "arm,cortex-a7"; 88 device_type = "cpu"; 89 clocks = <&ccu CLK_C0CPUX>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 cci-control-port = <&cci_control0>; 92 enable-method = "allwinner,sun8i-a83t-smp"; 93 reg = <2>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu3: cpu@3 { 98 compatible = "arm,cortex-a7"; 99 device_type = "cpu"; 100 clocks = <&ccu CLK_C0CPUX>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 cci-control-port = <&cci_control0>; 103 enable-method = "allwinner,sun8i-a83t-smp"; 104 reg = <3>; 105 #cooling-cells = <2>; 106 }; 107 108 cpu100: cpu@100 { 109 compatible = "arm,cortex-a7"; 110 device_type = "cpu"; 111 clocks = <&ccu CLK_C1CPUX>; 112 operating-points-v2 = <&cpu1_opp_table>; 113 cci-control-port = <&cci_control1>; 114 enable-method = "allwinner,sun8i-a83t-smp"; 115 reg = <0x100>; 116 #cooling-cells = <2>; 117 }; 118 119 cpu101: cpu@101 { 120 compatible = "arm,cortex-a7"; 121 device_type = "cpu"; 122 clocks = <&ccu CLK_C1CPUX>; 123 operating-points-v2 = <&cpu1_opp_table>; 124 cci-control-port = <&cci_control1>; 125 enable-method = "allwinner,sun8i-a83t-smp"; 126 reg = <0x101>; 127 #cooling-cells = <2>; 128 }; 129 130 cpu102: cpu@102 { 131 compatible = "arm,cortex-a7"; 132 device_type = "cpu"; 133 clocks = <&ccu CLK_C1CPUX>; 134 operating-points-v2 = <&cpu1_opp_table>; 135 cci-control-port = <&cci_control1>; 136 enable-method = "allwinner,sun8i-a83t-smp"; 137 reg = <0x102>; 138 #cooling-cells = <2>; 139 }; 140 141 cpu103: cpu@103 { 142 compatible = "arm,cortex-a7"; 143 device_type = "cpu"; 144 clocks = <&ccu CLK_C1CPUX>; 145 operating-points-v2 = <&cpu1_opp_table>; 146 cci-control-port = <&cci_control1>; 147 enable-method = "allwinner,sun8i-a83t-smp"; 148 reg = <0x103>; 149 #cooling-cells = <2>; 150 }; 151 }; 152 153 timer { 154 compatible = "arm,armv7-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 159 }; 160 161 clocks { 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges; 165 166 /* TODO: PRCM block has a mux for this. */ 167 osc24M: osc24M_clk { 168 #clock-cells = <0>; 169 compatible = "fixed-clock"; 170 clock-frequency = <24000000>; 171 clock-accuracy = <50000>; 172 clock-output-names = "osc24M"; 173 }; 174 175 /* 176 * This is called "internal OSC" in some places. 177 * It is an internal RC-based oscillator. 178 * TODO: Its controls are in the PRCM block. 179 */ 180 osc16M: osc16M_clk { 181 #clock-cells = <0>; 182 compatible = "fixed-clock"; 183 clock-frequency = <16000000>; 184 clock-output-names = "osc16M"; 185 }; 186 187 osc16Md512: osc16Md512_clk { 188 #clock-cells = <0>; 189 compatible = "fixed-factor-clock"; 190 clock-div = <512>; 191 clock-mult = <1>; 192 clocks = <&osc16M>; 193 clock-output-names = "osc16M-d512"; 194 }; 195 }; 196 197 de: display-engine { 198 compatible = "allwinner,sun8i-a83t-display-engine"; 199 allwinner,pipelines = <&mixer0>, <&mixer1>; 200 status = "disabled"; 201 }; 202 203 cpu0_opp_table: opp_table0 { 204 compatible = "operating-points-v2"; 205 opp-shared; 206 207 opp-480000000 { 208 opp-hz = /bits/ 64 <480000000>; 209 opp-microvolt = <840000>; 210 clock-latency-ns = <244144>; /* 8 32k periods */ 211 }; 212 213 opp-600000000 { 214 opp-hz = /bits/ 64 <600000000>; 215 opp-microvolt = <840000>; 216 clock-latency-ns = <244144>; /* 8 32k periods */ 217 }; 218 219 opp-720000000 { 220 opp-hz = /bits/ 64 <720000000>; 221 opp-microvolt = <840000>; 222 clock-latency-ns = <244144>; /* 8 32k periods */ 223 }; 224 225 opp-864000000 { 226 opp-hz = /bits/ 64 <864000000>; 227 opp-microvolt = <840000>; 228 clock-latency-ns = <244144>; /* 8 32k periods */ 229 }; 230 231 opp-912000000 { 232 opp-hz = /bits/ 64 <912000000>; 233 opp-microvolt = <840000>; 234 clock-latency-ns = <244144>; /* 8 32k periods */ 235 }; 236 237 opp-1008000000 { 238 opp-hz = /bits/ 64 <1008000000>; 239 opp-microvolt = <840000>; 240 clock-latency-ns = <244144>; /* 8 32k periods */ 241 }; 242 243 opp-1128000000 { 244 opp-hz = /bits/ 64 <1128000000>; 245 opp-microvolt = <840000>; 246 clock-latency-ns = <244144>; /* 8 32k periods */ 247 }; 248 249 opp-1200000000 { 250 opp-hz = /bits/ 64 <1200000000>; 251 opp-microvolt = <840000>; 252 clock-latency-ns = <244144>; /* 8 32k periods */ 253 }; 254 }; 255 256 cpu1_opp_table: opp_table1 { 257 compatible = "operating-points-v2"; 258 opp-shared; 259 260 opp-480000000 { 261 opp-hz = /bits/ 64 <480000000>; 262 opp-microvolt = <840000>; 263 clock-latency-ns = <244144>; /* 8 32k periods */ 264 }; 265 266 opp-600000000 { 267 opp-hz = /bits/ 64 <600000000>; 268 opp-microvolt = <840000>; 269 clock-latency-ns = <244144>; /* 8 32k periods */ 270 }; 271 272 opp-720000000 { 273 opp-hz = /bits/ 64 <720000000>; 274 opp-microvolt = <840000>; 275 clock-latency-ns = <244144>; /* 8 32k periods */ 276 }; 277 278 opp-864000000 { 279 opp-hz = /bits/ 64 <864000000>; 280 opp-microvolt = <840000>; 281 clock-latency-ns = <244144>; /* 8 32k periods */ 282 }; 283 284 opp-912000000 { 285 opp-hz = /bits/ 64 <912000000>; 286 opp-microvolt = <840000>; 287 clock-latency-ns = <244144>; /* 8 32k periods */ 288 }; 289 290 opp-1008000000 { 291 opp-hz = /bits/ 64 <1008000000>; 292 opp-microvolt = <840000>; 293 clock-latency-ns = <244144>; /* 8 32k periods */ 294 }; 295 296 opp-1128000000 { 297 opp-hz = /bits/ 64 <1128000000>; 298 opp-microvolt = <840000>; 299 clock-latency-ns = <244144>; /* 8 32k periods */ 300 }; 301 302 opp-1200000000 { 303 opp-hz = /bits/ 64 <1200000000>; 304 opp-microvolt = <840000>; 305 clock-latency-ns = <244144>; /* 8 32k periods */ 306 }; 307 }; 308 309 soc { 310 compatible = "simple-bus"; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges; 314 315 display_clocks: clock@1000000 { 316 compatible = "allwinner,sun8i-a83t-de2-clk"; 317 reg = <0x01000000 0x10000>; 318 clocks = <&ccu CLK_BUS_DE>, 319 <&ccu CLK_PLL_DE>; 320 clock-names = "bus", 321 "mod"; 322 resets = <&ccu RST_BUS_DE>; 323 #clock-cells = <1>; 324 #reset-cells = <1>; 325 }; 326 327 rotate: rotate@1020000 { 328 compatible = "allwinner,sun8i-a83t-de2-rotate"; 329 reg = <0x1020000 0x10000>; 330 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&display_clocks CLK_BUS_ROT>, 332 <&display_clocks CLK_ROT>; 333 clock-names = "bus", 334 "mod"; 335 resets = <&display_clocks RST_ROT>; 336 }; 337 338 mixer0: mixer@1100000 { 339 compatible = "allwinner,sun8i-a83t-de2-mixer-0"; 340 reg = <0x01100000 0x100000>; 341 clocks = <&display_clocks CLK_BUS_MIXER0>, 342 <&display_clocks CLK_MIXER0>; 343 clock-names = "bus", 344 "mod"; 345 resets = <&display_clocks RST_MIXER0>; 346 347 ports { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 mixer0_out: port@1 { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 reg = <1>; 355 356 mixer0_out_tcon0: endpoint@0 { 357 reg = <0>; 358 remote-endpoint = <&tcon0_in_mixer0>; 359 }; 360 361 mixer0_out_tcon1: endpoint@1 { 362 reg = <1>; 363 remote-endpoint = <&tcon1_in_mixer0>; 364 }; 365 }; 366 }; 367 }; 368 369 mixer1: mixer@1200000 { 370 compatible = "allwinner,sun8i-a83t-de2-mixer-1"; 371 reg = <0x01200000 0x100000>; 372 clocks = <&display_clocks CLK_BUS_MIXER1>, 373 <&display_clocks CLK_MIXER1>; 374 clock-names = "bus", 375 "mod"; 376 resets = <&display_clocks RST_WB>; 377 378 ports { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 mixer1_out: port@1 { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 reg = <1>; 386 387 mixer1_out_tcon0: endpoint@0 { 388 reg = <0>; 389 remote-endpoint = <&tcon0_in_mixer1>; 390 }; 391 392 mixer1_out_tcon1: endpoint@1 { 393 reg = <1>; 394 remote-endpoint = <&tcon1_in_mixer1>; 395 }; 396 }; 397 }; 398 }; 399 400 cpucfg@1700000 { 401 compatible = "allwinner,sun8i-a83t-cpucfg"; 402 reg = <0x01700000 0x400>; 403 }; 404 405 cci@1790000 { 406 compatible = "arm,cci-400"; 407 #address-cells = <1>; 408 #size-cells = <1>; 409 reg = <0x01790000 0x10000>; 410 ranges = <0x0 0x01790000 0x10000>; 411 412 cci_control0: slave-if@4000 { 413 compatible = "arm,cci-400-ctrl-if"; 414 interface-type = "ace"; 415 reg = <0x4000 0x1000>; 416 }; 417 418 cci_control1: slave-if@5000 { 419 compatible = "arm,cci-400-ctrl-if"; 420 interface-type = "ace"; 421 reg = <0x5000 0x1000>; 422 }; 423 424 pmu@9000 { 425 compatible = "arm,cci-400-pmu,r1"; 426 reg = <0x9000 0x5000>; 427 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 435 }; 436 }; 437 438 syscon: syscon@1c00000 { 439 compatible = "allwinner,sun8i-a83t-system-controller", 440 "syscon"; 441 reg = <0x01c00000 0x1000>; 442 }; 443 444 dma: dma-controller@1c02000 { 445 compatible = "allwinner,sun8i-a83t-dma"; 446 reg = <0x01c02000 0x1000>; 447 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&ccu CLK_BUS_DMA>; 449 resets = <&ccu RST_BUS_DMA>; 450 #dma-cells = <1>; 451 }; 452 453 tcon0: lcd-controller@1c0c000 { 454 compatible = "allwinner,sun8i-a83t-tcon-lcd"; 455 reg = <0x01c0c000 0x1000>; 456 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 458 clock-names = "ahb", "tcon-ch0"; 459 clock-output-names = "tcon-pixel-clock"; 460 #clock-cells = <0>; 461 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 462 reset-names = "lcd", "lvds"; 463 464 ports { 465 #address-cells = <1>; 466 #size-cells = <0>; 467 468 tcon0_in: port@0 { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 reg = <0>; 472 473 tcon0_in_mixer0: endpoint@0 { 474 reg = <0>; 475 remote-endpoint = <&mixer0_out_tcon0>; 476 }; 477 478 tcon0_in_mixer1: endpoint@1 { 479 reg = <1>; 480 remote-endpoint = <&mixer1_out_tcon0>; 481 }; 482 }; 483 484 tcon0_out: port@1 { 485 reg = <1>; 486 }; 487 }; 488 }; 489 490 tcon1: lcd-controller@1c0d000 { 491 compatible = "allwinner,sun8i-a83t-tcon-tv"; 492 reg = <0x01c0d000 0x1000>; 493 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 495 clock-names = "ahb", "tcon-ch1"; 496 resets = <&ccu RST_BUS_TCON1>; 497 reset-names = "lcd"; 498 499 ports { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 503 tcon1_in: port@0 { 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <0>; 507 508 tcon1_in_mixer0: endpoint@0 { 509 reg = <0>; 510 remote-endpoint = <&mixer0_out_tcon1>; 511 }; 512 513 tcon1_in_mixer1: endpoint@1 { 514 reg = <1>; 515 remote-endpoint = <&mixer1_out_tcon1>; 516 }; 517 }; 518 519 tcon1_out: port@1 { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 reg = <1>; 523 524 tcon1_out_hdmi: endpoint@1 { 525 reg = <1>; 526 remote-endpoint = <&hdmi_in_tcon1>; 527 }; 528 }; 529 }; 530 }; 531 532 mmc0: mmc@1c0f000 { 533 compatible = "allwinner,sun8i-a83t-mmc", 534 "allwinner,sun7i-a20-mmc"; 535 reg = <0x01c0f000 0x1000>; 536 clocks = <&ccu CLK_BUS_MMC0>, 537 <&ccu CLK_MMC0>, 538 <&ccu CLK_MMC0_OUTPUT>, 539 <&ccu CLK_MMC0_SAMPLE>; 540 clock-names = "ahb", 541 "mmc", 542 "output", 543 "sample"; 544 resets = <&ccu RST_BUS_MMC0>; 545 reset-names = "ahb"; 546 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 547 status = "disabled"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 }; 551 552 mmc1: mmc@1c10000 { 553 compatible = "allwinner,sun8i-a83t-mmc", 554 "allwinner,sun7i-a20-mmc"; 555 reg = <0x01c10000 0x1000>; 556 clocks = <&ccu CLK_BUS_MMC1>, 557 <&ccu CLK_MMC1>, 558 <&ccu CLK_MMC1_OUTPUT>, 559 <&ccu CLK_MMC1_SAMPLE>; 560 clock-names = "ahb", 561 "mmc", 562 "output", 563 "sample"; 564 resets = <&ccu RST_BUS_MMC1>; 565 reset-names = "ahb"; 566 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&mmc1_pins>; 569 status = "disabled"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 }; 573 574 mmc2: mmc@1c11000 { 575 compatible = "allwinner,sun8i-a83t-emmc"; 576 reg = <0x01c11000 0x1000>; 577 clocks = <&ccu CLK_BUS_MMC2>, 578 <&ccu CLK_MMC2>, 579 <&ccu CLK_MMC2_OUTPUT>, 580 <&ccu CLK_MMC2_SAMPLE>; 581 clock-names = "ahb", 582 "mmc", 583 "output", 584 "sample"; 585 resets = <&ccu RST_BUS_MMC2>; 586 reset-names = "ahb"; 587 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 588 status = "disabled"; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 }; 592 593 sid: eeprom@1c14000 { 594 compatible = "allwinner,sun8i-a83t-sid"; 595 reg = <0x1c14000 0x400>; 596 #address-cells = <1>; 597 #size-cells = <1>; 598 599 ths_calibration: thermal-sensor-calibration@34 { 600 reg = <0x34 8>; 601 }; 602 }; 603 604 crypto: crypto@1c15000 { 605 compatible = "allwinner,sun8i-a83t-crypto"; 606 reg = <0x01c15000 0x1000>; 607 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 608 resets = <&ccu RST_BUS_SS>; 609 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; 610 clock-names = "bus", "mod"; 611 }; 612 613 msgbox: mailbox@1c17000 { 614 compatible = "allwinner,sun8i-a83t-msgbox", 615 "allwinner,sun6i-a31-msgbox"; 616 reg = <0x01c17000 0x1000>; 617 clocks = <&ccu CLK_BUS_MSGBOX>; 618 resets = <&ccu RST_BUS_MSGBOX>; 619 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 620 #mbox-cells = <1>; 621 }; 622 623 usb_otg: usb@1c19000 { 624 compatible = "allwinner,sun8i-a83t-musb", 625 "allwinner,sun8i-a33-musb"; 626 reg = <0x01c19000 0x0400>; 627 clocks = <&ccu CLK_BUS_OTG>; 628 resets = <&ccu RST_BUS_OTG>; 629 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 630 interrupt-names = "mc"; 631 phys = <&usbphy 0>; 632 phy-names = "usb"; 633 extcon = <&usbphy 0>; 634 dr_mode = "otg"; 635 status = "disabled"; 636 }; 637 638 usbphy: phy@1c19400 { 639 compatible = "allwinner,sun8i-a83t-usb-phy"; 640 reg = <0x01c19400 0x10>, 641 <0x01c1a800 0x14>, 642 <0x01c1b800 0x14>; 643 reg-names = "phy_ctrl", 644 "pmu1", 645 "pmu2"; 646 clocks = <&ccu CLK_USB_PHY0>, 647 <&ccu CLK_USB_PHY1>, 648 <&ccu CLK_USB_HSIC>, 649 <&ccu CLK_USB_HSIC_12M>; 650 clock-names = "usb0_phy", 651 "usb1_phy", 652 "usb2_phy", 653 "usb2_hsic_12M"; 654 resets = <&ccu RST_USB_PHY0>, 655 <&ccu RST_USB_PHY1>, 656 <&ccu RST_USB_HSIC>; 657 reset-names = "usb0_reset", 658 "usb1_reset", 659 "usb2_reset"; 660 status = "disabled"; 661 #phy-cells = <1>; 662 }; 663 664 ehci0: usb@1c1a000 { 665 compatible = "allwinner,sun8i-a83t-ehci", 666 "generic-ehci"; 667 reg = <0x01c1a000 0x100>; 668 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&ccu CLK_BUS_EHCI0>; 670 resets = <&ccu RST_BUS_EHCI0>; 671 phys = <&usbphy 1>; 672 phy-names = "usb"; 673 status = "disabled"; 674 }; 675 676 ohci0: usb@1c1a400 { 677 compatible = "allwinner,sun8i-a83t-ohci", 678 "generic-ohci"; 679 reg = <0x01c1a400 0x100>; 680 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; 682 resets = <&ccu RST_BUS_OHCI0>; 683 phys = <&usbphy 1>; 684 phy-names = "usb"; 685 status = "disabled"; 686 }; 687 688 ehci1: usb@1c1b000 { 689 compatible = "allwinner,sun8i-a83t-ehci", 690 "generic-ehci"; 691 reg = <0x01c1b000 0x100>; 692 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&ccu CLK_BUS_EHCI1>; 694 resets = <&ccu RST_BUS_EHCI1>; 695 phys = <&usbphy 2>; 696 phy-names = "usb"; 697 status = "disabled"; 698 }; 699 700 ccu: clock@1c20000 { 701 compatible = "allwinner,sun8i-a83t-ccu"; 702 reg = <0x01c20000 0x400>; 703 clocks = <&osc24M>, <&osc16Md512>; 704 clock-names = "hosc", "losc"; 705 #clock-cells = <1>; 706 #reset-cells = <1>; 707 }; 708 709 pio: pinctrl@1c20800 { 710 compatible = "allwinner,sun8i-a83t-pinctrl"; 711 interrupt-parent = <&r_intc>; 712 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 715 reg = <0x01c20800 0x400>; 716 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; 717 clock-names = "apb", "hosc", "losc"; 718 gpio-controller; 719 interrupt-controller; 720 #interrupt-cells = <3>; 721 #gpio-cells = <3>; 722 723 /omit-if-no-ref/ 724 csi_8bit_parallel_pins: csi-8bit-parallel-pins { 725 pins = "PE0", "PE2", "PE3", "PE6", "PE7", 726 "PE8", "PE9", "PE10", "PE11", 727 "PE12", "PE13"; 728 function = "csi"; 729 }; 730 731 /omit-if-no-ref/ 732 csi_mclk_pin: csi-mclk-pin { 733 pins = "PE1"; 734 function = "csi"; 735 }; 736 737 emac_rgmii_pins: emac-rgmii-pins { 738 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 739 "PD11", "PD12", "PD13", "PD14", "PD18", 740 "PD19", "PD21", "PD22", "PD23"; 741 function = "gmac"; 742 /* 743 * data lines in RGMII mode use DDR mode 744 * and need a higher signal drive strength 745 */ 746 drive-strength = <40>; 747 }; 748 749 hdmi_pins: hdmi-pins { 750 pins = "PH6", "PH7", "PH8"; 751 function = "hdmi"; 752 }; 753 754 i2c0_pins: i2c0-pins { 755 pins = "PH0", "PH1"; 756 function = "i2c0"; 757 }; 758 759 i2c1_pins: i2c1-pins { 760 pins = "PH2", "PH3"; 761 function = "i2c1"; 762 }; 763 764 /omit-if-no-ref/ 765 i2c2_pe_pins: i2c2-pe-pins { 766 pins = "PE14", "PE15"; 767 function = "i2c2"; 768 }; 769 770 i2c2_ph_pins: i2c2-ph-pins { 771 pins = "PH4", "PH5"; 772 function = "i2c2"; 773 }; 774 775 i2s1_pins: i2s1-pins { 776 /* I2S1 does not have external MCLK pin */ 777 pins = "PG10", "PG11", "PG12", "PG13"; 778 function = "i2s1"; 779 }; 780 781 lcd_lvds_pins: lcd-lvds-pins { 782 pins = "PD18", "PD19", "PD20", "PD21", "PD22", 783 "PD23", "PD24", "PD25", "PD26", "PD27"; 784 function = "lvds0"; 785 }; 786 787 mmc0_pins: mmc0-pins { 788 pins = "PF0", "PF1", "PF2", 789 "PF3", "PF4", "PF5"; 790 function = "mmc0"; 791 drive-strength = <30>; 792 bias-pull-up; 793 }; 794 795 mmc1_pins: mmc1-pins { 796 pins = "PG0", "PG1", "PG2", 797 "PG3", "PG4", "PG5"; 798 function = "mmc1"; 799 drive-strength = <30>; 800 bias-pull-up; 801 }; 802 803 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { 804 pins = "PC5", "PC6", "PC8", "PC9", 805 "PC10", "PC11", "PC12", "PC13", 806 "PC14", "PC15", "PC16"; 807 function = "mmc2"; 808 drive-strength = <30>; 809 bias-pull-up; 810 }; 811 812 pwm_pin: pwm-pin { 813 pins = "PD28"; 814 function = "pwm"; 815 }; 816 817 spdif_tx_pin: spdif-tx-pin { 818 pins = "PE18"; 819 function = "spdif"; 820 }; 821 822 uart0_pb_pins: uart0-pb-pins { 823 pins = "PB9", "PB10"; 824 function = "uart0"; 825 }; 826 827 uart0_pf_pins: uart0-pf-pins { 828 pins = "PF2", "PF4"; 829 function = "uart0"; 830 }; 831 832 uart1_pins: uart1-pins { 833 pins = "PG6", "PG7"; 834 function = "uart1"; 835 }; 836 837 uart1_rts_cts_pins: uart1-rts-cts-pins { 838 pins = "PG8", "PG9"; 839 function = "uart1"; 840 }; 841 842 /omit-if-no-ref/ 843 uart2_pb_pins: uart2-pb-pins { 844 pins = "PB0", "PB1"; 845 function = "uart2"; 846 }; 847 }; 848 849 timer@1c20c00 { 850 compatible = "allwinner,sun8i-a23-timer"; 851 reg = <0x01c20c00 0xa0>; 852 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&osc24M>; 855 }; 856 857 watchdog@1c20ca0 { 858 compatible = "allwinner,sun6i-a31-wdt"; 859 reg = <0x01c20ca0 0x20>; 860 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&osc24M>; 862 }; 863 864 spdif: spdif@1c21000 { 865 #sound-dai-cells = <0>; 866 compatible = "allwinner,sun8i-a83t-spdif", 867 "allwinner,sun8i-h3-spdif"; 868 reg = <0x01c21000 0x400>; 869 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 871 resets = <&ccu RST_BUS_SPDIF>; 872 clock-names = "apb", "spdif"; 873 dmas = <&dma 2>; 874 dma-names = "tx"; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&spdif_tx_pin>; 877 status = "disabled"; 878 }; 879 880 i2s0: i2s@1c22000 { 881 #sound-dai-cells = <0>; 882 compatible = "allwinner,sun8i-a83t-i2s"; 883 reg = <0x01c22000 0x400>; 884 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 886 clock-names = "apb", "mod"; 887 dmas = <&dma 3>, <&dma 3>; 888 resets = <&ccu RST_BUS_I2S0>; 889 dma-names = "rx", "tx"; 890 status = "disabled"; 891 }; 892 893 i2s1: i2s@1c22400 { 894 #sound-dai-cells = <0>; 895 compatible = "allwinner,sun8i-a83t-i2s"; 896 reg = <0x01c22400 0x400>; 897 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 899 clock-names = "apb", "mod"; 900 dmas = <&dma 4>, <&dma 4>; 901 resets = <&ccu RST_BUS_I2S1>; 902 dma-names = "rx", "tx"; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&i2s1_pins>; 905 status = "disabled"; 906 }; 907 908 i2s2: i2s@1c22800 { 909 #sound-dai-cells = <0>; 910 compatible = "allwinner,sun8i-a83t-i2s"; 911 reg = <0x01c22800 0x400>; 912 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 914 clock-names = "apb", "mod"; 915 dmas = <&dma 27>; 916 resets = <&ccu RST_BUS_I2S2>; 917 dma-names = "tx"; 918 status = "disabled"; 919 }; 920 921 pwm: pwm@1c21400 { 922 compatible = "allwinner,sun8i-a83t-pwm", 923 "allwinner,sun8i-h3-pwm"; 924 reg = <0x01c21400 0x400>; 925 clocks = <&osc24M>; 926 #pwm-cells = <3>; 927 status = "disabled"; 928 }; 929 930 uart0: serial@1c28000 { 931 compatible = "snps,dw-apb-uart"; 932 reg = <0x01c28000 0x400>; 933 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 934 reg-shift = <2>; 935 reg-io-width = <4>; 936 clocks = <&ccu CLK_BUS_UART0>; 937 resets = <&ccu RST_BUS_UART0>; 938 status = "disabled"; 939 }; 940 941 uart1: serial@1c28400 { 942 compatible = "snps,dw-apb-uart"; 943 reg = <0x01c28400 0x400>; 944 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 945 reg-shift = <2>; 946 reg-io-width = <4>; 947 clocks = <&ccu CLK_BUS_UART1>; 948 resets = <&ccu RST_BUS_UART1>; 949 status = "disabled"; 950 }; 951 952 uart2: serial@1c28800 { 953 compatible = "snps,dw-apb-uart"; 954 reg = <0x01c28800 0x400>; 955 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 956 reg-shift = <2>; 957 reg-io-width = <4>; 958 clocks = <&ccu CLK_BUS_UART2>; 959 resets = <&ccu RST_BUS_UART2>; 960 status = "disabled"; 961 }; 962 963 uart3: serial@1c28c00 { 964 compatible = "snps,dw-apb-uart"; 965 reg = <0x01c28c00 0x400>; 966 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 967 reg-shift = <2>; 968 reg-io-width = <4>; 969 clocks = <&ccu CLK_BUS_UART3>; 970 resets = <&ccu RST_BUS_UART3>; 971 status = "disabled"; 972 }; 973 974 uart4: serial@1c29000 { 975 compatible = "snps,dw-apb-uart"; 976 reg = <0x01c29000 0x400>; 977 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 978 reg-shift = <2>; 979 reg-io-width = <4>; 980 clocks = <&ccu CLK_BUS_UART4>; 981 resets = <&ccu RST_BUS_UART4>; 982 status = "disabled"; 983 }; 984 985 i2c0: i2c@1c2ac00 { 986 compatible = "allwinner,sun8i-a83t-i2c", 987 "allwinner,sun6i-a31-i2c"; 988 reg = <0x01c2ac00 0x400>; 989 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&ccu CLK_BUS_I2C0>; 991 resets = <&ccu RST_BUS_I2C0>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&i2c0_pins>; 994 status = "disabled"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 }; 998 999 i2c1: i2c@1c2b000 { 1000 compatible = "allwinner,sun8i-a83t-i2c", 1001 "allwinner,sun6i-a31-i2c"; 1002 reg = <0x01c2b000 0x400>; 1003 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&ccu CLK_BUS_I2C1>; 1005 resets = <&ccu RST_BUS_I2C1>; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&i2c1_pins>; 1008 status = "disabled"; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 }; 1012 1013 i2c2: i2c@1c2b400 { 1014 compatible = "allwinner,sun8i-a83t-i2c", 1015 "allwinner,sun6i-a31-i2c"; 1016 reg = <0x01c2b400 0x400>; 1017 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&ccu CLK_BUS_I2C2>; 1019 resets = <&ccu RST_BUS_I2C2>; 1020 status = "disabled"; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 }; 1024 1025 emac: ethernet@1c30000 { 1026 compatible = "allwinner,sun8i-a83t-emac"; 1027 syscon = <&syscon>; 1028 reg = <0x01c30000 0x104>; 1029 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "macirq"; 1031 clocks = <&ccu CLK_BUS_EMAC>; 1032 clock-names = "stmmaceth"; 1033 resets = <&ccu RST_BUS_EMAC>; 1034 reset-names = "stmmaceth"; 1035 status = "disabled"; 1036 1037 mdio: mdio { 1038 compatible = "snps,dwmac-mdio"; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 }; 1042 }; 1043 1044 gic: interrupt-controller@1c81000 { 1045 compatible = "arm,gic-400"; 1046 reg = <0x01c81000 0x1000>, 1047 <0x01c82000 0x2000>, 1048 <0x01c84000 0x2000>, 1049 <0x01c86000 0x2000>; 1050 interrupt-controller; 1051 #interrupt-cells = <3>; 1052 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1053 }; 1054 1055 csi: camera@1cb0000 { 1056 compatible = "allwinner,sun8i-a83t-csi"; 1057 reg = <0x01cb0000 0x1000>; 1058 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&ccu CLK_BUS_CSI>, 1060 <&ccu CLK_CSI_SCLK>, 1061 <&ccu CLK_DRAM_CSI>; 1062 clock-names = "bus", "mod", "ram"; 1063 resets = <&ccu RST_BUS_CSI>; 1064 status = "disabled"; 1065 }; 1066 1067 hdmi: hdmi@1ee0000 { 1068 compatible = "allwinner,sun8i-a83t-dw-hdmi"; 1069 reg = <0x01ee0000 0x10000>; 1070 reg-io-width = <1>; 1071 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 1073 <&ccu CLK_HDMI>; 1074 clock-names = "iahb", "isfr", "tmds"; 1075 resets = <&ccu RST_BUS_HDMI1>; 1076 reset-names = "ctrl"; 1077 phys = <&hdmi_phy>; 1078 phy-names = "phy"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&hdmi_pins>; 1081 status = "disabled"; 1082 1083 ports { 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 hdmi_in: port@0 { 1088 reg = <0>; 1089 1090 hdmi_in_tcon1: endpoint { 1091 remote-endpoint = <&tcon1_out_hdmi>; 1092 }; 1093 }; 1094 1095 hdmi_out: port@1 { 1096 reg = <1>; 1097 }; 1098 }; 1099 }; 1100 1101 hdmi_phy: hdmi-phy@1ef0000 { 1102 compatible = "allwinner,sun8i-a83t-hdmi-phy"; 1103 reg = <0x01ef0000 0x10000>; 1104 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 1105 clock-names = "bus", "mod"; 1106 resets = <&ccu RST_BUS_HDMI0>; 1107 reset-names = "phy"; 1108 #phy-cells = <0>; 1109 }; 1110 1111 r_intc: interrupt-controller@1f00c00 { 1112 compatible = "allwinner,sun8i-a83t-r-intc", 1113 "allwinner,sun6i-a31-r-intc"; 1114 interrupt-controller; 1115 #interrupt-cells = <3>; 1116 reg = <0x01f00c00 0x400>; 1117 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1118 }; 1119 1120 r_ccu: clock@1f01400 { 1121 compatible = "allwinner,sun8i-a83t-r-ccu"; 1122 reg = <0x01f01400 0x400>; 1123 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, 1124 <&ccu CLK_PLL_PERIPH>; 1125 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1126 #clock-cells = <1>; 1127 #reset-cells = <1>; 1128 }; 1129 1130 r_cpucfg@1f01c00 { 1131 compatible = "allwinner,sun8i-a83t-r-cpucfg"; 1132 reg = <0x1f01c00 0x400>; 1133 }; 1134 1135 r_cir: ir@1f02000 { 1136 compatible = "allwinner,sun8i-a83t-ir", 1137 "allwinner,sun6i-a31-ir"; 1138 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1139 clock-names = "apb", "ir"; 1140 resets = <&r_ccu RST_APB0_IR>; 1141 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1142 reg = <0x01f02000 0x400>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&r_cir_pin>; 1145 status = "disabled"; 1146 }; 1147 1148 r_lradc: lradc@1f03c00 { 1149 compatible = "allwinner,sun8i-a83t-r-lradc"; 1150 reg = <0x01f03c00 0x100>; 1151 interrupt-parent = <&r_intc>; 1152 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1153 status = "disabled"; 1154 }; 1155 1156 r_pio: pinctrl@1f02c00 { 1157 compatible = "allwinner,sun8i-a83t-r-pinctrl"; 1158 reg = <0x01f02c00 0x400>; 1159 interrupt-parent = <&r_intc>; 1160 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 1162 <&osc16Md512>; 1163 clock-names = "apb", "hosc", "losc"; 1164 gpio-controller; 1165 #gpio-cells = <3>; 1166 interrupt-controller; 1167 #interrupt-cells = <3>; 1168 1169 r_cir_pin: r-cir-pin { 1170 pins = "PL12"; 1171 function = "s_cir_rx"; 1172 }; 1173 1174 r_rsb_pins: r-rsb-pins { 1175 pins = "PL0", "PL1"; 1176 function = "s_rsb"; 1177 drive-strength = <20>; 1178 bias-pull-up; 1179 }; 1180 }; 1181 1182 r_rsb: rsb@1f03400 { 1183 compatible = "allwinner,sun8i-a83t-rsb", 1184 "allwinner,sun8i-a23-rsb"; 1185 reg = <0x01f03400 0x400>; 1186 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&r_ccu CLK_APB0_RSB>; 1188 clock-frequency = <3000000>; 1189 resets = <&r_ccu RST_APB0_RSB>; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&r_rsb_pins>; 1192 status = "disabled"; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 }; 1196 1197 ths: thermal-sensor@1f04000 { 1198 compatible = "allwinner,sun8i-a83t-ths"; 1199 reg = <0x01f04000 0x100>; 1200 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1201 nvmem-cells = <&ths_calibration>; 1202 nvmem-cell-names = "calibration"; 1203 #thermal-sensor-cells = <1>; 1204 }; 1205 }; 1206 1207 thermal-zones { 1208 cpu0_thermal: cpu0-thermal { 1209 polling-delay-passive = <0>; 1210 polling-delay = <0>; 1211 thermal-sensors = <&ths 0>; 1212 1213 trips { 1214 cpu0_hot: cpu-hot { 1215 temperature = <80000>; 1216 hysteresis = <2000>; 1217 type = "passive"; 1218 }; 1219 1220 cpu0_very_hot: cpu-very-hot { 1221 temperature = <100000>; 1222 hysteresis = <0>; 1223 type = "critical"; 1224 }; 1225 }; 1226 1227 cooling-maps { 1228 cpu-hot-limit { 1229 trip = <&cpu0_hot>; 1230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1234 }; 1235 }; 1236 }; 1237 1238 cpu1_thermal: cpu1-thermal { 1239 polling-delay-passive = <0>; 1240 polling-delay = <0>; 1241 thermal-sensors = <&ths 1>; 1242 1243 trips { 1244 cpu1_hot: cpu-hot { 1245 temperature = <80000>; 1246 hysteresis = <2000>; 1247 type = "passive"; 1248 }; 1249 1250 cpu1_very_hot: cpu-very-hot { 1251 temperature = <100000>; 1252 hysteresis = <0>; 1253 type = "critical"; 1254 }; 1255 }; 1256 1257 cooling-maps { 1258 cpu-hot-limit { 1259 trip = <&cpu1_hot>; 1260 cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1261 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1262 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1263 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1264 }; 1265 }; 1266 }; 1267 1268 gpu_thermal: gpu-thermal { 1269 polling-delay-passive = <0>; 1270 polling-delay = <0>; 1271 thermal-sensors = <&ths 2>; 1272 }; 1273 }; 1274 }; 1275
Indexes created Wed Oct 01 15:09:59 GMT 2025