1 /* $NetBSD: pci_subr.c,v 1.244 2024/04/19 21:24:00 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.244 2024/04/19 21:24:00 andvar Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #include <sys/kmem.h> 56 57 #define MALLOC(sz) kmem_alloc(sz, KM_SLEEP) 58 #define FREE(p, sz) kmem_free(p, sz) 59 60 #else 61 #include <pci.h> 62 #include <stdarg.h> 63 #include <stdbool.h> 64 #include <stdio.h> 65 #include <stdlib.h> 66 #include <string.h> 67 68 #define MALLOC(sz) malloc(sz) 69 #define FREE(p, sz) free(p) 70 71 #endif 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 #ifdef _KERNEL 76 #include <dev/pci/pcivar.h> 77 #else 78 #include <dev/pci/pci_verbose.h> 79 #include <dev/pci/pcidevs_data.h> 80 #endif 81 82 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 83 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 84 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 85 #define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b))) 86 87 #ifdef _KERNEL 88 /* 89 * Common routines used to match a compatible device by its PCI ID code. 90 */ 91 92 const struct device_compatible_entry * 93 pci_compatible_lookup_id(pcireg_t const id, 94 const struct device_compatible_entry *dce) 95 { 96 return device_compatible_lookup_id(id, PCI_COMPAT_EOL_VALUE, dce); 97 } 98 99 const struct device_compatible_entry * 100 pci_compatible_lookup(const struct pci_attach_args * const pa, 101 const struct device_compatible_entry * const dce) 102 { 103 return pci_compatible_lookup_id(pa->pa_id, dce); 104 } 105 106 const struct device_compatible_entry * 107 pci_compatible_lookup_subsys(const struct pci_attach_args * const pa, 108 const struct device_compatible_entry * const dce) 109 { 110 const pcireg_t subsysid = 111 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 112 113 return pci_compatible_lookup_id(subsysid, dce); 114 } 115 116 int 117 pci_compatible_match(const struct pci_attach_args * const pa, 118 const struct device_compatible_entry * const dce) 119 { 120 return pci_compatible_lookup(pa, dce) != NULL; 121 } 122 123 int 124 pci_compatible_match_subsys(const struct pci_attach_args * const pa, 125 const struct device_compatible_entry * const dce) 126 { 127 return pci_compatible_lookup_subsys(pa, dce) != NULL; 128 } 129 #endif /* _KERNEL */ 130 131 /* 132 * Descriptions of known PCI classes and subclasses. 133 * 134 * Subclasses are described in the same way as classes, but have a 135 * NULL subclass pointer. 136 */ 137 struct pci_class { 138 const char *name; 139 u_int val; /* as wide as pci_{,sub}class_t */ 140 const struct pci_class *subclasses; 141 }; 142 143 /* 144 * Class 0x00. 145 * Before rev. 2.0. 146 */ 147 static const struct pci_class pci_subclass_prehistoric[] = { 148 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 149 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 150 { NULL, 0, NULL, }, 151 }; 152 153 /* 154 * Class 0x01. 155 * Mass storage controller 156 */ 157 158 /* SCSI programming interface */ 159 static const struct pci_class pci_interface_scsi[] = { 160 { "vendor-specific", PCI_INTERFACE_SCSI_VND, NULL, }, 161 { "PQI storage", PCI_INTERFACE_SCSI_PQI_STORAGE, NULL, }, 162 { "PQI controller", PCI_INTERFACE_SCSI_PQI_CNTRL, NULL, }, 163 { "PQI storage and controller", PCI_INTERFACE_SCSI_PQI_STORAGE_CNTRL, 164 NULL, }, 165 { "NVME", PCI_INTERFACE_SCSI_NVME, NULL, }, 166 { NULL, 0, NULL, }, 167 }; 168 169 /* ATA programming interface */ 170 static const struct pci_class pci_interface_ata[] = { 171 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 172 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 173 { NULL, 0, NULL, }, 174 }; 175 176 /* SATA programming interface */ 177 static const struct pci_class pci_interface_sata[] = { 178 { "vendor-specific", PCI_INTERFACE_SATA_VND, NULL, }, 179 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 180 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 181 { NULL, 0, NULL, }, 182 }; 183 184 /* Flash programming interface */ 185 static const struct pci_class pci_interface_nvm[] = { 186 { "vendor-specific", PCI_INTERFACE_NVM_VND, NULL, }, 187 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 188 { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, }, 189 { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, }, 190 { NULL, 0, NULL, }, 191 }; 192 193 /* UFS programming interface */ 194 static const struct pci_class pci_interface_ufs[] = { 195 { "vendor-specific", PCI_INTERFACE_UFS_VND, NULL, }, 196 { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, }, 197 { NULL, 0, NULL, }, 198 }; 199 200 /* Subclasses */ 201 static const struct pci_class pci_subclass_mass_storage[] = { 202 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, 203 pci_interface_scsi }, 204 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 205 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 206 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 207 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 208 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 209 pci_interface_ata }, 210 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 211 pci_interface_sata }, 212 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 213 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 214 pci_interface_nvm, }, 215 { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS, 216 pci_interface_ufs, }, 217 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 218 { NULL, 0, NULL, }, 219 }; 220 221 /* 222 * Class 0x02. 223 * Network controller. 224 */ 225 static const struct pci_class pci_subclass_network[] = { 226 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 227 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 228 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 229 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 230 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 231 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 232 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 233 { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, }, 234 { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, }, 235 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 /* 240 * Class 0x03. 241 * Display controller. 242 */ 243 244 /* VGA programming interface */ 245 static const struct pci_class pci_interface_vga[] = { 246 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 247 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 248 { NULL, 0, NULL, }, 249 }; 250 /* Subclasses */ 251 static const struct pci_class pci_subclass_display[] = { 252 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 253 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 254 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 255 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 256 { NULL, 0, NULL, }, 257 }; 258 259 /* 260 * Class 0x04. 261 * Multimedia device. 262 */ 263 264 /* HD Audio programming interface */ 265 static const struct pci_class pci_interface_hda[] = { 266 { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, }, 267 { "HD Audio 1.0 + vendor-ext", PCI_INTERFACE_HDAUDIO_VND, NULL, }, 268 { NULL, 0, NULL, }, 269 }; 270 271 static const struct pci_class pci_subclass_multimedia[] = { 272 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 273 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 274 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 275 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, 276 pci_interface_hda, }, 277 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 278 { NULL, 0, NULL, }, 279 }; 280 281 /* 282 * Class 0x05. 283 * Memory controller. 284 */ 285 static const struct pci_class pci_subclass_memory[] = { 286 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 287 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 288 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 289 { NULL, 0, NULL, }, 290 }; 291 292 /* 293 * Class 0x06. 294 * Bridge device. 295 */ 296 297 /* PCI bridge programming interface */ 298 static const struct pci_class pci_interface_pcibridge[] = { 299 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 300 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 301 { NULL, 0, NULL, }, 302 }; 303 304 /* Semi-transparent PCI-to-PCI bridge programming interface */ 305 static const struct pci_class pci_interface_stpci[] = { 306 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 307 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 308 { NULL, 0, NULL, }, 309 }; 310 311 /* Advanced Switching programming interface */ 312 static const struct pci_class pci_interface_advsw[] = { 313 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 314 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 315 { NULL, 0, NULL, }, 316 }; 317 318 /* Subclasses */ 319 static const struct pci_class pci_subclass_bridge[] = { 320 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 321 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 322 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 323 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 324 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 325 pci_interface_pcibridge }, 326 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 327 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 328 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 329 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 330 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 331 pci_interface_stpci, }, 332 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 333 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 334 pci_interface_advsw, }, 335 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 336 { NULL, 0, NULL, }, 337 }; 338 339 /* 340 * Class 0x07. 341 * Simple communications controller. 342 */ 343 344 /* Serial controller programming interface */ 345 static const struct pci_class pci_interface_serial[] = { 346 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 347 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 348 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 349 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 350 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 351 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 352 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 353 { NULL, 0, NULL, }, 354 }; 355 356 /* Parallel controller programming interface */ 357 static const struct pci_class pci_interface_parallel[] = { 358 { "", PCI_INTERFACE_PARALLEL, NULL,}, 359 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 360 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 361 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 362 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 363 { NULL, 0, NULL,}, 364 }; 365 366 /* Modem programming interface */ 367 static const struct pci_class pci_interface_modem[] = { 368 { "", PCI_INTERFACE_MODEM, NULL,}, 369 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 370 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 371 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 372 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 373 { NULL, 0, NULL,}, 374 }; 375 376 /* Subclasses */ 377 static const struct pci_class pci_subclass_communications[] = { 378 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 379 pci_interface_serial, }, 380 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 381 pci_interface_parallel, }, 382 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 383 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 384 pci_interface_modem, }, 385 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 386 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 387 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 388 { NULL, 0, NULL,}, 389 }; 390 391 /* 392 * Class 0x08. 393 * Base system peripheral. 394 */ 395 396 /* PIC programming interface */ 397 static const struct pci_class pci_interface_pic[] = { 398 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 399 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 400 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 401 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 402 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 403 { NULL, 0, NULL, }, 404 }; 405 406 /* DMA programming interface */ 407 static const struct pci_class pci_interface_dma[] = { 408 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 409 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 410 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 411 { NULL, 0, NULL, }, 412 }; 413 414 /* Timer programming interface */ 415 static const struct pci_class pci_interface_tmr[] = { 416 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 417 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 418 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 419 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 420 { NULL, 0, NULL, }, 421 }; 422 423 /* RTC programming interface */ 424 static const struct pci_class pci_interface_rtc[] = { 425 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 426 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 427 { NULL, 0, NULL, }, 428 }; 429 430 /* Subclasses */ 431 static const struct pci_class pci_subclass_system[] = { 432 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 433 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 434 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 435 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 436 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 437 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 438 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 439 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 440 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 441 { NULL, 0, NULL, }, 442 }; 443 444 /* 445 * Class 0x09. 446 * Input device. 447 */ 448 449 /* Gameport programming interface */ 450 static const struct pci_class pci_interface_game[] = { 451 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 452 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 453 { NULL, 0, NULL, }, 454 }; 455 456 /* Subclasses */ 457 static const struct pci_class pci_subclass_input[] = { 458 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 459 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 460 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 461 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 462 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 463 pci_interface_game, }, 464 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 465 { NULL, 0, NULL, }, 466 }; 467 468 /* 469 * Class 0x0a. 470 * Docking station. 471 */ 472 static const struct pci_class pci_subclass_dock[] = { 473 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 474 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 475 { NULL, 0, NULL, }, 476 }; 477 478 /* 479 * Class 0x0b. 480 * Processor. 481 */ 482 static const struct pci_class pci_subclass_processor[] = { 483 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 484 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 485 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 486 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 487 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 488 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 489 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 490 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 491 { NULL, 0, NULL, }, 492 }; 493 494 /* 495 * Class 0x0c. 496 * Serial bus controller. 497 */ 498 499 /* IEEE1394 programming interface */ 500 static const struct pci_class pci_interface_ieee1394[] = { 501 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 502 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 503 { NULL, 0, NULL,}, 504 }; 505 506 /* USB programming interface */ 507 static const struct pci_class pci_interface_usb[] = { 508 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 509 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 510 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 511 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 512 { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, }, 513 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 514 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 515 { NULL, 0, NULL, }, 516 }; 517 518 /* IPMI programming interface */ 519 static const struct pci_class pci_interface_ipmi[] = { 520 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 521 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 522 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 523 { NULL, 0, NULL, }, 524 }; 525 526 /* Subclasses */ 527 static const struct pci_class pci_subclass_serialbus[] = { 528 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 529 pci_interface_ieee1394, }, 530 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 531 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 532 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 533 pci_interface_usb, }, 534 /* XXX Fiber Channel/_FIBRECHANNEL */ 535 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 536 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 537 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 538 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 539 pci_interface_ipmi, }, 540 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 541 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 542 { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, }, 543 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 544 { NULL, 0, NULL, }, 545 }; 546 547 /* 548 * Class 0x0d. 549 * Wireless Controller. 550 */ 551 static const struct pci_class pci_subclass_wireless[] = { 552 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 553 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 554 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 555 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 556 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 557 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 558 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 559 { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, }, 560 { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, }, 561 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 562 { NULL, 0, NULL, }, 563 }; 564 565 /* 566 * Class 0x0e. 567 * Intelligent IO controller. 568 */ 569 570 /* Intelligent IO programming interface */ 571 static const struct pci_class pci_interface_i2o[] = { 572 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 573 { NULL, 0, NULL, }, 574 }; 575 576 /* Subclasses */ 577 static const struct pci_class pci_subclass_i2o[] = { 578 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 579 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 580 { NULL, 0, NULL, }, 581 }; 582 583 /* 584 * Class 0x0f. 585 * Satellite communication controller. 586 */ 587 static const struct pci_class pci_subclass_satcom[] = { 588 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 589 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 590 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 591 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 592 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 593 { NULL, 0, NULL, }, 594 }; 595 596 /* 597 * Class 0x10. 598 * Encryption/Decryption controller. 599 */ 600 static const struct pci_class pci_subclass_crypto[] = { 601 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 602 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 603 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 604 { NULL, 0, NULL, }, 605 }; 606 607 /* 608 * Class 0x11. 609 * Data acquisition and signal processing controller. 610 */ 611 static const struct pci_class pci_subclass_dasp[] = { 612 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 613 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 614 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 615 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 616 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 617 { NULL, 0, NULL, }, 618 }; 619 620 /* List of classes */ 621 static const struct pci_class pci_classes[] = { 622 { "prehistoric", PCI_CLASS_PREHISTORIC, 623 pci_subclass_prehistoric, }, 624 { "mass storage", PCI_CLASS_MASS_STORAGE, 625 pci_subclass_mass_storage, }, 626 { "network", PCI_CLASS_NETWORK, 627 pci_subclass_network, }, 628 { "display", PCI_CLASS_DISPLAY, 629 pci_subclass_display, }, 630 { "multimedia", PCI_CLASS_MULTIMEDIA, 631 pci_subclass_multimedia, }, 632 { "memory", PCI_CLASS_MEMORY, 633 pci_subclass_memory, }, 634 { "bridge", PCI_CLASS_BRIDGE, 635 pci_subclass_bridge, }, 636 { "communications", PCI_CLASS_COMMUNICATIONS, 637 pci_subclass_communications, }, 638 { "system", PCI_CLASS_SYSTEM, 639 pci_subclass_system, }, 640 { "input", PCI_CLASS_INPUT, 641 pci_subclass_input, }, 642 { "dock", PCI_CLASS_DOCK, 643 pci_subclass_dock, }, 644 { "processor", PCI_CLASS_PROCESSOR, 645 pci_subclass_processor, }, 646 { "serial bus", PCI_CLASS_SERIALBUS, 647 pci_subclass_serialbus, }, 648 { "wireless", PCI_CLASS_WIRELESS, 649 pci_subclass_wireless, }, 650 { "I2O", PCI_CLASS_I2O, 651 pci_subclass_i2o, }, 652 { "satellite comm", PCI_CLASS_SATCOM, 653 pci_subclass_satcom, }, 654 { "crypto", PCI_CLASS_CRYPTO, 655 pci_subclass_crypto, }, 656 { "DASP", PCI_CLASS_DASP, 657 pci_subclass_dasp, }, 658 { "processing accelerators", PCI_CLASS_ACCEL, 659 NULL, }, 660 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 661 NULL, }, 662 { "undefined", PCI_CLASS_UNDEFINED, 663 NULL, }, 664 { NULL, 0, 665 NULL, }, 666 }; 667 668 DEV_VERBOSE_DEFINE(pci); 669 670 /* 671 * Append a formatted string to dest without writing more than len 672 * characters (including the trailing NUL character). dest and len 673 * are updated for use in subsequent calls to snappendf(). 674 * 675 * Returns 0 on success, a negative value if vnsprintf() fails, or 676 * a positive value if the dest buffer would have overflowed. 677 */ 678 679 static int __printflike(3, 4) 680 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 681 { 682 va_list ap; 683 int count; 684 685 va_start(ap, fmt); 686 count = vsnprintf(*dest, *len, fmt, ap); 687 va_end(ap); 688 689 /* Let vsnprintf() errors bubble up to caller */ 690 if (count < 0 || *len == 0) 691 return count; 692 693 /* Handle overflow */ 694 if ((size_t)count >= *len) { 695 *dest += *len - 1; 696 *len = 1; 697 return 1; 698 } 699 700 /* Update dest & len to point at trailing NUL */ 701 *dest += count; 702 *len -= count; 703 704 return 0; 705 } 706 707 void 708 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 709 size_t l) 710 { 711 pci_class_t class; 712 pci_subclass_t subclass; 713 pci_interface_t interface; 714 pci_revision_t revision; 715 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 716 const struct pci_class *classp, *subclassp, *interfacep; 717 718 class = PCI_CLASS(class_reg); 719 subclass = PCI_SUBCLASS(class_reg); 720 interface = PCI_INTERFACE(class_reg); 721 revision = PCI_REVISION(class_reg); 722 723 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 724 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 725 PCI_PRODUCT(id_reg)); 726 727 classp = pci_classes; 728 while (classp->name != NULL) { 729 if (class == classp->val) 730 break; 731 classp++; 732 } 733 734 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 735 while (subclassp && subclassp->name != NULL) { 736 if (subclass == subclassp->val) 737 break; 738 subclassp++; 739 } 740 741 interfacep = (subclassp && subclassp->name != NULL) ? 742 subclassp->subclasses : NULL; 743 while (interfacep && interfacep->name != NULL) { 744 if (interface == interfacep->val) 745 break; 746 interfacep++; 747 } 748 749 (void)snappendf(&cp, &l, "%s %s", vendor, product); 750 if (showclass) { 751 (void)snappendf(&cp, &l, " ("); 752 if (classp->name == NULL) 753 (void)snappendf(&cp, &l, 754 "class 0x%02x, subclass 0x%02x", 755 class, subclass); 756 else { 757 if (subclassp == NULL || subclassp->name == NULL) 758 (void)snappendf(&cp, &l, 759 "%s, subclass 0x%02x", 760 classp->name, subclass); 761 else 762 (void)snappendf(&cp, &l, "%s %s", 763 subclassp->name, classp->name); 764 } 765 if ((interfacep == NULL) || (interfacep->name == NULL)) { 766 if (interface != 0) 767 (void)snappendf(&cp, &l, ", interface 0x%02x", 768 interface); 769 } else if (strncmp(interfacep->name, "", 1) != 0) 770 (void)snappendf(&cp, &l, ", %s", interfacep->name); 771 if (revision != 0) 772 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 773 (void)snappendf(&cp, &l, ")"); 774 } 775 } 776 777 #ifdef _KERNEL 778 void 779 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 780 const char *known, int addrev) 781 { 782 char devinfo[256]; 783 784 if (known) { 785 aprint_normal(": %s", known); 786 if (addrev) 787 aprint_normal(" (rev. 0x%02x)", 788 PCI_REVISION(pa->pa_class)); 789 aprint_normal("\n"); 790 } else { 791 pci_devinfo(pa->pa_id, pa->pa_class, 0, 792 devinfo, sizeof(devinfo)); 793 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 794 PCI_REVISION(pa->pa_class)); 795 } 796 if (naive) 797 aprint_naive(": %s\n", naive); 798 else 799 aprint_naive("\n"); 800 } 801 #endif 802 803 /* 804 * Print out most of the PCI configuration registers. Typically used 805 * in a device attach routine like this: 806 * 807 * #ifdef MYDEV_DEBUG 808 * printf("%s: ", device_xname(sc->sc_dev)); 809 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 810 * #endif 811 */ 812 813 #define i2o(i) ((i) * 4) 814 #define o2i(o) ((o) / 4) 815 #define onoff2(str, rval, bit, onstr, offstr) \ 816 /*CONSTCOND*/ \ 817 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 818 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 819 820 static void 821 pci_conf_print_common( 822 #ifdef _KERNEL 823 pci_chipset_tag_t pc, pcitag_t tag, 824 #endif 825 const pcireg_t *regs) 826 { 827 pci_class_t class; 828 pci_subclass_t subclass; 829 pci_interface_t interface; 830 pci_revision_t revision; 831 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 832 const struct pci_class *classp, *subclassp, *interfacep; 833 const char *name; 834 pcireg_t rval; 835 unsigned int num; 836 837 rval = regs[o2i(PCI_CLASS_REG)]; 838 class = PCI_CLASS(rval); 839 subclass = PCI_SUBCLASS(rval); 840 interface = PCI_INTERFACE(rval); 841 revision = PCI_REVISION(rval); 842 843 rval = regs[o2i(PCI_ID_REG)]; 844 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 845 if (name) 846 printf(" Vendor Name: %s (0x%04x)\n", name, 847 PCI_VENDOR(rval)); 848 else 849 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 850 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 851 PCI_PRODUCT(rval)); 852 if (name) 853 printf(" Device Name: %s (0x%04x)\n", name, 854 PCI_PRODUCT(rval)); 855 else 856 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 857 858 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 859 860 printf(" Command register: 0x%04x\n", rval & 0xffff); 861 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 862 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 863 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 864 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 865 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 866 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 867 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 868 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 869 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 870 onoff("Fast back-to-back transactions", rval, 871 PCI_COMMAND_BACKTOBACK_ENABLE); 872 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 873 874 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 875 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 876 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 877 "inactive"); 878 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 879 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 880 onoff("User Definable Features (UDF) support", rval, 881 PCI_STATUS_UDF_SUPPORT); 882 onoff("Fast back-to-back capable", rval, 883 PCI_STATUS_BACKTOBACK_SUPPORT); 884 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 885 886 printf(" DEVSEL timing: "); 887 switch (rval & PCI_STATUS_DEVSEL_MASK) { 888 case PCI_STATUS_DEVSEL_FAST: 889 printf("fast"); 890 break; 891 case PCI_STATUS_DEVSEL_MEDIUM: 892 printf("medium"); 893 break; 894 case PCI_STATUS_DEVSEL_SLOW: 895 printf("slow"); 896 break; 897 default: 898 printf("unknown/reserved"); /* XXX */ 899 break; 900 } 901 printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 902 903 onoff("Slave signaled Target Abort", rval, 904 PCI_STATUS_TARGET_TARGET_ABORT); 905 onoff("Master received Target Abort", rval, 906 PCI_STATUS_MASTER_TARGET_ABORT); 907 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 908 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 909 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 910 911 rval = regs[o2i(PCI_CLASS_REG)]; 912 for (classp = pci_classes; classp->name != NULL; classp++) { 913 if (class == classp->val) 914 break; 915 } 916 917 /* 918 * ECN: Change Root Complex Event Collector Class Code 919 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 920 * in PCIe extend capability to know whether it's RCEC or IOMMU. 921 */ 922 if ((class == PCI_CLASS_SYSTEM) 923 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 924 int pcie_capoff; 925 pcireg_t reg; 926 927 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 928 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 929 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC) 930 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 931 } 932 } 933 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 934 while (subclassp && subclassp->name != NULL) { 935 if (subclass == subclassp->val) 936 break; 937 subclassp++; 938 } 939 940 interfacep = (subclassp && subclassp->name != NULL) ? 941 subclassp->subclasses : NULL; 942 while (interfacep && interfacep->name != NULL) { 943 if (interface == interfacep->val) 944 break; 945 interfacep++; 946 } 947 948 if (classp->name != NULL) 949 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 950 else 951 printf(" Class ID: 0x%02x\n", class); 952 if (subclassp != NULL && subclassp->name != NULL) 953 printf(" Subclass Name: %s (0x%02x)\n", 954 subclassp->name, PCI_SUBCLASS(rval)); 955 else 956 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 957 if ((interfacep != NULL) && (interfacep->name != NULL) 958 && (strncmp(interfacep->name, "", 1) != 0)) 959 printf(" Interface Name: %s (0x%02x)\n", 960 interfacep->name, interface); 961 else 962 printf(" Interface: 0x%02x\n", interface); 963 printf(" Revision ID: 0x%02x\n", revision); 964 965 rval = regs[o2i(PCI_BHLC_REG)]; 966 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 967 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 968 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 969 PCI_HDRTYPE(rval)); 970 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 971 num = PCI_CACHELINE(rval); 972 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 973 } 974 975 static int 976 pci_conf_print_bar( 977 #ifdef _KERNEL 978 pci_chipset_tag_t pc, pcitag_t tag, 979 #endif 980 const pcireg_t *regs, int reg, const char *name) 981 { 982 int width; 983 pcireg_t rval, rval64h; 984 bool ioen, memen; 985 #ifdef _KERNEL 986 pcireg_t mask, mask64h = 0; 987 #endif 988 989 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 990 ioen = rval & PCI_COMMAND_IO_ENABLE; 991 memen = rval & PCI_COMMAND_MEM_ENABLE; 992 993 width = 4; 994 /* 995 * Section 6.2.5.1, `Address Maps', tells us that: 996 * 997 * 1) The builtin software should have already mapped the 998 * device in a reasonable way. 999 * 1000 * 2) A device which wants 2^n bytes of memory will hardwire 1001 * the bottom n bits of the address to 0. As recommended, 1002 * we write all 1s and see what we get back. 1003 */ 1004 1005 rval = regs[o2i(reg)]; 1006 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 1007 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 1008 rval64h = regs[o2i(reg + 4)]; 1009 width = 8; 1010 } else 1011 rval64h = 0; 1012 1013 #ifdef _KERNEL 1014 if (rval != 0 && memen) { 1015 int s; 1016 1017 /* 1018 * The following sequence seems to make some devices 1019 * (e.g. host bus bridges, which don't normally 1020 * have their space mapped) very unhappy, to 1021 * the point of crashing the system. 1022 * 1023 * Therefore, if the mapping register is zero to 1024 * start out with, don't bother trying. 1025 */ 1026 s = splhigh(); 1027 pci_conf_write(pc, tag, reg, 0xffffffff); 1028 mask = pci_conf_read(pc, tag, reg); 1029 pci_conf_write(pc, tag, reg, rval); 1030 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 1031 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 1032 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 1033 mask64h = pci_conf_read(pc, tag, reg + 4); 1034 pci_conf_write(pc, tag, reg + 4, rval64h); 1035 } 1036 splx(s); 1037 } else 1038 mask = mask64h = 0; 1039 #endif /* _KERNEL */ 1040 1041 printf(" Base address register at 0x%02x", reg); 1042 if (name) 1043 printf(" (%s)", name); 1044 printf("\n "); 1045 if (rval == 0) { 1046 printf("not implemented\n"); 1047 return width; 1048 } 1049 printf("type: "); 1050 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 1051 const char *type, *prefetch; 1052 1053 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1054 case PCI_MAPREG_MEM_TYPE_32BIT: 1055 type = "32-bit"; 1056 break; 1057 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1058 type = "32-bit-1M"; 1059 break; 1060 case PCI_MAPREG_MEM_TYPE_64BIT: 1061 type = "64-bit"; 1062 break; 1063 default: 1064 type = "unknown (XXX)"; 1065 break; 1066 } 1067 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 1068 prefetch = ""; 1069 else 1070 prefetch = "non"; 1071 printf("%s %sprefetchable memory\n", type, prefetch); 1072 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1073 case PCI_MAPREG_MEM_TYPE_64BIT: 1074 printf(" base: 0x%016llx", 1075 PCI_MAPREG_MEM64_ADDR( 1076 ((((long long) rval64h) << 32) | rval))); 1077 if (!memen) 1078 printf(", disabled"); 1079 printf("\n"); 1080 #ifdef _KERNEL 1081 printf(" size: 0x%016llx\n", 1082 PCI_MAPREG_MEM64_SIZE( 1083 ((((long long) mask64h) << 32) | mask))); 1084 #endif 1085 break; 1086 case PCI_MAPREG_MEM_TYPE_32BIT: 1087 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1088 default: 1089 printf(" base: 0x%08x", 1090 PCI_MAPREG_MEM_ADDR(rval)); 1091 if (!memen) 1092 printf(", disabled"); 1093 printf("\n"); 1094 #ifdef _KERNEL 1095 printf(" size: 0x%08x\n", 1096 PCI_MAPREG_MEM_SIZE(mask)); 1097 #endif 1098 break; 1099 } 1100 } else { 1101 #ifdef _KERNEL 1102 if (ioen) 1103 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1104 #endif 1105 printf("I/O\n"); 1106 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1107 if (!ioen) 1108 printf(", disabled"); 1109 printf("\n"); 1110 #ifdef _KERNEL 1111 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1112 #endif 1113 } 1114 1115 return width; 1116 } 1117 1118 static void 1119 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1120 { 1121 int off, needaddr, neednl; 1122 1123 needaddr = 1; 1124 neednl = 0; 1125 for (off = first; off < pastlast; off += 4) { 1126 if ((off % 16) == 0 || needaddr) { 1127 printf(" 0x%02x:", off); 1128 needaddr = 0; 1129 } 1130 printf(" 0x%08x", regs[o2i(off)]); 1131 neednl = 1; 1132 if ((off % 16) == 12) { 1133 printf("\n"); 1134 neednl = 0; 1135 } 1136 } 1137 if (neednl) 1138 printf("\n"); 1139 } 1140 1141 static const char * 1142 pci_conf_print_agp_calcycle(uint8_t cal) 1143 { 1144 1145 switch (cal) { 1146 case 0x0: 1147 return "4ms"; 1148 case 0x1: 1149 return "16ms"; 1150 case 0x2: 1151 return "64ms"; 1152 case 0x3: 1153 return "256ms"; 1154 case 0x7: 1155 return "Calibration Cycle Not Needed"; 1156 default: 1157 return "(reserved)"; 1158 } 1159 } 1160 1161 static void 1162 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1163 { 1164 if (isagp3) { 1165 /* AGP 3.0 */ 1166 if (reg & AGP_MODE_V3_RATE_4x) 1167 printf("x4"); 1168 if (reg & AGP_MODE_V3_RATE_8x) 1169 printf("x8"); 1170 } else { 1171 /* AGP 2.0 */ 1172 if (reg & AGP_MODE_V2_RATE_1x) 1173 printf("x1"); 1174 if (reg & AGP_MODE_V2_RATE_2x) 1175 printf("x2"); 1176 if (reg & AGP_MODE_V2_RATE_4x) 1177 printf("x4"); 1178 } 1179 printf("\n"); 1180 } 1181 1182 static void 1183 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1184 { 1185 pcireg_t rval; 1186 bool isagp3; 1187 1188 printf("\n AGP Capabilities Register\n"); 1189 1190 rval = regs[o2i(capoff)]; 1191 printf(" Revision: %d.%d\n", 1192 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1193 1194 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1195 printf(" Status register: 0x%04x\n", rval); 1196 printf(" RQ: %u\n", 1197 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1198 printf(" ARQSZ: %u\n", 1199 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1200 printf(" CAL cycle: %s\n", 1201 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1202 onoff("SBA", rval, AGP_MODE_SBA); 1203 onoff("htrans#", rval, AGP_MODE_HTRANS); 1204 onoff("Over 4G", rval, AGP_MODE_4G); 1205 onoff("Fast Write", rval, AGP_MODE_FW); 1206 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1207 isagp3 = rval & AGP_MODE_MODE_3; 1208 printf(" Data Rate Support: "); 1209 pci_conf_print_agp_datarate(rval, isagp3); 1210 1211 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1212 printf(" Command register: 0x%08x\n", rval); 1213 printf(" PRQ: %u\n", 1214 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1215 printf(" PARQSZ: %u\n", 1216 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1217 printf(" PCAL cycle: %s\n", 1218 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1219 onoff("SBA", rval, AGP_MODE_SBA); 1220 onoff("AGP", rval, AGP_MODE_AGP); 1221 onoff("Over 4G", rval, AGP_MODE_4G); 1222 onoff("Fast Write", rval, AGP_MODE_FW); 1223 if (isagp3) { 1224 printf(" Data Rate Enable: "); 1225 /* 1226 * The Data Rate Enable bits are used only on 3.0 and the 1227 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1228 * flag to print correctly. 1229 */ 1230 pci_conf_print_agp_datarate(rval, isagp3); 1231 } 1232 } 1233 1234 static const char * 1235 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1236 { 1237 1238 switch ((caps >> 6) & 7) { 1239 case 0: return "self-powered"; 1240 case 1: return "55 mA"; 1241 case 2: return "100 mA"; 1242 case 3: return "160 mA"; 1243 case 4: return "220 mA"; 1244 case 5: return "270 mA"; 1245 case 6: return "320 mA"; 1246 case 7: 1247 default: return "375 mA"; 1248 } 1249 } 1250 1251 static const char * 1252 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1253 { 1254 static const char unk[] = "unknown"; 1255 static const char *pmrev[8] = { 1256 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1257 }; 1258 if (val > 7) 1259 return unk; 1260 return pmrev[val]; 1261 } 1262 1263 static void 1264 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1265 { 1266 uint16_t caps, pmcsr; 1267 1268 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1269 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1270 1271 printf("\n PCI Power Management Capabilities Register\n"); 1272 1273 printf(" Capabilities register: 0x%04x\n", caps); 1274 printf(" Version: %s\n", 1275 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1276 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1277 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1278 printf(" 3.3V auxiliary current: %s\n", 1279 pci_conf_print_pcipm_cap_aux(caps)); 1280 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1281 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1282 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1283 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1284 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1285 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1286 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1287 1288 printf(" Control/status register: 0x%08x\n", pmcsr); 1289 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1290 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1291 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1292 printf(" PME# assertion: %sabled\n", 1293 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1294 printf(" Data Select: %d\n", 1295 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1296 printf(" Data Scale: %d\n", 1297 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1298 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1299 printf(" Bridge Support Extensions register: 0x%02x\n", 1300 (pmcsr >> 16) & 0xff); 1301 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1302 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1303 printf(" Data register: 0x%02x\n", 1304 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1305 } 1306 1307 /* XXX pci_conf_print_vpd_cap */ 1308 /* XXX pci_conf_print_slotid_cap */ 1309 1310 static void 1311 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1312 { 1313 uint32_t ctl, mmc, mme; 1314 1315 regs += o2i(capoff); 1316 ctl = *regs++; 1317 mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1318 mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1319 1320 printf("\n PCI Message Signaled Interrupt\n"); 1321 1322 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1323 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1324 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1325 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1326 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1327 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1328 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1329 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1330 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1331 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1332 printf(" Message Address %sregister: 0x%08x\n", 1333 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1334 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1335 printf(" Message Address %sregister: 0x%08x\n", 1336 "(upper) ", *regs++); 1337 } 1338 printf(" Message Data register: "); 1339 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1340 printf("0x%08x\n", *regs); 1341 else 1342 printf("0x%04x\n", *regs & 0xffff); 1343 regs++; 1344 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1345 printf(" Vector Mask register: 0x%08x\n", *regs++); 1346 printf(" Vector Pending register: 0x%08x\n", *regs++); 1347 } 1348 } 1349 1350 /* XXX pci_conf_print_cpci_hostwap_cap */ 1351 1352 /* 1353 * For both command register and status register. 1354 * The argument "idx" is index number (0 to 7). 1355 */ 1356 static int 1357 pcix_split_trans(unsigned int idx) 1358 { 1359 static int table[8] = { 1360 1, 2, 3, 4, 8, 12, 16, 32 1361 }; 1362 1363 if (idx >= __arraycount(table)) 1364 return -1; 1365 return table[idx]; 1366 } 1367 1368 static void 1369 pci_conf_print_pcix_cap_2ndbusmode(int num) 1370 { 1371 const char *maxfreq, *maxperiod; 1372 1373 printf(" Mode: "); 1374 if (num <= 0x07) 1375 printf("PCI-X Mode 1\n"); 1376 else if (num <= 0x0b) 1377 printf("PCI-X 266 (Mode 2)\n"); 1378 else 1379 printf("PCI-X 533 (Mode 2)\n"); 1380 1381 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1382 switch (num & 0x03) { 1383 default: 1384 case 0: 1385 maxfreq = "N/A"; 1386 maxperiod = "N/A"; 1387 break; 1388 case 1: 1389 maxfreq = "66MHz"; 1390 maxperiod = "15ns"; 1391 break; 1392 case 2: 1393 maxfreq = "100MHz"; 1394 maxperiod = "10ns"; 1395 break; 1396 case 3: 1397 maxfreq = "133MHz"; 1398 maxperiod = "7.5ns"; 1399 break; 1400 } 1401 printf(" Max Clock Freq: %s\n", maxfreq); 1402 printf(" Min Clock Period: %s\n", maxperiod); 1403 } 1404 1405 static void 1406 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1407 { 1408 pcireg_t reg; 1409 int isbridge; 1410 int i; 1411 1412 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1413 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1414 printf("\n PCI-X %s Capabilities Register\n", 1415 isbridge ? "Bridge" : "Non-bridge"); 1416 1417 reg = regs[o2i(capoff)]; 1418 if (isbridge != 0) { 1419 printf(" Secondary status register: 0x%04x\n", 1420 (reg & 0xffff0000) >> 16); 1421 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1422 onoff("133MHz capable", reg, PCIX_STATUS_133); 1423 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1424 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1425 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1426 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1427 pci_conf_print_pcix_cap_2ndbusmode( 1428 PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1429 printf(" Version: 0x%x\n", 1430 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1431 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1432 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1433 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1434 } else { 1435 printf(" Command register: 0x%04x\n", 1436 (reg & 0xffff0000) >> 16); 1437 onoff("Data Parity Error Recovery", reg, 1438 PCIX_CMD_PERR_RECOVER); 1439 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1440 printf(" Maximum Burst Read Count: %u\n", 1441 PCIX_CMD_BYTECNT(reg)); 1442 printf(" Maximum Split Transactions: %d\n", 1443 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1444 >> PCIX_CMD_SPLTRANS_SHIFT)); 1445 } 1446 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1447 printf(" %sStatus register: 0x%08x\n", 1448 isbridge ? "Bridge " : "", reg); 1449 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1450 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1451 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1452 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1453 onoff("133MHz capable", reg, PCIX_STATUS_133); 1454 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1455 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1456 if (isbridge != 0) { 1457 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1458 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1459 } else { 1460 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1461 "bridge device", "simple device"); 1462 printf(" Designed max memory read byte count: %d\n", 1463 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1464 >> PCIX_STATUS_MAXB_SHIFT)); 1465 printf(" Designed max outstanding split transaction: %d\n", 1466 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1467 >> PCIX_STATUS_MAXST_SHIFT)); 1468 printf(" MAX cumulative Read Size: %u\n", 1469 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1470 onoff("Received split completion error", reg, 1471 PCIX_STATUS_SCERR); 1472 } 1473 onoff("266MHz capable", reg, PCIX_STATUS_266); 1474 onoff("533MHz capable", reg, PCIX_STATUS_533); 1475 1476 if (isbridge == 0) 1477 return; 1478 1479 /* Only for bridge */ 1480 for (i = 0; i < 2; i++) { 1481 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1482 printf(" %s split transaction control register: 0x%08x\n", 1483 (i == 0) ? "Upstream" : "Downstream", reg); 1484 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1485 printf(" Commitment Limit: %d\n", 1486 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1487 } 1488 } 1489 1490 /* pci_conf_print_ht_slave_cap */ 1491 /* pci_conf_print_ht_host_cap */ 1492 /* pci_conf_print_ht_switch_cap */ 1493 /* pci_conf_print_ht_intr_cap */ 1494 /* pci_conf_print_ht_revid_cap */ 1495 /* pci_conf_print_ht_unitid_cap */ 1496 /* pci_conf_print_ht_extcnf_cap */ 1497 /* pci_conf_print_ht_addrmap_cap */ 1498 /* pci_conf_print_ht_msimap_cap */ 1499 1500 static void 1501 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1502 { 1503 pcireg_t val; 1504 uint32_t lo, hi; 1505 1506 /* 1507 * Print the rest of the command register bits. Others are 1508 * printed in pci_conf_print_ht_cap(). 1509 */ 1510 val = regs[o2i(capoff + PCI_HT_CMD)]; 1511 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1512 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1513 1514 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1515 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1516 printf(" Address Low register: 0x%08x\n", lo); 1517 printf(" Address high register: 0x%08x\n", hi); 1518 printf(" Address: 0x%016" PRIx64 "\n", 1519 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1520 } 1521 1522 /* pci_conf_print_ht_droute_cap */ 1523 /* pci_conf_print_ht_vcset_cap */ 1524 /* pci_conf_print_ht_retry_cap */ 1525 /* pci_conf_print_ht_x86enc_cap */ 1526 /* pci_conf_print_ht_gen3_cap */ 1527 /* pci_conf_print_ht_fle_cap */ 1528 /* pci_conf_print_ht_pm_cap */ 1529 /* pci_conf_print_ht_hnc_cap */ 1530 1531 static const struct ht_types { 1532 pcireg_t cap; 1533 const char *name; 1534 void (*printfunc)(const pcireg_t *, int); 1535 } ht_captab[] = { 1536 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1537 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1538 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1539 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1540 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1541 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1542 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1543 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1544 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1545 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1546 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1547 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1548 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1549 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1550 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1551 {PCI_HT_CAP_PM, "Power Management", NULL }, 1552 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1553 }; 1554 1555 static void 1556 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1557 { 1558 pcireg_t val, foundcap; 1559 unsigned int off; 1560 1561 val = regs[o2i(capoff + PCI_HT_CMD)]; 1562 1563 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1564 1565 printf(" Command register: 0x%04x\n", val >> 16); 1566 foundcap = PCI_HT_CAP(val); 1567 for (off = 0; off < __arraycount(ht_captab); off++) { 1568 if (ht_captab[off].cap == foundcap) 1569 break; 1570 } 1571 printf(" Capability Type: 0x%02x ", foundcap); 1572 if (off >= __arraycount(ht_captab)) { 1573 printf("(unknown)\n"); 1574 return; 1575 } 1576 printf("(%s)\n", ht_captab[off].name); 1577 if (ht_captab[off].printfunc != NULL) 1578 ht_captab[off].printfunc(regs, capoff); 1579 } 1580 1581 static void 1582 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1583 { 1584 uint16_t caps; 1585 1586 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1587 1588 printf("\n PCI Vendor Specific Capabilities Register\n"); 1589 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1590 } 1591 1592 static void 1593 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1594 { 1595 pcireg_t val; 1596 1597 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1598 1599 printf("\n Debugport Capability Register\n"); 1600 printf(" Debug base Register: 0x%04x\n", 1601 val >> PCI_DEBUG_BASER_SHIFT); 1602 printf(" port offset: 0x%04x\n", 1603 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1604 printf(" BAR number: %u\n", 1605 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1606 } 1607 1608 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1609 /* XXX pci_conf_print_hotplug_cap */ 1610 1611 static void 1612 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1613 { 1614 pcireg_t reg; 1615 1616 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1617 1618 printf("\n Subsystem ID Capability Register\n"); 1619 printf(" Subsystem ID: 0x%08x\n", reg); 1620 } 1621 1622 /* XXX pci_conf_print_agp8_cap */ 1623 static void 1624 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1625 { 1626 pcireg_t reg, reg2, val; 1627 bool havemisc1; 1628 1629 printf("\n Secure Capability Register\n"); 1630 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1631 printf(" Capability Register: 0x%04x\n", reg >> 16); 1632 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1633 printf(" Capability block type: "); 1634 /* I know IOMMU Only */ 1635 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1636 printf("IOMMU\n"); 1637 else { 1638 printf("0x%x(unknown)\n", val); 1639 return; 1640 } 1641 1642 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1643 printf(" Capability revision: 0x%02x ", val); 1644 if (val == PCI_SECURE_CAP_REV_IOMMU) 1645 printf("(IOMMU)\n"); 1646 else { 1647 printf("(unknown)\n"); 1648 return; 1649 } 1650 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1651 onoff("HyperTransport tunnel translation support", reg, 1652 PCI_SECURE_CAP_HTTUNNEL); 1653 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1654 onoff("IOMMU Extended Feature Register support", reg, 1655 PCI_SECURE_CAP_EFRSUP); 1656 onoff("IOMMU Miscellaneous Information Register 1", reg, 1657 PCI_SECURE_CAP_EXT); 1658 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1659 1660 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1661 printf(" Base Address Low Register: 0x%08x\n", reg); 1662 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1663 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1664 printf(" Base Address High Register: 0x%08x\n", reg2); 1665 printf(" Base Address: 0x%016" PRIx64 "\n", 1666 ((uint64_t)reg2 << 32) 1667 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1668 1669 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1670 printf(" IOMMU Range Register: 0x%08x\n", reg); 1671 printf(" HyperTransport UnitID: 0x%02x\n", 1672 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1673 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1674 printf(" Device range bus number: 0x%02x\n", 1675 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1676 printf(" First device: 0x%04x\n", 1677 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1678 printf(" Last device: 0x%04x\n", 1679 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1680 1681 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1682 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1683 printf(" MSI Message number: 0x%02x\n", 1684 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1685 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1686 printf(" Guest Virtual Address size: "); 1687 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1688 printf("48bits\n"); 1689 else 1690 printf("0x%x(unknown)\n", val); 1691 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1692 printf(" Physical Address size: %dbits\n", val); 1693 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1694 printf(" Virtual Address size: %dbits\n", val); 1695 onoff("ATS response address range reserved", reg, 1696 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1697 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1698 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1699 1700 if (!havemisc1) 1701 return; 1702 1703 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1704 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1705 printf(" MSI Message number (GA): 0x%02x\n", 1706 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1707 } 1708 1709 static void 1710 pci_print_pcie_L0s_latency(uint32_t val) 1711 { 1712 1713 switch (val) { 1714 case 0x0: 1715 printf("Less than 64ns\n"); 1716 break; 1717 case 0x1: 1718 case 0x2: 1719 case 0x3: 1720 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1721 break; 1722 case 0x4: 1723 printf("512ns to less than 1us\n"); 1724 break; 1725 case 0x5: 1726 printf("1us to less than 2us\n"); 1727 break; 1728 case 0x6: 1729 printf("2us - 4us\n"); 1730 break; 1731 case 0x7: 1732 printf("More than 4us\n"); 1733 break; 1734 } 1735 } 1736 1737 static void 1738 pci_print_pcie_L1_latency(uint32_t val) 1739 { 1740 1741 switch (val) { 1742 case 0x0: 1743 printf("Less than 1us\n"); 1744 break; 1745 case 0x6: 1746 printf("32us - 64us\n"); 1747 break; 1748 case 0x7: 1749 printf("More than 64us\n"); 1750 break; 1751 default: 1752 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1753 break; 1754 } 1755 } 1756 1757 static void 1758 pci_print_pcie_compl_timeout(uint32_t val) 1759 { 1760 1761 switch (val) { 1762 case 0x0: 1763 printf("50us to 50ms\n"); 1764 break; 1765 case 0x5: 1766 printf("16ms to 55ms\n"); 1767 break; 1768 case 0x6: 1769 printf("65ms to 210ms\n"); 1770 break; 1771 case 0x9: 1772 printf("260ms to 900ms\n"); 1773 break; 1774 case 0xa: 1775 printf("1s to 3.5s\n"); 1776 break; 1777 default: 1778 printf("unknown %u value\n", val); 1779 break; 1780 } 1781 } 1782 1783 static const char * const pcie_linkspeeds[] = { 1784 "2.5", "5.0", "8.0", "16.0", "32.0" 1785 }; 1786 1787 /* 1788 * Print link speed. This function is used for the following register bits: 1789 * Maximum Link Speed in LCAP 1790 * Current Link Speed in LCSR 1791 * Target Link Speed in LCSR2 1792 * All of above bitfield's values start from 1. 1793 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1794 * this check also works for devices which compliant to versions of the base 1795 * specification prior to 3.0. 1796 */ 1797 static void 1798 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1799 { 1800 1801 if ((regnum == PCIE_LCSR2) && (val == 0)) 1802 printf("2.5GT/s\n"); 1803 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1804 printf("unknown value (%u)\n", val); 1805 else 1806 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1807 } 1808 1809 /* 1810 * Print link speed "vector". 1811 * This function is used for the following register bits: 1812 * Supported Link Speeds Vector in LCAP2 1813 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1814 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1815 * Enable Lower SKP OS Generation Vector in LCTL3 1816 * All of above bitfield's values start from 0. 1817 */ 1818 static void 1819 pci_print_pcie_linkspeedvector(pcireg_t val) 1820 { 1821 unsigned int i; 1822 1823 /* Start from 0 */ 1824 for (i = 0; i < 16; i++) 1825 if (((val >> i) & 0x01) != 0) { 1826 if (i >= __arraycount(pcie_linkspeeds)) 1827 printf(" unknown vector (0x%x)", 1 << i); 1828 else 1829 printf(" %sGT/s", pcie_linkspeeds[i]); 1830 } 1831 } 1832 1833 static void 1834 pci_print_pcie_link_deemphasis(pcireg_t val) 1835 { 1836 switch (val) { 1837 case 0: 1838 printf("-6dB"); 1839 break; 1840 case 1: 1841 printf("-3.5dB"); 1842 break; 1843 default: 1844 printf("(reserved value)"); 1845 } 1846 } 1847 1848 static const struct _pcie_link_preset_preshoot_deemphasis { 1849 const char *preshoot; 1850 const char *deemphasis; 1851 } pcie_link_preset_preshoot_deemphasis[] = { 1852 { "0.0", "-6.0+-1.5" }, /* P0 */ 1853 { "0.0", "-3.5+-1" }, /* P1 */ 1854 { "0.0", "-4.4+-1.5" }, /* P2 */ 1855 { "0.0", "-2.5+-1" }, /* P3 */ 1856 { "0.0", "0.0" }, /* P4 */ 1857 { "1.9+-1", "0.0" }, /* P5 */ 1858 { "2.5+-1", "0.0" }, /* P6 */ 1859 { "3.5+-1", "-6.0+-1.5" }, /* P7 */ 1860 { "3.5+-1", "-3.5+-1" }, /* P8 */ 1861 { "3.5+-1", "0.0" }, /* P9 */ 1862 { "0.0", NULL } /* P10 */ 1863 }; 1864 1865 static void 1866 pci_print_pcie_link_preset_preshoot_deemphasis(pcireg_t val) 1867 { 1868 const char *deemphasis; 1869 1870 if (val >= __arraycount(pcie_link_preset_preshoot_deemphasis)) { 1871 /* 1872 * This may be printed because the default value of some 1873 * register fields is 0b1111. 1874 */ 1875 printf("reserved value (0x%x)", val); 1876 return; 1877 } 1878 1879 printf("Preshoot %sdB", 1880 pcie_link_preset_preshoot_deemphasis[val].preshoot); 1881 deemphasis = pcie_link_preset_preshoot_deemphasis[val].deemphasis; 1882 1883 if (deemphasis != NULL) 1884 printf(", De-emphasis %sdB", deemphasis); 1885 } 1886 1887 static void 1888 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1889 { 1890 pcireg_t reg; /* for each register */ 1891 pcireg_t val; /* for each bitfield */ 1892 bool check_slot = false; 1893 unsigned int pcie_devtype; 1894 bool check_upstreamport = false; 1895 unsigned int pciever; 1896 unsigned int i; 1897 1898 printf("\n PCI Express Capabilities Register\n"); 1899 /* Capability Register */ 1900 reg = regs[o2i(capoff)]; 1901 printf(" Capability register: 0x%04x\n", reg >> 16); 1902 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1903 printf(" Capability version: %u\n", pciever); 1904 printf(" Device type: "); 1905 pcie_devtype = PCIE_XCAP_TYPE(reg); 1906 switch (pcie_devtype) { 1907 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1908 printf("PCI Express Endpoint device\n"); 1909 check_upstreamport = true; 1910 break; 1911 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1912 printf("Legacy PCI Express Endpoint device\n"); 1913 check_upstreamport = true; 1914 break; 1915 case PCIE_XCAP_TYPE_RP: /* 0x4 */ 1916 printf("Root Port of PCI Express Root Complex\n"); 1917 check_slot = true; 1918 break; 1919 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1920 printf("Upstream Port of PCI Express Switch\n"); 1921 check_upstreamport = true; 1922 break; 1923 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1924 printf("Downstream Port of PCI Express Switch\n"); 1925 check_slot = true; 1926 break; 1927 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1928 printf("PCI Express to PCI/PCI-X Bridge\n"); 1929 check_upstreamport = true; 1930 break; 1931 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1932 printf("PCI/PCI-X to PCI Express Bridge\n"); 1933 /* Upstream port is not PCIe */ 1934 check_slot = true; 1935 break; 1936 case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */ 1937 printf("Root Complex Integrated Endpoint\n"); 1938 break; 1939 case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */ 1940 printf("Root Complex Event Collector\n"); 1941 break; 1942 default: 1943 printf("unknown\n"); 1944 break; 1945 } 1946 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1947 printf(" Interrupt Message Number: 0x%02x\n", 1948 PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1949 1950 /* Device Capability Register */ 1951 reg = regs[o2i(capoff + PCIE_DCAP)]; 1952 printf(" Device Capabilities Register: 0x%08x\n", reg); 1953 printf(" Max Payload Size Supported: %u bytes max\n", 1954 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1955 printf(" Phantom Functions Supported: "); 1956 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1957 case 0x0: 1958 printf("not available\n"); 1959 break; 1960 case 0x1: 1961 printf("MSB\n"); 1962 break; 1963 case 0x2: 1964 printf("two MSB\n"); 1965 break; 1966 case 0x3: 1967 printf("All three bits\n"); 1968 break; 1969 } 1970 printf(" Extended Tag Field Supported: %dbit\n", 1971 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1972 printf(" Endpoint L0 Acceptable Latency: "); 1973 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1974 printf(" Endpoint L1 Acceptable Latency: "); 1975 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1976 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1977 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1978 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1979 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1980 if (check_upstreamport) { 1981 printf(" Captured Slot Power Limit: "); 1982 pci_conf_print_pcie_power( 1983 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1984 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1985 } 1986 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1987 1988 /* Device Control Register */ 1989 reg = regs[o2i(capoff + PCIE_DCSR)]; 1990 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1991 onoff("Correctable Error Reporting Enable", reg, 1992 PCIE_DCSR_ENA_COR_ERR); 1993 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1994 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1995 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1996 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1997 printf(" Max Payload Size: %d byte\n", 1998 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1999 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 2000 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 2001 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 2002 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 2003 printf(" Max Read Request Size: %d byte\n", 2004 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 2005 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 2006 onoff("Bridge Config Retry Enable", reg, 2007 PCIE_DCSR_BRDG_CFG_RETRY); 2008 2009 /* Device Status Register */ 2010 reg = regs[o2i(capoff + PCIE_DCSR)]; 2011 printf(" Device Status Register: 0x%04x\n", reg >> 16); 2012 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 2013 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 2014 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 2015 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 2016 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 2017 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 2018 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 2019 2020 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2021 /* Link Capability Register */ 2022 reg = regs[o2i(capoff + PCIE_LCAP)]; 2023 printf(" Link Capabilities Register: 0x%08x\n", reg); 2024 printf(" Maximum Link Speed: "); 2025 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 2026 printf(" Maximum Link Width: x%u lanes\n", 2027 PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 2028 printf(" Active State PM Support: "); 2029 switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 2030 case 0x0: 2031 printf("No ASPM support\n"); 2032 break; 2033 case 0x1: 2034 printf("L0s supported\n"); 2035 break; 2036 case 0x2: 2037 printf("L1 supported\n"); 2038 break; 2039 case 0x3: 2040 printf("L0s and L1 supported\n"); 2041 break; 2042 } 2043 printf(" L0 Exit Latency: "); 2044 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 2045 printf(" L1 Exit Latency: "); 2046 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 2047 printf(" Port Number: %u\n", 2048 PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT)); 2049 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 2050 onoff("Surprise Down Error Report", reg, 2051 PCIE_LCAP_SURPRISE_DOWN); 2052 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 2053 onoff("Link BW Notification Capable", reg, 2054 PCIE_LCAP_LINK_BW_NOTIFY); 2055 onoff("ASPM Optionally Compliance", reg, 2056 PCIE_LCAP_ASPM_COMPLIANCE); 2057 2058 /* Link Control Register */ 2059 reg = regs[o2i(capoff + PCIE_LCSR)]; 2060 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 2061 printf(" Active State PM Control: "); 2062 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 2063 case 0: 2064 printf("disabled\n"); 2065 break; 2066 case 1: 2067 printf("L0s Entry Enabled\n"); 2068 break; 2069 case 2: 2070 printf("L1 Entry Enabled\n"); 2071 break; 2072 case 3: 2073 printf("L0s and L1 Entry Enabled\n"); 2074 break; 2075 } 2076 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 2077 "128bytes", "64bytes"); 2078 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 2079 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 2080 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 2081 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 2082 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 2083 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 2084 onoff("Link Bandwidth Management Interrupt Enable", reg, 2085 PCIE_LCSR_LBMIE); 2086 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 2087 PCIE_LCSR_LABIE); 2088 printf(" DRS Signaling Control: "); 2089 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 2090 case 0: 2091 printf("not reported\n"); 2092 break; 2093 case 1: 2094 printf("Interrupt Enabled\n"); 2095 break; 2096 case 2: 2097 printf("DRS to FRS Signaling Enabled\n"); 2098 break; 2099 default: 2100 printf("reserved\n"); 2101 break; 2102 } 2103 2104 /* Link Status Register */ 2105 reg = regs[o2i(capoff + PCIE_LCSR)]; 2106 printf(" Link Status Register: 0x%04x\n", reg >> 16); 2107 printf(" Negotiated Link Speed: "); 2108 pci_print_pcie_linkspeed(PCIE_LCSR, 2109 PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 2110 printf(" Negotiated Link Width: x%u lanes\n", 2111 PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW)); 2112 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 2113 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 2114 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 2115 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 2116 onoff("Link Bandwidth Management Status", reg, 2117 PCIE_LCSR_LINK_BW_MGMT); 2118 onoff("Link Autonomous Bandwidth Status", reg, 2119 PCIE_LCSR_LINK_AUTO_BW); 2120 } 2121 2122 if (check_slot == true) { 2123 pcireg_t slcap; 2124 2125 /* Slot Capability Register */ 2126 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 2127 printf(" Slot Capability Register: 0x%08x\n", reg); 2128 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2129 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2130 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2131 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2132 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2133 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2134 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2135 printf(" Slot Power Limit Value: "); 2136 pci_conf_print_pcie_power(PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2137 PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2138 onoff("Electromechanical Interlock Present", reg, 2139 PCIE_SLCAP_EIP); 2140 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2141 printf(" Physical Slot Number: %d\n", 2142 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2143 2144 /* Slot Control Register */ 2145 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2146 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2147 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2148 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2149 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2150 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2151 onoff("Command Completed Interrupt Enabled", reg, 2152 PCIE_SLCSR_CCE); 2153 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2154 /* 2155 * For Attention Indicator Control and Power Indicator Control, 2156 * it's allowed to be a read only value 0 if corresponding 2157 * capability register bit is 0. 2158 */ 2159 if (slcap & PCIE_SLCAP_AIP) { 2160 printf(" Attention Indicator Control: "); 2161 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2162 case 0x0: 2163 printf("reserved\n"); 2164 break; 2165 case PCIE_SLCSR_IND_ON: 2166 printf("on\n"); 2167 break; 2168 case PCIE_SLCSR_IND_BLINK: 2169 printf("blink\n"); 2170 break; 2171 case PCIE_SLCSR_IND_OFF: 2172 printf("off\n"); 2173 break; 2174 } 2175 } 2176 if (slcap & PCIE_SLCAP_PIP) { 2177 printf(" Power Indicator Control: "); 2178 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2179 case 0x0: 2180 printf("reserved\n"); 2181 break; 2182 case PCIE_SLCSR_IND_ON: 2183 printf("on\n"); 2184 break; 2185 case PCIE_SLCSR_IND_BLINK: 2186 printf("blink\n"); 2187 break; 2188 case PCIE_SLCSR_IND_OFF: 2189 printf("off\n"); 2190 break; 2191 } 2192 } 2193 printf(" Power Controller Control: Power %s\n", 2194 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2195 onoff("Electromechanical Interlock Control", 2196 reg, PCIE_SLCSR_EIC); 2197 onoff("Data Link Layer State Changed Enable", reg, 2198 PCIE_SLCSR_DLLSCE); 2199 onoff("Auto Slot Power Limit Disable", reg, 2200 PCIE_SLCSR_AUTOSPLDIS); 2201 2202 /* Slot Status Register */ 2203 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2204 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2205 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2206 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2207 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2208 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2209 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2210 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2211 onoff("Electromechanical Interlock engaged", reg, 2212 PCIE_SLCSR_EIS); 2213 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2214 } 2215 2216 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2217 /* Root Control Register */ 2218 reg = regs[o2i(capoff + PCIE_RCR)]; 2219 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2220 onoff("SERR on Correctable Error Enable", reg, 2221 PCIE_RCR_SERR_CER); 2222 onoff("SERR on Non-Fatal Error Enable", reg, 2223 PCIE_RCR_SERR_NFER); 2224 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2225 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2226 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2227 2228 /* Root Capability Register */ 2229 printf(" Root Capability Register: 0x%04x\n", 2230 reg >> 16); 2231 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2232 2233 /* Root Status Register */ 2234 reg = regs[o2i(capoff + PCIE_RSR)]; 2235 printf(" Root Status Register: 0x%08x\n", reg); 2236 printf(" PME Requester ID: 0x%04x\n", 2237 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2238 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2239 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2240 } 2241 2242 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2243 if (pciever < 2) 2244 return; 2245 2246 /* Device Capabilities 2 */ 2247 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2248 printf(" Device Capabilities 2: 0x%08x\n", reg); 2249 printf(" Completion Timeout Ranges Supported: "); 2250 val = reg & PCIE_DCAP2_COMPT_RANGE; 2251 switch (val) { 2252 case 0: 2253 printf("not supported\n"); 2254 break; 2255 default: 2256 for (i = 0; i <= 3; i++) { 2257 if (((val >> i) & 0x01) != 0) 2258 printf("%c", 'A' + i); 2259 } 2260 printf("\n"); 2261 } 2262 onoff("Completion Timeout Disable Supported", reg, 2263 PCIE_DCAP2_COMPT_DIS); 2264 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2265 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2266 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2267 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2268 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2269 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2270 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2271 printf(" TPH Completer Supported: "); 2272 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2273 case 0: 2274 printf("Not supported\n"); 2275 break; 2276 case 1: 2277 printf("TPH\n"); 2278 break; 2279 case 3: 2280 printf("TPH and Extended TPH\n"); 2281 break; 2282 default: 2283 printf("(reserved value)\n"); 2284 break; 2285 } 2286 printf(" LN System CLS: "); 2287 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2288 case 0x0: 2289 printf("Not supported or not in effect\n"); 2290 break; 2291 case 0x1: 2292 printf("64byte cachelines in effect\n"); 2293 break; 2294 case 0x2: 2295 printf("128byte cachelines in effect\n"); 2296 break; 2297 case 0x3: 2298 printf("Reserved\n"); 2299 break; 2300 } 2301 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2302 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2303 printf(" OBFF Supported: "); 2304 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2305 case 0x0: 2306 printf("Not supported\n"); 2307 break; 2308 case 0x1: 2309 printf("Message only\n"); 2310 break; 2311 case 0x2: 2312 printf("WAKE# only\n"); 2313 break; 2314 case 0x3: 2315 printf("Both\n"); 2316 break; 2317 } 2318 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2319 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2320 val = PCIREG_SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2321 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2322 printf(" Emergency Power Reduction Supported: "); 2323 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2324 case 0x0: 2325 printf("Not supported\n"); 2326 break; 2327 case 0x1: 2328 printf("Device Specific mechanism\n"); 2329 break; 2330 case 0x2: 2331 printf("Form Factor spec or Device Specific mechanism\n"); 2332 break; 2333 case 0x3: 2334 printf("Reserved\n"); 2335 break; 2336 } 2337 onoff("Emergency Power Reduction Initialization Required", reg, 2338 PCIE_DCAP2_EMGPWRRED_INI); 2339 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2340 2341 /* Device Control 2 */ 2342 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2343 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2344 printf(" Completion Timeout Value: "); 2345 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2346 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2347 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2348 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2349 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2350 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2351 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2352 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2353 onoff("Emergency Power Reduction Request", reg, 2354 PCIE_DCSR2_EMGPWRRED_REQ); 2355 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2356 printf(" OBFF: "); 2357 switch (PCIREG_SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2358 case 0x0: 2359 printf("Disabled\n"); 2360 break; 2361 case 0x1: 2362 printf("Enabled with Message Signaling Variation A\n"); 2363 break; 2364 case 0x2: 2365 printf("Enabled with Message Signaling Variation B\n"); 2366 break; 2367 case 0x3: 2368 printf("Enabled using WAKE# signaling\n"); 2369 break; 2370 } 2371 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2372 2373 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2374 bool drs_supported = false; 2375 2376 /* Link Capability 2 */ 2377 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2378 /* If the vector is 0, LCAP2 is not implemented */ 2379 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2380 printf(" Link Capabilities 2: 0x%08x\n", reg); 2381 printf(" Supported Link Speeds Vector:"); 2382 pci_print_pcie_linkspeedvector( 2383 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2384 printf("\n"); 2385 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2386 printf(" " 2387 "Lower SKP OS Generation Supported Speed Vector:"); 2388 pci_print_pcie_linkspeedvector( 2389 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2390 printf("\n"); 2391 printf(" " 2392 "Lower SKP OS Reception Supported Speed Vector:"); 2393 pci_print_pcie_linkspeedvector( 2394 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2395 printf("\n"); 2396 onoff("Retimer Presence Detect Supported", reg, 2397 PCIE_LCAP2_RETIMERPD); 2398 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2399 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2400 } 2401 2402 /* Link Control 2 */ 2403 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2404 /* If the vector is 0, LCAP2 is not implemented */ 2405 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2406 printf(" Target Link Speed: "); 2407 pci_print_pcie_linkspeed(PCIE_LCSR2, 2408 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2409 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2410 onoff("HW Autonomous Speed Disabled", reg, 2411 PCIE_LCSR2_HW_AS_DIS); 2412 printf(" Selectable De-emphasis: "); 2413 pci_print_pcie_link_deemphasis( 2414 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2415 printf("\n"); 2416 printf(" Transmit Margin: %u\n", 2417 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2418 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2419 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2420 printf(" Compliance Preset/De-emphasis: "); 2421 pci_print_pcie_link_preset_preshoot_deemphasis( 2422 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2423 printf("\n"); 2424 2425 /* Link Status 2 */ 2426 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2427 printf(" Current De-emphasis Level: "); 2428 pci_print_pcie_link_deemphasis( 2429 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2430 printf("\n"); 2431 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2432 onoff("Equalization Phase 1 Successful", reg, 2433 PCIE_LCSR2_EQP1_SUC); 2434 onoff("Equalization Phase 2 Successful", reg, 2435 PCIE_LCSR2_EQP2_SUC); 2436 onoff("Equalization Phase 3 Successful", reg, 2437 PCIE_LCSR2_EQP3_SUC); 2438 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2439 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2440 if (drs_supported) { 2441 printf(" Downstream Component Presence: "); 2442 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2443 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2444 printf("Link Down - Presence Not" 2445 " Determined\n"); 2446 break; 2447 case PCIE_DSCOMPN_DOWN_NOTPRES: 2448 printf("Link Down - Component Not Present\n"); 2449 break; 2450 case PCIE_DSCOMPN_DOWN_PRES: 2451 printf("Link Down - Component Present\n"); 2452 break; 2453 case PCIE_DSCOMPN_UP_PRES: 2454 printf("Link Up - Component Present\n"); 2455 break; 2456 case PCIE_DSCOMPN_UP_PRES_DRS: 2457 printf("Link Up - Component Present and DRS" 2458 " received\n"); 2459 break; 2460 default: 2461 printf("reserved\n"); 2462 break; 2463 } 2464 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2465 } 2466 } 2467 2468 /* Slot Capability 2 */ 2469 /* Slot Control 2 */ 2470 /* Slot Status 2 */ 2471 } 2472 2473 static void 2474 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2475 { 2476 pcireg_t reg; 2477 2478 printf("\n MSI-X Capability Register\n"); 2479 2480 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2481 printf(" Message Control register: 0x%04x\n", 2482 (reg >> 16) & 0xff); 2483 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2484 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2485 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2486 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2487 printf(" Table offset register: 0x%08x\n", reg); 2488 printf(" Table offset: 0x%08x\n", 2489 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2490 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2491 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2492 printf(" Pending bit array register: 0x%08x\n", reg); 2493 printf(" Pending bit array offset: 0x%08x\n", 2494 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2495 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2496 } 2497 2498 static void 2499 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2500 { 2501 pcireg_t reg; 2502 2503 printf("\n Serial ATA Capability Register\n"); 2504 2505 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2506 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2507 printf(" Revision: %u.%u\n", 2508 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2509 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2510 2511 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2512 2513 printf(" BAR Register: 0x%08x\n", reg); 2514 printf(" Register location: "); 2515 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2516 printf("in config space\n"); 2517 else { 2518 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2519 printf(" BAR offset: 0x%08x\n", 2520 PCIREG_SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2521 } 2522 } 2523 2524 static void 2525 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2526 { 2527 pcireg_t reg; 2528 2529 printf("\n Advanced Features Capability Register\n"); 2530 2531 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2532 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2533 printf(" AF Structure Length: 0x%02x\n", 2534 PCIREG_SHIFTOUT(reg, PCI_AF_LENGTH)); 2535 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2536 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2537 reg = regs[o2i(capoff + PCI_AFCSR)]; 2538 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2539 /* 2540 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2541 * and it's always 0 on read 2542 */ 2543 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2544 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2545 } 2546 2547 static void 2548 pci_conf_print_ea_cap_prop(unsigned int prop) 2549 { 2550 2551 switch (prop) { 2552 case PCI_EA_PROP_MEM_NONPREF: 2553 printf("Memory Space, Non-Prefetchable\n"); 2554 break; 2555 case PCI_EA_PROP_MEM_PREF: 2556 printf("Memory Space, Prefetchable\n"); 2557 break; 2558 case PCI_EA_PROP_IO: 2559 printf("I/O Space\n"); 2560 break; 2561 case PCI_EA_PROP_VF_MEM_NONPREF: 2562 printf("Resource for VF use, Memory Space, Non-Prefetchable\n"); 2563 break; 2564 case PCI_EA_PROP_VF_MEM_PREF: 2565 printf("Resource for VF use, Memory Space, Prefetch\n"); 2566 break; 2567 case PCI_EA_PROP_BB_MEM_NONPREF: 2568 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2569 break; 2570 case PCI_EA_PROP_BB_MEM_PREF: 2571 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2572 break; 2573 case PCI_EA_PROP_BB_IO: 2574 printf("Behind Bridge, I/O Space\n"); 2575 break; 2576 case PCI_EA_PROP_MEM_UNAVAIL: 2577 printf("Memory Space Unavailable\n"); 2578 break; 2579 case PCI_EA_PROP_IO_UNAVAIL: 2580 printf("IO Space Unavailable\n"); 2581 break; 2582 case PCI_EA_PROP_UNAVAIL: 2583 printf("Entry Unavailable for use\n"); 2584 break; 2585 default: 2586 printf("Reserved\n"); 2587 break; 2588 } 2589 } 2590 2591 static void 2592 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2593 { 2594 pcireg_t reg, reg2; 2595 unsigned int entries, entoff, i; 2596 2597 printf("\n Enhanced Allocation Capability Register\n"); 2598 2599 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2600 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2601 entries = PCIREG_SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2602 printf(" EA Num Entries: %u\n", entries); 2603 2604 /* Type 1 only */ 2605 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2606 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2607 printf(" EA Capability Second register: 0x%08x\n", reg); 2608 printf(" Fixed Secondary Bus Number: %hhu\n", 2609 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2610 printf(" Fixed Subordinate Bus Number: %hhu\n", 2611 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2612 entoff = capoff + 8; 2613 } else 2614 entoff = capoff + 4; 2615 2616 for (i = 0; i < entries; i++) { 2617 uint64_t base, offset; 2618 bool baseis64, offsetis64; 2619 unsigned int bei, entry_size; 2620 2621 printf(" Entry %u:\n", i); 2622 /* The first DW */ 2623 reg = regs[o2i(entoff)]; 2624 printf(" The first register: 0x%08x\n", reg); 2625 entry_size = PCIREG_SHIFTOUT(reg, PCI_EA_ES); 2626 printf(" Entry size: %u\n", entry_size); 2627 printf(" BAR Equivalent Indicator: "); 2628 bei = PCIREG_SHIFTOUT(reg, PCI_EA_BEI); 2629 switch (bei) { 2630 case PCI_EA_BEI_BAR0: 2631 case PCI_EA_BEI_BAR1: 2632 case PCI_EA_BEI_BAR2: 2633 case PCI_EA_BEI_BAR3: 2634 case PCI_EA_BEI_BAR4: 2635 case PCI_EA_BEI_BAR5: 2636 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2637 break; 2638 case PCI_EA_BEI_BEHIND: 2639 printf("Behind the function\n"); 2640 break; 2641 case PCI_EA_BEI_NOTIND: 2642 printf("Not Indicated\n"); 2643 break; 2644 case PCI_EA_BEI_EXPROM: 2645 printf("Expansion ROM\n"); 2646 break; 2647 case PCI_EA_BEI_VFBAR0: 2648 case PCI_EA_BEI_VFBAR1: 2649 case PCI_EA_BEI_VFBAR2: 2650 case PCI_EA_BEI_VFBAR3: 2651 case PCI_EA_BEI_VFBAR4: 2652 case PCI_EA_BEI_VFBAR5: 2653 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2654 break; 2655 case PCI_EA_BEI_RESERVED: 2656 default: 2657 printf("Reserved\n"); 2658 break; 2659 } 2660 2661 printf(" Primary Properties: "); 2662 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_PP)); 2663 printf(" Secondary Properties: "); 2664 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_SP)); 2665 onoff("Writable", reg, PCI_EA_W); 2666 onoff("Enable for this entry", reg, PCI_EA_E); 2667 2668 if (entry_size == 0) { 2669 entoff += 4; 2670 continue; 2671 } 2672 2673 /* Base addr */ 2674 reg = regs[o2i(entoff + 4)]; 2675 base = reg & PCI_EA_LOWMASK; 2676 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2677 printf(" Base Address Register Low: 0x%08x\n", reg); 2678 if (baseis64) { 2679 /* 64bit */ 2680 reg2 = regs[o2i(entoff + 12)]; 2681 printf(" Base Address Register high: 0x%08x\n", 2682 reg2); 2683 base |= (uint64_t)reg2 << 32; 2684 } 2685 2686 /* Offset addr */ 2687 reg = regs[o2i(entoff + 8)]; 2688 offset = reg & PCI_EA_LOWMASK; 2689 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2690 printf(" Max Offset Register Low: 0x%08x\n", reg); 2691 if (offsetis64) { 2692 /* 64bit */ 2693 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2694 printf(" Max Offset Register high: 0x%08x\n", 2695 reg2); 2696 offset |= (uint64_t)reg2 << 32; 2697 } 2698 2699 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2700 "\n", base, base + offset); 2701 2702 entoff += 4 + (4 * entry_size); 2703 } 2704 } 2705 2706 /* XXX pci_conf_print_fpb_cap */ 2707 2708 static struct { 2709 pcireg_t cap; 2710 const char *name; 2711 void (*printfunc)(const pcireg_t *, int); 2712 } pci_captab[] = { 2713 { PCI_CAP_RESERVED0, "reserved", NULL }, 2714 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2715 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2716 { PCI_CAP_VPD, "VPD", NULL }, 2717 { PCI_CAP_SLOTID, "SlotID", NULL }, 2718 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2719 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2720 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2721 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2722 { PCI_CAP_VENDSPEC, "Vendor-specific", 2723 pci_conf_print_vendspec_cap }, 2724 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2725 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2726 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2727 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2728 pci_conf_print_subsystem_cap }, 2729 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2730 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2731 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2732 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2733 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2734 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2735 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2736 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2737 }; 2738 2739 static int 2740 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2741 { 2742 pcireg_t rval; 2743 unsigned int capptr; 2744 int off; 2745 2746 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2747 return 0; 2748 2749 /* Determine the Capability List Pointer register to start with. */ 2750 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2751 case 0: /* standard device header */ 2752 case 1: /* PCI-PCI bridge header */ 2753 capptr = PCI_CAPLISTPTR_REG; 2754 break; 2755 case 2: /* PCI-CardBus Bridge header */ 2756 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2757 break; 2758 default: 2759 return 0; 2760 } 2761 2762 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2763 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2764 rval = regs[o2i(off)]; 2765 if (capid == PCI_CAPLIST_CAP(rval)) { 2766 if (offsetp != NULL) 2767 *offsetp = off; 2768 return 1; 2769 } 2770 } 2771 return 0; 2772 } 2773 2774 static void 2775 pci_conf_print_caplist( 2776 #ifdef _KERNEL 2777 pci_chipset_tag_t pc, pcitag_t tag, 2778 #endif 2779 const pcireg_t *regs, int capoff) 2780 { 2781 int off; 2782 pcireg_t foundcap; 2783 pcireg_t rval; 2784 bool foundtable[__arraycount(pci_captab)]; 2785 unsigned int i; 2786 2787 /* Clear table */ 2788 for (i = 0; i < __arraycount(pci_captab); i++) 2789 foundtable[i] = false; 2790 2791 /* Print capability register's offset and the type first */ 2792 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2793 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2794 rval = regs[o2i(off)]; 2795 printf(" Capability register at 0x%02x\n", off); 2796 2797 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2798 foundcap = PCI_CAPLIST_CAP(rval); 2799 if (foundcap < __arraycount(pci_captab)) { 2800 printf("%s)\n", pci_captab[foundcap].name); 2801 /* Mark as found */ 2802 foundtable[foundcap] = true; 2803 } else 2804 printf("unknown)\n"); 2805 } 2806 2807 /* 2808 * And then, print the detail of each capability registers 2809 * in capability value's order. 2810 */ 2811 for (i = 0; i < __arraycount(pci_captab); i++) { 2812 if (foundtable[i] == false) 2813 continue; 2814 2815 /* 2816 * The type was found. Search capability list again and 2817 * print all capabilities that the capability type is 2818 * the same. This is required because some capabilities 2819 * appear multiple times (e.g. HyperTransport capability). 2820 */ 2821 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2822 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2823 rval = regs[o2i(off)]; 2824 if ((PCI_CAPLIST_CAP(rval) == i) 2825 && (pci_captab[i].printfunc != NULL)) 2826 pci_captab[i].printfunc(regs, off); 2827 } 2828 } 2829 } 2830 2831 /* Extended Capability */ 2832 2833 static void 2834 pci_conf_print_aer_cap_uc(pcireg_t reg) 2835 { 2836 2837 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2838 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2839 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2840 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2841 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2842 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2843 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2844 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2845 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2846 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2847 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2848 onoff("Unsupported Request Error", reg, 2849 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2850 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2851 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2852 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2853 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2854 onoff("TLP Prefix Blocked Error", reg, 2855 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2856 onoff("Poisoned TLP Egress Blocked", reg, 2857 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2858 } 2859 2860 static void 2861 pci_conf_print_aer_cap_cor(pcireg_t reg) 2862 { 2863 2864 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2865 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2866 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2867 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2868 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2869 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2870 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2871 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2872 } 2873 2874 static void 2875 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2876 { 2877 2878 printf(" First Error Pointer: 0x%04x\n", 2879 PCIREG_SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2880 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2881 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2882 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2883 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2884 onoff("Multiple Header Recording Capable", reg, 2885 PCI_AER_MULT_HDR_CAPABLE); 2886 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2887 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2888 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2889 2890 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2891 if (!tlp_prefix_log) 2892 return; 2893 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2894 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2895 } 2896 2897 static void 2898 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2899 { 2900 2901 onoff("Correctable Error Reporting Enable", reg, 2902 PCI_AER_ROOTERR_COR_ENABLE); 2903 onoff("Non-Fatal Error Reporting Enable", reg, 2904 PCI_AER_ROOTERR_NF_ENABLE); 2905 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2906 } 2907 2908 static void 2909 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2910 { 2911 2912 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2913 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2914 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2915 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2916 PCI_AER_ROOTERR_MULTI_UC_ERR); 2917 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2918 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2919 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2920 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2921 PCIREG_SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2922 } 2923 2924 static void 2925 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2926 { 2927 2928 printf(" Correctable Source ID: 0x%04x\n", 2929 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2930 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2931 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2932 } 2933 2934 static void 2935 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2936 { 2937 pcireg_t reg; 2938 int pcie_capoff; 2939 int pcie_devtype = -1; 2940 bool tlp_prefix_log = false; 2941 2942 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2943 reg = regs[o2i(pcie_capoff)]; 2944 pcie_devtype = PCIE_XCAP_TYPE(reg); 2945 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2946 if (PCIREG_SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2947 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2948 /* End-End TLP Prefix Supported */ 2949 if (reg & PCIE_DCAP2_EETLP_PREF) { 2950 tlp_prefix_log = true; 2951 } 2952 } 2953 } 2954 2955 printf("\n Advanced Error Reporting Register\n"); 2956 2957 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2958 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2959 pci_conf_print_aer_cap_uc(reg); 2960 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2961 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2962 pci_conf_print_aer_cap_uc(reg); 2963 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2964 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2965 pci_conf_print_aer_cap_uc(reg); 2966 2967 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2968 printf(" Correctable Error Status register: 0x%08x\n", reg); 2969 pci_conf_print_aer_cap_cor(reg); 2970 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2971 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2972 pci_conf_print_aer_cap_cor(reg); 2973 2974 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2975 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2976 reg); 2977 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2978 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2979 printf(" Header Log register:\n"); 2980 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2981 extcapoff + PCI_AER_ROOTERR_CMD); 2982 2983 switch (pcie_devtype) { 2984 case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */ 2985 case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */ 2986 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2987 printf(" Root Error Command register: 0x%08x\n", reg); 2988 pci_conf_print_aer_cap_rooterr_cmd(reg); 2989 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2990 printf(" Root Error Status register: 0x%08x\n", reg); 2991 pci_conf_print_aer_cap_rooterr_status(reg); 2992 2993 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2994 printf(" Error Source Identification register: 0x%08x\n", 2995 reg); 2996 pci_conf_print_aer_cap_errsrc_id(reg); 2997 break; 2998 } 2999 3000 if (tlp_prefix_log) { 3001 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 3002 printf(" TLP Prefix Log register: 0x%08x\n", reg); 3003 } 3004 } 3005 3006 /* 3007 * Helper function to print the arbitration phase register. 3008 * 3009 * phases: Number of phases in the arbitration tables. 3010 * arbsize: Number of bits in each phase. 3011 * indent: Add more two spaces if it's true. 3012 */ 3013 static void 3014 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 3015 const int phases, int arbsize, bool indent) 3016 { 3017 pcireg_t reg; 3018 int num_per_reg = 32 / arbsize; 3019 int i, j; 3020 3021 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 3022 for (i = 0; i < phases; i += num_per_reg) { 3023 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 3024 for (j = 0; j < num_per_reg; j++) { 3025 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 3026 i + j, 3027 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 3028 reg >>= arbsize; 3029 } 3030 } 3031 } 3032 3033 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 3034 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 3035 3036 static void 3037 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 3038 { 3039 pcireg_t reg, n; 3040 int arbtab, parbsize; 3041 pcireg_t arbsel; 3042 int i, count; 3043 3044 printf("\n Virtual Channel Register\n"); 3045 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 3046 printf(" Port VC Capability register 1: 0x%08x\n", reg); 3047 count = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 3048 printf(" Extended VC Count: %d\n", count); 3049 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 3050 printf(" Low Priority Extended VC Count: %u\n", n); 3051 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 3052 printf(" Reference Clock: %s\n", 3053 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 3054 parbsize = 1 << PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 3055 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 3056 3057 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 3058 printf(" Port VC Capability register 2: 0x%08x\n", reg); 3059 onoff("Hardware fixed arbitration scheme", 3060 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 3061 onoff("WRR arbitration with 32 phases", 3062 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 3063 onoff("WRR arbitration with 64 phases", 3064 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 3065 onoff("WRR arbitration with 128 phases", 3066 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 3067 arbtab = PCIREG_SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 3068 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 3069 3070 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 3071 printf(" Port VC Control register: 0x%04x\n", reg); 3072 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 3073 printf(" VC Arbitration Select: 0x%x\n", arbsel); 3074 3075 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 3076 printf(" Port VC Status register: 0x%04x\n", reg); 3077 onoff("VC Arbitration Table Status", 3078 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 3079 3080 if ((arbtab != 0) && (arbsel != 0)) 3081 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 3082 "VC", arb_phases[arbsel], 4, false); 3083 3084 for (i = 0; i < count + 1; i++) { 3085 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 3086 printf(" VC number %d\n", i); 3087 printf(" VC Resource Capability Register: 0x%08x\n", reg); 3088 onoff(" Non-configurable Hardware fixed arbitration scheme", 3089 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 3090 onoff(" WRR arbitration with 32 phases", 3091 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 3092 onoff(" WRR arbitration with 64 phases", 3093 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 3094 onoff(" WRR arbitration with 128 phases", 3095 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 3096 onoff(" Time-based WRR arbitration with 128 phases", 3097 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 3098 onoff(" WRR arbitration with 256 phases", 3099 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 3100 onoff(" Advanced Packet Switching", 3101 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 3102 onoff(" Reject Snoop Transaction", 3103 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 3104 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 3105 printf(" Maximum Time Slots: %d\n", n); 3106 arbtab = PCIREG_SHIFTOUT(reg, 3107 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 3108 printf(" Port Arbitration Table offset: 0x%02x\n", 3109 arbtab); 3110 3111 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 3112 printf(" VC Resource Control Register: 0x%08x\n", reg); 3113 printf(" TC/VC Map: 0x%02x\n", 3114 PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 3115 /* 3116 * The load Port Arbitration Table bit is used to update 3117 * the Port Arbitration logic and it's always 0 on read, so 3118 * we don't print it. 3119 */ 3120 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 3121 printf(" Port Arbitration Select: 0x%x\n", arbsel); 3122 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 3123 printf(" VC ID: %d\n", n); 3124 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 3125 3126 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 3127 printf(" VC Resource Status Register: 0x%08x\n", reg); 3128 onoff(" Port Arbitration Table Status", 3129 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 3130 onoff(" VC Negotiation Pending", 3131 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3132 3133 if ((arbtab != 0) && (arbsel != 0)) 3134 pci_conf_print_vc_cap_arbtab(regs, 3135 extcapoff + (arbtab * 16), 3136 "Port", arb_phases[arbsel], parbsize, true); 3137 } 3138 } 3139 3140 /* 3141 * Print Power limit. This encoding is the same among the following registers: 3142 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3143 * - The Slot Power Limit in the PCIe Slot Capability Register. 3144 * - The Base Power in the Data register of Power Budgeting capability. 3145 */ 3146 static void 3147 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3148 { 3149 unsigned int sdiv = 1; 3150 3151 if ((scale == 0) && (base > 0xef)) { 3152 const char *s; 3153 3154 switch (base) { 3155 case 0xf0: 3156 s = "239W < x <= 250W"; 3157 break; 3158 case 0xf1: 3159 s = "250W < x <= 275W"; 3160 break; 3161 case 0xf2: 3162 s = "275W < x <= 300W"; 3163 break; 3164 default: 3165 s = "reserved for greater than 300W"; 3166 break; 3167 } 3168 printf("%s\n", s); 3169 return; 3170 } 3171 3172 for (unsigned int i = scale; i > 0; i--) 3173 sdiv *= 10; 3174 3175 printf("%u", base / sdiv); 3176 3177 if (scale != 0) { 3178 printf(".%u", base % sdiv); 3179 } 3180 printf ("W\n"); 3181 return; 3182 } 3183 3184 static const char * 3185 pci_conf_print_pwrbdgt_type(uint8_t reg) 3186 { 3187 3188 switch (reg) { 3189 case 0x00: 3190 return "PME Aux"; 3191 case 0x01: 3192 return "Auxilary"; 3193 case 0x02: 3194 return "Idle"; 3195 case 0x03: 3196 return "Sustained"; 3197 case 0x04: 3198 return "Sustained (Emergency Power Reduction)"; 3199 case 0x05: 3200 return "Maximum (Emergency Power Reduction)"; 3201 case 0x07: 3202 return "Maximum"; 3203 default: 3204 return "Unknown"; 3205 } 3206 } 3207 3208 static const char * 3209 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3210 { 3211 3212 switch (reg) { 3213 case 0x00: 3214 return "Power(12V)"; 3215 case 0x01: 3216 return "Power(3.3V)"; 3217 case 0x02: 3218 return "Power(1.5V or 1.8V)"; 3219 case 0x07: 3220 return "Thermal"; 3221 default: 3222 return "Unknown"; 3223 } 3224 } 3225 3226 static void 3227 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3228 { 3229 pcireg_t reg; 3230 3231 printf("\n Power Budgeting\n"); 3232 3233 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3234 printf(" Data Select register: 0x%08x\n", reg); 3235 3236 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3237 printf(" Data register: 0x%08x\n", reg); 3238 printf(" Base Power: "); 3239 pci_conf_print_pcie_power( 3240 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3241 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3242 printf(" PM Sub State: 0x%hhx\n", 3243 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3244 printf(" PM State: D%u\n", 3245 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3246 printf(" Type: %s\n", 3247 pci_conf_print_pwrbdgt_type( 3248 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3249 printf(" Power Rail: %s\n", 3250 pci_conf_print_pwrbdgt_pwrrail( 3251 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3252 3253 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3254 printf(" Power Budget Capability register: 0x%08x\n", reg); 3255 onoff("System Allocated", 3256 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3257 } 3258 3259 static const char * 3260 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3261 { 3262 3263 switch (type) { 3264 case 0x00: 3265 return "Configuration Space Element"; 3266 case 0x01: 3267 return "System Egress Port or internal sink (memory)"; 3268 case 0x02: 3269 return "Internal Root Complex Link"; 3270 default: 3271 return "Unknown"; 3272 } 3273 } 3274 3275 static void 3276 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3277 { 3278 pcireg_t reg; 3279 unsigned char nent, linktype; 3280 int i; 3281 3282 printf("\n Root Complex Link Declaration\n"); 3283 3284 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3285 printf(" Element Self Description Register: 0x%08x\n", reg); 3286 printf(" Element Type: %s\n", 3287 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3288 nent = PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3289 printf(" Number of Link Entries: %hhu\n", nent); 3290 printf(" Component ID: %hhu\n", 3291 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3292 printf(" Port Number: %hhu\n", 3293 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3294 for (i = 0; i < nent; i++) { 3295 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3296 printf(" Link Entry %d:\n", i + 1); 3297 printf(" Link Description Register: 0x%08x\n", reg); 3298 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3299 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3300 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3301 "Configuration Space", "Memory-Mapped Space"); 3302 onoff(" Associated RCRB Header", reg, 3303 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3304 printf(" Target Component ID: %hhu\n", 3305 (uint8_t)PCIREG_SHIFTOUT(reg, 3306 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3307 printf(" Target Port Number: %hhu\n", 3308 (uint8_t)PCIREG_SHIFTOUT(reg, 3309 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3310 3311 if (linktype == 0) { 3312 /* Memory-Mapped Space */ 3313 reg = regs[o2i(extcapoff 3314 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3315 printf(" Link Address Low Register: 0x%08x\n", 3316 reg); 3317 reg = regs[o2i(extcapoff 3318 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3319 printf(" Link Address High Register: 0x%08x\n", 3320 reg); 3321 } else { 3322 unsigned int nb; 3323 pcireg_t lo, hi; 3324 3325 /* Configuration Space */ 3326 lo = regs[o2i(extcapoff 3327 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3328 printf(" Configuration Space Low Register: " 3329 "0x%08x\n", lo); 3330 hi = regs[o2i(extcapoff 3331 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3332 printf(" Configuration Space High Register: " 3333 "0x%08x\n", hi); 3334 nb = PCIREG_SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3335 printf(" N: %u\n", nb); 3336 printf(" Func: %hhu\n", 3337 (uint8_t)PCIREG_SHIFTOUT(lo, 3338 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3339 printf(" Dev: %hhu\n", 3340 (uint8_t)PCIREG_SHIFTOUT(lo, 3341 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3342 printf(" Bus: %hhu\n", 3343 (uint8_t)PCIREG_SHIFTOUT(lo, 3344 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3345 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3346 printf(" Configuration Space Base Address: " 3347 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3348 } 3349 } 3350 } 3351 3352 /* XXX pci_conf_print_rclink_ctl_cap */ 3353 3354 static void 3355 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3356 { 3357 pcireg_t reg; 3358 3359 printf("\n Root Complex Event Collector Association\n"); 3360 3361 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3362 printf(" Association Bitmap for Root Complex Integrated Devices:" 3363 " 0x%08x\n", reg); 3364 3365 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3366 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3367 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3368 reg); 3369 printf(" RCEC Next Bus: %u\n", 3370 PCIREG_SHIFTOUT(reg, 3371 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3372 printf(" RCEC Last Bus: %u\n", 3373 PCIREG_SHIFTOUT(reg, 3374 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3375 } 3376 } 3377 3378 /* XXX pci_conf_print_mfvc_cap */ 3379 /* XXX pci_conf_print_vc2_cap */ 3380 /* XXX pci_conf_print_rcrb_cap */ 3381 /* XXX pci_conf_print_vendor_cap */ 3382 /* XXX pci_conf_print_cac_cap */ 3383 3384 static void 3385 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3386 { 3387 pcireg_t reg, cap, ctl; 3388 unsigned int size, i; 3389 3390 printf("\n Access Control Services\n"); 3391 3392 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3393 cap = reg & 0xffff; 3394 ctl = reg >> 16; 3395 printf(" ACS Capability register: 0x%08x\n", cap); 3396 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3397 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3398 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3399 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3400 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3401 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3402 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3403 size = PCIREG_SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3404 if (size == 0) 3405 size = 256; 3406 printf(" Egress Control Vector Size: %u\n", size); 3407 printf(" ACS Control register: 0x%08x\n", ctl); 3408 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3409 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3410 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3411 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3412 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3413 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3414 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3415 3416 /* 3417 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3418 * Control vector. 3419 */ 3420 if ((cap & PCI_ACS_CAP_E) == 0) 3421 return; 3422 for (i = 0; i < size; i += 32) 3423 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3424 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3425 } 3426 3427 static void 3428 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3429 { 3430 pcireg_t reg, cap, ctl; 3431 3432 printf("\n Alternative Routing-ID Interpretation Register\n"); 3433 3434 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3435 cap = reg & 0xffff; 3436 ctl = reg >> 16; 3437 printf(" Capability register: 0x%08x\n", cap); 3438 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3439 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3440 printf(" Next Function Number: %u\n", 3441 PCIREG_SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3442 printf(" Control register: 0x%08x\n", ctl); 3443 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3444 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3445 printf(" Function Group: %u\n", 3446 PCIREG_SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3447 } 3448 3449 static void 3450 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3451 { 3452 pcireg_t reg, cap, ctl; 3453 unsigned int num; 3454 3455 printf("\n Address Translation Services\n"); 3456 3457 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3458 cap = reg & 0xffff; 3459 ctl = reg >> 16; 3460 printf(" Capability register: 0x%04x\n", cap); 3461 num = PCIREG_SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3462 if (num == 0) 3463 num = 32; 3464 printf(" Invalidate Queue Depth: %u\n", num); 3465 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3466 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3467 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3468 3469 printf(" Control register: 0x%04x\n", ctl); 3470 printf(" Smallest Translation Unit: %u\n", 3471 PCIREG_SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3472 onoff("Enable", reg, PCI_ATS_CTL_EN); 3473 } 3474 3475 static void 3476 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3477 { 3478 pcireg_t lo, hi; 3479 3480 printf("\n Device Serial Number Register\n"); 3481 3482 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3483 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3484 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3485 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3486 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3487 } 3488 3489 static void 3490 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3491 { 3492 char buf[sizeof("99999 MB")]; 3493 pcireg_t reg; 3494 pcireg_t total_vfs; 3495 int i; 3496 bool first; 3497 3498 printf("\n Single Root IO Virtualization Register\n"); 3499 3500 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3501 printf(" Capabilities register: 0x%08x\n", reg); 3502 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3503 onoff("ARI Capable Hierarchy Preserved", reg, 3504 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3505 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3506 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3507 PCIREG_SHIFTOUT(reg, PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3508 } 3509 3510 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3511 printf(" Control register: 0x%04x\n", reg); 3512 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3513 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3514 onoff("VF Migration Interrupt Enable", reg, 3515 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3516 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3517 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3518 3519 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3520 printf(" Status register: 0x%04x\n", reg); 3521 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3522 3523 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3524 printf(" InitialVFs register: 0x%04x\n", reg); 3525 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3526 printf(" TotalVFs register: 0x%04x\n", reg); 3527 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3528 printf(" NumVFs register: 0x%04x\n", reg); 3529 3530 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3531 printf(" Function Dependency Link register: 0x%04x\n", reg); 3532 3533 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3534 printf(" First VF Offset register: 0x%04x\n", reg); 3535 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3536 printf(" VF Stride register: 0x%04x\n", reg); 3537 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3538 printf(" Device ID: 0x%04x\n", reg); 3539 3540 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3541 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3542 printf(" Supported Page Size:"); 3543 for (i = 0, first = true; i < 32; i++) { 3544 if (reg & __BIT(i)) { 3545 #ifdef _KERNEL 3546 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3547 #else 3548 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3549 HN_AUTOSCALE, 0); 3550 #endif 3551 printf("%s %s", first ? "" : ",", buf); 3552 first = false; 3553 } 3554 } 3555 printf("\n"); 3556 3557 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3558 printf(" System Page Sizes register: 0x%08x\n", reg); 3559 printf(" Page Size: "); 3560 if (reg != 0) { 3561 int bitpos = ffs(reg) -1; 3562 3563 /* Assume only one bit is set. */ 3564 #ifdef _KERNEL 3565 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3566 #else 3567 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3568 "B", HN_AUTOSCALE, 0); 3569 #endif 3570 printf("%s", buf); 3571 } else { 3572 printf("unknown"); 3573 } 3574 printf("\n"); 3575 3576 for (i = 0; i < 6; i++) { 3577 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3578 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3579 } 3580 3581 if (total_vfs > 0) { 3582 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3583 printf(" VF Migration State Array Offset register: 0x%08x\n", 3584 reg); 3585 printf(" VF Migration State Offset: 0x%08x\n", 3586 PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3587 i = PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3588 printf(" VF Migration State BIR: "); 3589 if (i >= 0 && i <= 5) { 3590 printf("BAR%d", i); 3591 } else { 3592 printf("unknown BAR (%d)", i); 3593 } 3594 printf("\n"); 3595 } 3596 } 3597 3598 /* XXX pci_conf_print_mriov_cap */ 3599 3600 static void 3601 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3602 { 3603 pcireg_t reg, cap, ctl; 3604 pcireg_t regl, regh; 3605 uint64_t addr; 3606 int n; 3607 3608 printf("\n Multicast\n"); 3609 3610 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3611 cap = reg & 0xffff; 3612 ctl = reg >> 16; 3613 printf(" Capability Register: 0x%04x\n", cap); 3614 printf(" Max Group: %u\n", 3615 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3616 3617 /* Endpoint Only */ 3618 n = PCIREG_SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3619 if (n > 0) 3620 printf(" Window Size Requested: %d\n", 1 << (n - 1)); 3621 3622 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3623 3624 printf(" Control Register: 0x%04x\n", ctl); 3625 printf(" Num Group: %u\n", 3626 PCIREG_SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3627 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3628 3629 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3630 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3631 printf(" Base Address Register 0: 0x%08x\n", regl); 3632 printf(" Base Address Register 1: 0x%08x\n", regh); 3633 printf(" Index Position: %u\n", 3634 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3635 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3636 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3637 3638 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3639 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3640 printf(" Receive Register 0: 0x%08x\n", regl); 3641 printf(" Receive Register 1: 0x%08x\n", regh); 3642 3643 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3644 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3645 printf(" Block All Register 0: 0x%08x\n", regl); 3646 printf(" Block All Register 1: 0x%08x\n", regh); 3647 3648 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3649 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3650 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3651 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3652 3653 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3654 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3655 printf(" Overlay BAR 0: 0x%08x\n", regl); 3656 printf(" Overlay BAR 1: 0x%08x\n", regh); 3657 3658 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3659 printf(" Overlay Size: "); 3660 if (n >= 6) 3661 printf("%d\n", n); 3662 else 3663 printf("off\n"); 3664 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3665 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3666 } 3667 3668 static void 3669 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3670 { 3671 pcireg_t reg, ctl, sta; 3672 3673 printf("\n Page Request\n"); 3674 3675 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3676 ctl = reg & 0xffff; 3677 sta = reg >> 16; 3678 printf(" Control Register: 0x%04x\n", ctl); 3679 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3680 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3681 3682 printf(" Status Register: 0x%04x\n", sta); 3683 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3684 onoff("Unexpected Page Request Group Index", reg, 3685 PCI_PAGE_REQ_STA_UPRGI); 3686 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3687 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3688 3689 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3690 printf(" Outstanding Page Request Capacity: %u\n", reg); 3691 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3692 printf(" Outstanding Page Request Allocation: %u\n", reg); 3693 } 3694 3695 /* XXX pci_conf_print_amd_cap */ 3696 3697 #define MEM_PBUFSIZE sizeof("999GB") 3698 3699 static void 3700 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3701 { 3702 pcireg_t cap, ctl; 3703 unsigned int bars, i, n; 3704 char pbuf[MEM_PBUFSIZE]; 3705 3706 printf("\n Resizable BAR\n"); 3707 3708 /* Get Number of Resizable BARs */ 3709 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3710 bars = PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3711 printf(" Number of Resizable BARs: "); 3712 if (bars <= 6) 3713 printf("%u\n", bars); 3714 else { 3715 printf("incorrect (%u)\n", bars); 3716 return; 3717 } 3718 3719 for (n = 0; n < 6; n++) { 3720 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3721 printf(" Capability register(%u): 0x%08x\n", n, cap); 3722 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3723 continue; /* Not Used */ 3724 printf(" Acceptable BAR sizes:"); 3725 for (i = 4; i <= 23; i++) { 3726 if ((cap & (1 << i)) != 0) { 3727 humanize_number(pbuf, MEM_PBUFSIZE, 3728 (int64_t)1024 * 1024 << (i - 4), "B", 3729 #ifdef _KERNEL 3730 1); 3731 #else 3732 HN_AUTOSCALE, HN_NOSPACE); 3733 #endif 3734 printf(" %s", pbuf); 3735 } 3736 } 3737 printf("\n"); 3738 3739 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3740 printf(" Control register(%u): 0x%08x\n", n, ctl); 3741 printf(" BAR Index: %u\n", 3742 PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3743 humanize_number(pbuf, MEM_PBUFSIZE, 3744 (int64_t)1024 * 1024 3745 << PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3746 "B", 3747 #ifdef _KERNEL 3748 1); 3749 #else 3750 HN_AUTOSCALE, HN_NOSPACE); 3751 #endif 3752 printf(" BAR Size: %s\n", pbuf); 3753 } 3754 } 3755 3756 static void 3757 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3758 { 3759 pcireg_t reg; 3760 unsigned int substmax, i; 3761 3762 printf("\n Dynamic Power Allocation\n"); 3763 3764 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3765 printf(" Capability register: 0x%08x\n", reg); 3766 substmax = PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3767 printf(" Substate Max: %u\n", substmax); 3768 printf(" Transition Latency Unit: "); 3769 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3770 case 0: 3771 printf("1ms\n"); 3772 break; 3773 case 1: 3774 printf("10ms\n"); 3775 break; 3776 case 2: 3777 printf("100ms\n"); 3778 break; 3779 default: 3780 printf("reserved\n"); 3781 break; 3782 } 3783 printf(" Power Allocation Scale: "); 3784 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3785 case 0: 3786 printf("10.0x\n"); 3787 break; 3788 case 1: 3789 printf("1.0x\n"); 3790 break; 3791 case 2: 3792 printf("0.1x\n"); 3793 break; 3794 case 3: 3795 printf("0.01x\n"); 3796 break; 3797 } 3798 printf(" Transition Latency Value 0: %u\n", 3799 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3800 printf(" Transition Latency Value 1: %u\n", 3801 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3802 3803 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3804 printf(" Latency Indicator register: 0x%08x\n", reg); 3805 3806 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3807 printf(" Status register: 0x%04x\n", reg & 0xffff); 3808 printf(" Substate Status: 0x%02x\n", 3809 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3810 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3811 printf(" Control register: 0x%04x\n", reg >> 16); 3812 printf(" Substate Control: 0x%02x\n", 3813 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3814 3815 for (i = 0; i <= substmax; i++) 3816 printf(" Substate Power Allocation register %d: 0x%02x\n", 3817 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3818 } 3819 3820 static const char * 3821 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3822 { 3823 3824 switch (val) { 3825 case PCI_TPH_REQ_STTBLLOC_NONE: 3826 return "Not Present"; 3827 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3828 return "in the TPH Requester Capability Structure"; 3829 case PCI_TPH_REQ_STTBLLOC_MSIX: 3830 return "in the MSI-X Table"; 3831 default: 3832 return "Unknown"; 3833 } 3834 } 3835 3836 static void 3837 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3838 { 3839 pcireg_t reg; 3840 int size = 0, i, j; 3841 uint8_t sttbloc; 3842 3843 printf("\n TPH Requester Extended Capability\n"); 3844 3845 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3846 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3847 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3848 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3849 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3850 onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3851 sttbloc = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3852 printf(" ST Table Location: %s\n", 3853 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3854 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3855 size = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3856 printf(" ST Table Size: %d\n", size); 3857 } 3858 3859 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3860 printf(" TPH Requester Control register: 0x%08x\n", reg); 3861 printf(" ST Mode Select: "); 3862 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3863 case PCI_TPH_REQ_CTL_STSEL_NO: 3864 printf("No ST Mode\n"); 3865 break; 3866 case PCI_TPH_REQ_CTL_STSEL_IV: 3867 printf("Interrupt Vector Mode\n"); 3868 break; 3869 case PCI_TPH_REQ_CTL_STSEL_DS: 3870 printf("Device Specific Mode\n"); 3871 break; 3872 default: 3873 printf("(reserved value)\n"); 3874 break; 3875 } 3876 printf(" TPH Requester Enable: "); 3877 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3878 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3879 printf("Not permitted\n"); 3880 break; 3881 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3882 printf("TPH and not Extended TPH\n"); 3883 break; 3884 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3885 printf("TPH and Extended TPH"); 3886 break; 3887 default: 3888 printf("(reserved value)\n"); 3889 break; 3890 } 3891 3892 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3893 return; 3894 3895 for (i = 0; i < size ; i += 2) { 3896 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3897 for (j = 0; j < 2 ; j++) { 3898 uint32_t entry = reg; 3899 3900 if (j != 0) 3901 entry >>= 16; 3902 entry &= 0xffff; 3903 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3904 i + j, entry); 3905 } 3906 } 3907 } 3908 3909 static void 3910 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3911 { 3912 pcireg_t reg; 3913 3914 printf("\n Latency Tolerance Reporting\n"); 3915 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3916 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3917 printf(" Max Snoop Latency: %juns\n", 3918 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3919 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3920 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3921 printf(" Max No-Snoop Latency: %juns\n", 3922 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3923 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3924 } 3925 3926 static void 3927 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3928 { 3929 int pcie_capoff; 3930 pcireg_t reg; 3931 int i, maxlinkwidth; 3932 3933 printf("\n Secondary PCI Express Register\n"); 3934 3935 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3936 printf(" Link Control 3 register: 0x%08x\n", reg); 3937 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3938 onoff("Link Equalization Request Interrupt Enable", 3939 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3940 printf(" Enable Lower SKP OS Generation Vector:"); 3941 pci_print_pcie_linkspeedvector( 3942 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3943 printf("\n"); 3944 3945 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3946 printf(" Lane Error Status register: 0x%08x\n", reg); 3947 3948 /* Get Max Link Width */ 3949 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3950 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3951 maxlinkwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3952 } else { 3953 printf("error: failed to get PCIe capability\n"); 3954 return; 3955 } 3956 for (i = 0; i < maxlinkwidth; i++) { 3957 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3958 if (i % 2 != 0) 3959 reg >>= 16; 3960 else 3961 reg &= 0xffff; 3962 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3963 i, reg); 3964 printf(" Downstream Port Transmit Preset: 0x%x\n", 3965 PCIREG_SHIFTOUT(reg, 3966 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3967 printf(" Downstream Port Receive Hint: 0x%x\n", 3968 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3969 printf(" Upstream Port Transmit Preset: 0x%x\n", 3970 PCIREG_SHIFTOUT(reg, 3971 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3972 printf(" Upstream Port Receive Hint: 0x%x\n", 3973 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3974 } 3975 } 3976 3977 /* XXX pci_conf_print_pmux_cap */ 3978 3979 static void 3980 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3981 { 3982 pcireg_t reg, cap, ctl; 3983 unsigned int num; 3984 3985 printf("\n Process Address Space ID\n"); 3986 3987 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3988 cap = reg & 0xffff; 3989 ctl = reg >> 16; 3990 printf(" PASID Capability Register: 0x%04x\n", cap); 3991 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3992 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3993 num = (1 << PCIREG_SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3994 printf(" Max PASID Width: %u\n", num); 3995 3996 printf(" PASID Control Register: 0x%04x\n", ctl); 3997 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3998 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3999 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 4000 } 4001 4002 static void 4003 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 4004 { 4005 pcireg_t reg, cap, ctl; 4006 unsigned int num; 4007 4008 printf("\n LN Requester\n"); 4009 4010 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 4011 cap = reg & 0xffff; 4012 ctl = reg >> 16; 4013 printf(" LNR Capability register: 0x%04x\n", cap); 4014 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 4015 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 4016 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 4017 printf(" LNR Registration MAX: %u\n", num); 4018 4019 printf(" LNR Control register: 0x%04x\n", ctl); 4020 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 4021 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 4022 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 4023 printf(" LNR Registration Limit: %u\n", num); 4024 } 4025 4026 static void 4027 pci_conf_print_dpc_pio(pcireg_t r) 4028 { 4029 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 4030 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 4031 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 4032 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 4033 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 4034 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 4035 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 4036 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 4037 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 4038 } 4039 4040 static void 4041 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 4042 { 4043 pcireg_t reg, cap, ctl, stat, errsrc; 4044 const char *trigstr; 4045 bool rpext; 4046 4047 printf("\n Downstream Port Containment\n"); 4048 4049 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 4050 cap = reg & 0xffff; 4051 ctl = reg >> 16; 4052 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 4053 printf(" DPC Capability register: 0x%04x\n", cap); 4054 printf(" DPC Interrupt Message Number: %02x\n", 4055 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 4056 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 4057 onoff("Poisoned TLP Egress Blocking Supported", reg, 4058 PCI_DPCCAP_POISONTLPEB); 4059 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 4060 printf(" RP PIO Log Size: %u\n", 4061 PCIREG_SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 4062 onoff("DL_Active ERR_COR Signaling Supported", reg, 4063 PCI_DPCCAP_DLACTECORS); 4064 printf(" DPC Control register: 0x%04x\n", ctl); 4065 switch (PCIREG_SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 4066 case 0: 4067 trigstr = "disabled"; 4068 break; 4069 case 1: 4070 trigstr = "enabled(ERR_FATAL)"; 4071 break; 4072 case 2: 4073 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 4074 break; 4075 default: 4076 trigstr = "(reserverd)"; 4077 break; 4078 } 4079 printf(" DPC Trigger Enable: %s\n", trigstr); 4080 printf(" DPC Completion Control: %s Completion Status\n", 4081 (reg & PCI_DPCCTL_COMPCTL) 4082 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 4083 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 4084 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 4085 onoff("Poisoned TLP Egress Blocking Enable", reg, 4086 PCI_DPCCTL_POISONTLPEB); 4087 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 4088 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 4089 4090 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 4091 stat = reg & 0xffff; 4092 errsrc = reg >> 16; 4093 printf(" DPC Status register: 0x%04x\n", stat); 4094 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 4095 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4096 case 0: 4097 trigstr = "an unmasked uncorrectable error"; 4098 break; 4099 case 1: 4100 trigstr = "receiving an ERR_NONFATAL"; 4101 break; 4102 case 2: 4103 trigstr = "receiving an ERR_FATAL"; 4104 break; 4105 case 3: 4106 trigstr = "DPC Trigger Reason Extension field"; 4107 break; 4108 } 4109 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 4110 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 4111 if (rpext) 4112 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 4113 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4114 case 0: 4115 trigstr = "Due to RP PIO error"; 4116 break; 4117 case 1: 4118 trigstr = "Due to the DPC Software trigger bit"; 4119 break; 4120 default: 4121 trigstr = "(reserved)"; 4122 break; 4123 } 4124 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 4125 if (rpext) 4126 printf(" RP PIO First Error Pointer: 0x%02x\n", 4127 PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 4128 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 4129 4130 if (!rpext) 4131 return; 4132 /* 4133 * All of the following registers are implemented by a device which has 4134 * RP Extensions for DPC 4135 */ 4136 4137 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4138 printf(" RP PIO Status Register: 0x%08x\n", reg); 4139 pci_conf_print_dpc_pio(reg); 4140 4141 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4142 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4143 pci_conf_print_dpc_pio(reg); 4144 4145 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4146 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4147 pci_conf_print_dpc_pio(reg); 4148 4149 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4150 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4151 pci_conf_print_dpc_pio(reg); 4152 4153 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4154 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4155 pci_conf_print_dpc_pio(reg); 4156 4157 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4158 extcapoff + PCI_DPC_RPPIO_HLOG); 4159 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4160 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4161 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4162 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4163 } 4164 4165 4166 static int 4167 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4168 { 4169 4170 /* Return scale in us */ 4171 switch (scale) { 4172 case 0x0: 4173 return 2; 4174 case 0x1: 4175 return 10; 4176 case 0x2: 4177 return 100; 4178 default: 4179 return -1; 4180 } 4181 } 4182 4183 static void 4184 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4185 { 4186 pcireg_t reg; 4187 int scale, val; 4188 int pcie_capoff; 4189 4190 printf("\n L1 PM Substates\n"); 4191 4192 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4193 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4194 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4195 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4196 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4197 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4198 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4199 /* The Link Activation Supported bit is only for Downstream Port */ 4200 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4201 uint32_t t = regs[o2i(pcie_capoff)]; 4202 4203 if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN)) 4204 onoff("Link Activation Supported", reg, 4205 PCI_L1PM_CAP_LA); 4206 } 4207 printf(" Port Common Mode Restore Time: %uus\n", 4208 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4209 scale = pci_conf_l1pm_cap_tposcale( 4210 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4211 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4212 printf(" Port T_POWER_ON: "); 4213 if (scale == -1) 4214 printf("unknown\n"); 4215 else 4216 printf("%dus\n", val * scale); 4217 4218 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4219 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4220 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4221 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4222 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4223 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4224 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4225 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4226 printf(" Common Mode Restore Time: %uus\n", 4227 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4228 scale = PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4229 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4230 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4231 4232 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4233 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4234 scale = pci_conf_l1pm_cap_tposcale( 4235 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4236 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4237 printf(" T_POWER_ON: "); 4238 if (scale == -1) 4239 printf("unknown\n"); 4240 else 4241 printf("%dus\n", val * scale); 4242 4243 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4244 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4245 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4246 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4247 } 4248 } 4249 4250 static void 4251 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4252 { 4253 pcireg_t reg; 4254 uint32_t val; 4255 4256 printf("\n Precision Time Measurement\n"); 4257 4258 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4259 printf(" PTM Capability register: 0x%08x\n", reg); 4260 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4261 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4262 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4263 printf(" Local Clock Granularity: "); 4264 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4265 switch (val) { 4266 case 0: 4267 printf("Not implemented\n"); 4268 break; 4269 case 0xffff: 4270 printf("> 254ns\n"); 4271 break; 4272 default: 4273 printf("%uns\n", val); 4274 break; 4275 } 4276 4277 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4278 printf(" PTM Control register: 0x%08x\n", reg); 4279 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4280 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4281 printf(" Effective Granularity: "); 4282 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4283 switch (val) { 4284 case 0: 4285 printf("Unknown\n"); 4286 break; 4287 case 0xffff: 4288 printf("> 254ns\n"); 4289 break; 4290 default: 4291 printf("%uns\n", val); 4292 break; 4293 } 4294 } 4295 4296 /* XXX pci_conf_print_mpcie_cap */ 4297 /* XXX pci_conf_print_frsq_cap */ 4298 /* XXX pci_conf_print_rtr_cap */ 4299 /* XXX pci_conf_print_desigvndsp_cap */ 4300 /* XXX pci_conf_print_vf_resizbar_cap */ 4301 4302 static void 4303 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4304 { 4305 pcireg_t reg; 4306 4307 printf("\n Data link Feature Register\n"); 4308 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4309 printf(" Capability register: 0x%08x\n", reg); 4310 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4311 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4312 4313 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4314 printf(" Status register: 0x%08x\n", reg); 4315 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4316 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4317 } 4318 4319 static void 4320 pci_conf_print_pl16g_cap(const pcireg_t *regs, int extcapoff) 4321 { 4322 pcireg_t reg, lwidth; 4323 int pcie_capoff; 4324 unsigned int i, j; 4325 4326 printf("\n Physical Layer 16.0 GT/s\n"); 4327 reg = regs[o2i(extcapoff + PCI_PL16G_CAP)]; 4328 printf(" Capability register: 0x%08x\n", reg); 4329 4330 reg = regs[o2i(extcapoff + PCI_PL16G_CTL)]; 4331 printf(" Control register: 0x%08x\n", reg); 4332 4333 reg = regs[o2i(extcapoff + PCI_PL16G_STAT)]; 4334 printf(" Status register: 0x%08x\n", reg); 4335 onoff("Equalization 16.0 GT/s Complete", reg, PCI_PL16G_STAT_EQ_COMPL); 4336 onoff("Equalization 16.0 GT/s Phase 1 Successful", reg, 4337 PCI_PL16G_STAT_EQ_P1S); 4338 onoff("Equalization 16.0 GT/s Phase 2 Successful", reg, 4339 PCI_PL16G_STAT_EQ_P2S); 4340 onoff("Equalization 16.0 GT/s Phase 3 Successful", reg, 4341 PCI_PL16G_STAT_EQ_P3S); 4342 4343 reg = regs[o2i(extcapoff + PCI_PL16G_LDPMS)]; 4344 printf(" Local Data Parity Mismatch Status register: 0x%08x\n", 4345 reg); 4346 4347 reg = regs[o2i(extcapoff + PCI_PL16G_FRDPMS)]; 4348 printf(" First Retimer Data Parity Mismatch Status register:" 4349 " 0x%08x\n", reg); 4350 4351 reg = regs[o2i(extcapoff + PCI_PL16G_SRDPMS)]; 4352 printf(" Second Retimer Data Parity Mismatch Status register:" 4353 " 0x%08x\n", reg); 4354 4355 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff) == 0) 4356 return; /* error */ 4357 4358 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 4359 lwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 4360 4361 for (i = 0; i < lwidth;) { 4362 reg = regs[o2i(extcapoff + PCI_PL16G_LEC + i)]; 4363 4364 for (j = 0; j < 4; j++) { 4365 pcireg_t up, down; 4366 4367 down = reg & 0x0000000f; 4368 up = (reg >> 4) & 0x0000000f; 4369 printf(" Lane %d downstream: ", i); 4370 pci_print_pcie_link_preset_preshoot_deemphasis(down); 4371 printf("\n Lane %d upstream: ", i); 4372 pci_print_pcie_link_preset_preshoot_deemphasis(up); 4373 printf("\n"); 4374 4375 reg >>= 8; 4376 i++; 4377 if (i >= lwidth) 4378 break; 4379 } 4380 } 4381 } 4382 4383 static const char * const pcie_receive_number_dp[] = { 4384 [0] = ("Broadcast " 4385 "(Downstream Port Receiver and all Retimer Pseudo Port Receiver)"), 4386 [1] = "Rx(A) (Downstream Port Receiver)", 4387 [2] = "Rx(B) (Retimer X or Z Upstream Pseudo Port Receiver)", 4388 [3] = "Rx(C) (Retimer X or Z Downstream Pseudo Port Receiver)", 4389 [4] = "Rx(D) (Retimer Y Upstream Pseudo Port Receiver)", 4390 [5] = "Rx(E) (Retimer Y Downstream Pseudo Port Receiver)", 4391 [6] = "Reserved", 4392 [7] = "Reserved" 4393 }; 4394 4395 static const char * const pcie_receive_number_up[] = { 4396 "Broadcast (Upstream Port Receiver)", 4397 "Reserved", 4398 "Reserved", 4399 "Reserved", 4400 "Reserved", 4401 "Reserved", 4402 "Rx(F) (Upstream Port Receiver)", 4403 "Reserved" 4404 }; 4405 4406 /* 4407 * Print PCI_LMR_LANECSR. This function is used for both control and status 4408 * register. The reg argument in the lower 16bit has the control or status 4409 * register. The encoding is the same except the receive number, so use _LCTL_ 4410 * macro. 4411 */ 4412 static void 4413 pci_conf_print_lmr_lcsr(pcireg_t reg, bool up, bool dp) 4414 { 4415 int rnum; 4416 4417 printf(" Receive Number: "); 4418 rnum = PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_RNUM); 4419 if (up) 4420 printf("%s\n", pcie_receive_number_up[rnum]); 4421 else if (dp) 4422 printf("%s\n", pcie_receive_number_dp[rnum]); 4423 else 4424 printf("%x\n", rnum); 4425 4426 printf(" Margin Type: %x\n", 4427 PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_MTYPE)); 4428 printf(" Usage Model: %s\n", 4429 (PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_UMODEL) == 0) 4430 ? "Lane Margining at Receiver" : "Reserved Encoding"); 4431 printf(" Margin Payload: 0x%02x\n", 4432 PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_MPAYLOAD)); 4433 } 4434 4435 static void 4436 pci_conf_print_lmr_cap(const pcireg_t *regs, int extcapoff) 4437 { 4438 pcireg_t reg, lwidth; 4439 int pcie_capoff; 4440 int pcie_devtype; 4441 unsigned int i; 4442 bool up, dp; 4443 4444 printf("\n Lane Margining at the Receiver\n"); 4445 reg = regs[o2i(extcapoff + PCI_LMR_PCAPSTAT)]; 4446 printf(" Port Capability register: 0x%04x\n", reg & 0xffff); 4447 onoff("Margining uses Driver Software", reg, PCI_LMR_PCAP_MUDS); 4448 printf(" Port Status register: 0x%04x\n", (reg >> 16) & 0xffff); 4449 onoff("Margining Ready", reg, PCI_LMR_PSTAT_MR); 4450 onoff("Margining Software Ready", reg, PCI_LMR_PSTAT_MSR); 4451 4452 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff) == 0) 4453 return; /* error */ 4454 4455 up = dp = false; 4456 reg = regs[o2i(pcie_capoff)]; 4457 pcie_devtype = PCIE_XCAP_TYPE(reg); 4458 switch (pcie_devtype) { 4459 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 4460 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 4461 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 4462 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 4463 up = true; 4464 break; 4465 case PCIE_XCAP_TYPE_RP: /* 0x4 */ 4466 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 4467 dp = true; 4468 break; 4469 default: 4470 printf("neither upstream nor downstream?(%x)\n", pcie_devtype); 4471 break; 4472 } 4473 4474 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 4475 lwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 4476 4477 for (i = 0; i < lwidth; i++) { 4478 pcireg_t lctl, lstat; 4479 4480 reg = regs[o2i(extcapoff + PCI_LMR_LANECSR + (i * 4))]; 4481 4482 lctl = reg & 0xffff; 4483 printf(" Lane %d control: 0x%04x\n", i, lctl); 4484 pci_conf_print_lmr_lcsr(lctl, up, dp); 4485 4486 lstat = (reg >> 16) & 0xffff; 4487 printf(" Lane %d status: 0x%04x\n", i, lstat); 4488 pci_conf_print_lmr_lcsr(lstat, up, dp); 4489 } 4490 } 4491 4492 /* XXX pci_conf_print_hierarchyid_cap */ 4493 /* XXX pci_conf_print_npem_cap */ 4494 4495 #undef MS 4496 #undef SM 4497 #undef RW 4498 4499 static struct { 4500 pcireg_t cap; 4501 const char *name; 4502 void (*printfunc)(const pcireg_t *, int); 4503 } pci_extcaptab[] = { 4504 { 0, "reserved", 4505 NULL }, 4506 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4507 pci_conf_print_aer_cap }, 4508 { PCI_EXTCAP_VC, "Virtual Channel", 4509 pci_conf_print_vc_cap }, 4510 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4511 pci_conf_print_sernum_cap }, 4512 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4513 pci_conf_print_pwrbdgt_cap }, 4514 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4515 pci_conf_print_rclink_dcl_cap }, 4516 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4517 NULL }, 4518 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4519 pci_conf_print_rcec_assoc_cap }, 4520 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4521 NULL }, 4522 { PCI_EXTCAP_VC2, "Virtual Channel", 4523 NULL }, 4524 { PCI_EXTCAP_RCRB, "RCRB Header", 4525 NULL }, 4526 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4527 NULL }, 4528 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4529 NULL }, 4530 { PCI_EXTCAP_ACS, "Access Control Services", 4531 pci_conf_print_acs_cap }, 4532 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4533 pci_conf_print_ari_cap }, 4534 { PCI_EXTCAP_ATS, "Address Translation Services", 4535 pci_conf_print_ats_cap }, 4536 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4537 pci_conf_print_sriov_cap }, 4538 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4539 NULL }, 4540 { PCI_EXTCAP_MCAST, "Multicast", 4541 pci_conf_print_multicast_cap }, 4542 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4543 pci_conf_print_page_req_cap }, 4544 { PCI_EXTCAP_AMD, "Reserved for AMD", 4545 NULL }, 4546 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4547 pci_conf_print_resizbar_cap }, 4548 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4549 pci_conf_print_dpa_cap }, 4550 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4551 pci_conf_print_tph_req_cap }, 4552 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4553 pci_conf_print_ltr_cap }, 4554 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4555 pci_conf_print_sec_pcie_cap }, 4556 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4557 NULL }, 4558 { PCI_EXTCAP_PASID, "Process Address Space ID", 4559 pci_conf_print_pasid_cap }, 4560 { PCI_EXTCAP_LNR, "LN Requester", 4561 pci_conf_print_lnr_cap }, 4562 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4563 pci_conf_print_dpc_cap }, 4564 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4565 pci_conf_print_l1pm_cap }, 4566 { PCI_EXTCAP_PTM, "Precision Time Measurement", 4567 pci_conf_print_ptm_cap }, 4568 { PCI_EXTCAP_MPCIE, "M-PCIe", 4569 NULL }, 4570 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4571 NULL }, 4572 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4573 NULL }, 4574 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4575 NULL }, 4576 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4577 NULL }, 4578 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4579 { PCI_EXTCAP_PL16G, "Physical Layer 16.0 GT/s", 4580 pci_conf_print_pl16g_cap }, 4581 { PCI_EXTCAP_LMR, "Lane Margining at the Receiver", 4582 pci_conf_print_lmr_cap }, 4583 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4584 NULL }, 4585 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4586 NULL }, 4587 { PCI_EXTCAP_PL32G, "Physical Layer 32.0 GT/s", 4588 NULL }, 4589 { PCI_EXTCAP_AP, "Alternate Protocol", 4590 NULL }, 4591 { PCI_EXTCAP_SFI, "System Firmware Intermediary", 4592 NULL }, 4593 }; 4594 4595 static int 4596 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4597 { 4598 int off; 4599 pcireg_t rval; 4600 4601 for (off = PCI_EXTCAPLIST_BASE; 4602 off != 0; 4603 off = PCI_EXTCAPLIST_NEXT(rval)) { 4604 rval = regs[o2i(off)]; 4605 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4606 if (offsetp != NULL) 4607 *offsetp = off; 4608 return 1; 4609 } 4610 } 4611 return 0; 4612 } 4613 4614 static void 4615 pci_conf_print_extcaplist( 4616 #ifdef _KERNEL 4617 pci_chipset_tag_t pc, pcitag_t tag, 4618 #endif 4619 const pcireg_t *regs) 4620 { 4621 int off; 4622 pcireg_t foundcap; 4623 pcireg_t rval; 4624 bool foundtable[__arraycount(pci_extcaptab)]; 4625 unsigned int i; 4626 4627 /* Check Extended capability structure */ 4628 off = PCI_EXTCAPLIST_BASE; 4629 rval = regs[o2i(off)]; 4630 if (rval == 0xffffffff || rval == 0) 4631 return; 4632 4633 /* Clear table */ 4634 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4635 foundtable[i] = false; 4636 4637 /* Print extended capability register's offset and the type first */ 4638 for (;;) { 4639 printf(" Extended Capability Register at 0x%02x\n", off); 4640 4641 foundcap = PCI_EXTCAPLIST_CAP(rval); 4642 printf(" type: 0x%04x (", foundcap); 4643 if (foundcap < __arraycount(pci_extcaptab)) { 4644 printf("%s)\n", pci_extcaptab[foundcap].name); 4645 /* Mark as found */ 4646 foundtable[foundcap] = true; 4647 } else 4648 printf("unknown)\n"); 4649 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4650 4651 off = PCI_EXTCAPLIST_NEXT(rval); 4652 if (off == 0) 4653 break; 4654 else if (off <= PCI_CONF_SIZE) { 4655 printf(" next pointer: 0x%03x (incorrect)\n", off); 4656 return; 4657 } 4658 rval = regs[o2i(off)]; 4659 } 4660 4661 /* 4662 * And then, print the detail of each capability registers 4663 * in capability value's order. 4664 */ 4665 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4666 if (foundtable[i] == false) 4667 continue; 4668 4669 /* 4670 * The type was found. Search capability list again and 4671 * print all capabilities that the capability type is 4672 * the same. 4673 */ 4674 if (pci_conf_find_extcap(regs, i, &off) == 0) 4675 continue; 4676 rval = regs[o2i(off)]; 4677 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4678 || (pci_extcaptab[i].printfunc == NULL)) 4679 continue; 4680 4681 pci_extcaptab[i].printfunc(regs, off); 4682 4683 } 4684 } 4685 4686 /* Print the Secondary Status Register. */ 4687 static void 4688 pci_conf_print_ssr(pcireg_t rval) 4689 { 4690 pcireg_t devsel; 4691 4692 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4693 onoff("66 MHz capable", rval, __BIT(5)); 4694 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4695 onoff("Fast back-to-back capable", rval, __BIT(7)); 4696 onoff("Data parity error detected", rval, __BIT(8)); 4697 4698 printf(" DEVSEL timing: "); 4699 devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9)); 4700 switch (devsel) { 4701 case 0: 4702 printf("fast"); 4703 break; 4704 case 1: 4705 printf("medium"); 4706 break; 4707 case 2: 4708 printf("slow"); 4709 break; 4710 default: 4711 printf("unknown/reserved"); /* XXX */ 4712 break; 4713 } 4714 printf(" (0x%x)\n", devsel); 4715 4716 onoff("Signalled target abort", rval, __BIT(11)); 4717 onoff("Received target abort", rval, __BIT(12)); 4718 onoff("Received master abort", rval, __BIT(13)); 4719 onoff("Received system error", rval, __BIT(14)); 4720 onoff("Detected parity error", rval, __BIT(15)); 4721 } 4722 4723 static void 4724 pci_conf_print_type0( 4725 #ifdef _KERNEL 4726 pci_chipset_tag_t pc, pcitag_t tag, 4727 #endif 4728 const pcireg_t *regs) 4729 { 4730 int off, width; 4731 pcireg_t rval; 4732 const char *str; 4733 4734 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4735 #ifdef _KERNEL 4736 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4737 #else 4738 width = pci_conf_print_bar(regs, off, NULL); 4739 #endif 4740 } 4741 4742 printf(" Cardbus CIS Pointer: 0x%08x\n", 4743 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4744 4745 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4746 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4747 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4748 4749 rval = regs[o2i(PCI_MAPREG_ROM)]; 4750 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4751 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4752 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4753 printf(" Validation Status: "); 4754 switch (PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4755 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4756 str = "Validation not supported"; 4757 break; 4758 case PCI_MAPREG_ROM_VSTAT_INPROG: 4759 str = "Validation in Progress"; 4760 break; 4761 case PCI_MAPREG_ROM_VSTAT_VPASS: 4762 str = "Validation Pass. " 4763 "Valid contents, trust test was not performed"; 4764 break; 4765 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4766 str = "Validation Pass. Valid and trusted contents"; 4767 break; 4768 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4769 str = "Validation Fail. Invalid contents"; 4770 break; 4771 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4772 str = "Validation Fail. Valid but untrusted contents"; 4773 break; 4774 case PCI_MAPREG_ROM_VSTAT_WPASS: 4775 str = "Warning Pass. Validation passed with warning. " 4776 "Valid contents, trust test was not performed"; 4777 break; 4778 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4779 str = "Warning Pass. Validation passed with warning. " 4780 "Valid and trusted contents"; 4781 break; 4782 } 4783 printf("%s\n", str); 4784 printf(" Validation Details: 0x%x\n", 4785 PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4786 4787 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4788 printf(" Capability list pointer: 0x%02x\n", 4789 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4790 else 4791 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4792 4793 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4794 4795 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4796 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4797 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4798 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4799 switch (PCI_INTERRUPT_PIN(rval)) { 4800 case PCI_INTERRUPT_PIN_NONE: 4801 printf("(none)"); 4802 break; 4803 case PCI_INTERRUPT_PIN_A: 4804 printf("(pin A)"); 4805 break; 4806 case PCI_INTERRUPT_PIN_B: 4807 printf("(pin B)"); 4808 break; 4809 case PCI_INTERRUPT_PIN_C: 4810 printf("(pin C)"); 4811 break; 4812 case PCI_INTERRUPT_PIN_D: 4813 printf("(pin D)"); 4814 break; 4815 default: 4816 printf("(? ? ?)"); 4817 break; 4818 } 4819 printf("\n"); 4820 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4821 } 4822 4823 static void 4824 pci_conf_print_type1( 4825 #ifdef _KERNEL 4826 pci_chipset_tag_t pc, pcitag_t tag, 4827 #endif 4828 const pcireg_t *regs) 4829 { 4830 int off, width; 4831 pcireg_t rval, csreg; 4832 uint32_t base, limit; 4833 uint32_t base_h, limit_h; 4834 uint64_t pbase, plimit; 4835 int use_upper; 4836 4837 /* 4838 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4839 * Bridge chip documentation, and may not be correct with 4840 * respect to various standards. (XXX) 4841 */ 4842 4843 for (off = 0x10; off < 0x18; off += width) { 4844 #ifdef _KERNEL 4845 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4846 #else 4847 width = pci_conf_print_bar(regs, off, NULL); 4848 #endif 4849 } 4850 4851 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4852 printf(" Primary bus number: 0x%02x\n", 4853 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4854 printf(" Secondary bus number: 0x%02x\n", 4855 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4856 printf(" Subordinate bus number: 0x%02x\n", 4857 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4858 printf(" Secondary bus latency timer: 0x%02x\n", 4859 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4860 4861 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4862 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4863 4864 /* I/O region */ 4865 printf(" I/O region:\n"); 4866 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4867 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4868 if (PCI_BRIDGE_IO_32BITS(rval)) 4869 use_upper = 1; 4870 else 4871 use_upper = 0; 4872 onoff("32bit I/O", rval, use_upper); 4873 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4874 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4875 4876 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4877 base_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4878 limit_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4879 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4880 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4881 4882 if (use_upper == 1) { 4883 base |= base_h << 16; 4884 limit |= limit_h << 16; 4885 } 4886 if (base < limit) { 4887 if (use_upper == 1) 4888 printf(" range: 0x%08x-0x%08x\n", base, limit); 4889 else 4890 printf(" range: 0x%04x-0x%04x\n", base, limit); 4891 } else 4892 printf(" range: not set\n"); 4893 4894 /* Non-prefetchable memory region */ 4895 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4896 printf(" Memory region:\n"); 4897 printf(" base register: 0x%04hx\n", 4898 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4899 printf(" limit register: 0x%04hx\n", 4900 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4901 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4902 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4903 if (base < limit) 4904 printf(" range: 0x%08x-0x%08x\n", base, limit); 4905 else 4906 printf(" range: not set\n"); 4907 4908 /* Prefetchable memory region */ 4909 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4910 printf(" Prefetchable memory region:\n"); 4911 printf(" base register: 0x%04x\n", 4912 (rval >> 0) & 0xffff); 4913 printf(" limit register: 0x%04x\n", 4914 (rval >> 16) & 0xffff); 4915 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4916 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4917 printf(" base upper 32 bits register: 0x%08x\n", 4918 base_h); 4919 printf(" limit upper 32 bits register: 0x%08x\n", 4920 limit_h); 4921 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4922 use_upper = 1; 4923 else 4924 use_upper = 0; 4925 onoff("64bit memory address", rval, use_upper); 4926 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4927 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4928 if (use_upper == 1) { 4929 pbase |= (uint64_t)base_h << 32; 4930 plimit |= (uint64_t)limit_h << 32; 4931 } 4932 if (pbase < plimit) { 4933 if (use_upper == 1) 4934 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4935 "\n", pbase, plimit); 4936 else 4937 printf(" range: 0x%08x-0x%08x\n", 4938 (uint32_t)pbase, (uint32_t)plimit); 4939 } else 4940 printf(" range: not set\n"); 4941 4942 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4943 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4944 printf(" Capability list pointer: 0x%02x\n", 4945 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4946 else 4947 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4948 4949 printf(" Expansion ROM Base Address: 0x%08x\n", 4950 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4951 4952 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4953 printf(" Interrupt line: 0x%02x\n", 4954 (rval >> 0) & 0xff); 4955 printf(" Interrupt pin: 0x%02x ", 4956 (rval >> 8) & 0xff); 4957 switch ((rval >> 8) & 0xff) { 4958 case PCI_INTERRUPT_PIN_NONE: 4959 printf("(none)"); 4960 break; 4961 case PCI_INTERRUPT_PIN_A: 4962 printf("(pin A)"); 4963 break; 4964 case PCI_INTERRUPT_PIN_B: 4965 printf("(pin B)"); 4966 break; 4967 case PCI_INTERRUPT_PIN_C: 4968 printf("(pin C)"); 4969 break; 4970 case PCI_INTERRUPT_PIN_D: 4971 printf("(pin D)"); 4972 break; 4973 default: 4974 printf("(? ? ?)"); 4975 break; 4976 } 4977 printf("\n"); 4978 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4979 printf(" Bridge control register: 0x%04hx\n", 4980 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4981 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4982 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4983 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4984 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4985 /* 4986 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4987 * VGA Palette Snoop Enable bit is set. 4988 */ 4989 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4990 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4991 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4992 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4993 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4994 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4995 onoff("Primary Discard Timer", rval, 4996 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4997 onoff("Secondary Discard Timer", 4998 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4999 onoff("Discard Timer Status", rval, 5000 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 5001 onoff("Discard Timer SERR# Enable", rval, 5002 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 5003 } 5004 5005 static void 5006 pci_conf_print_type2( 5007 #ifdef _KERNEL 5008 pci_chipset_tag_t pc, pcitag_t tag, 5009 #endif 5010 const pcireg_t *regs) 5011 { 5012 pcireg_t rval; 5013 5014 /* 5015 * XXX these need to be printed in more detail, need to be 5016 * XXX checked against specs/docs, etc. 5017 * 5018 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 5019 * controller chip documentation, and may not be correct with 5020 * respect to various standards. (XXX) 5021 */ 5022 5023 #ifdef _KERNEL 5024 pci_conf_print_bar(pc, tag, regs, 0x10, 5025 "CardBus socket/ExCA registers"); 5026 #else 5027 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 5028 #endif 5029 5030 /* Capability list pointer and secondary status register */ 5031 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 5032 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 5033 printf(" Capability list pointer: 0x%02x\n", 5034 PCI_CAPLIST_PTR(rval)); 5035 else 5036 printf(" Reserved @ 0x14: 0x%04x\n", 5037 PCIREG_SHIFTOUT(rval, __BITS(15, 0))); 5038 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 5039 5040 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 5041 printf(" PCI bus number: 0x%02x\n", 5042 (rval >> 0) & 0xff); 5043 printf(" CardBus bus number: 0x%02x\n", 5044 (rval >> 8) & 0xff); 5045 printf(" Subordinate bus number: 0x%02x\n", 5046 (rval >> 16) & 0xff); 5047 printf(" CardBus latency timer: 0x%02x\n", 5048 (rval >> 24) & 0xff); 5049 5050 /* XXX Print more prettily */ 5051 printf(" CardBus memory region 0:\n"); 5052 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 5053 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 5054 printf(" CardBus memory region 1:\n"); 5055 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 5056 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 5057 printf(" CardBus I/O region 0:\n"); 5058 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 5059 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 5060 printf(" CardBus I/O region 1:\n"); 5061 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 5062 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 5063 5064 rval = regs[o2i(PCI_INTERRUPT_REG)]; 5065 printf(" Interrupt line: 0x%02x\n", 5066 (rval >> 0) & 0xff); 5067 printf(" Interrupt pin: 0x%02x ", 5068 (rval >> 8) & 0xff); 5069 switch ((rval >> 8) & 0xff) { 5070 case PCI_INTERRUPT_PIN_NONE: 5071 printf("(none)"); 5072 break; 5073 case PCI_INTERRUPT_PIN_A: 5074 printf("(pin A)"); 5075 break; 5076 case PCI_INTERRUPT_PIN_B: 5077 printf("(pin B)"); 5078 break; 5079 case PCI_INTERRUPT_PIN_C: 5080 printf("(pin C)"); 5081 break; 5082 case PCI_INTERRUPT_PIN_D: 5083 printf("(pin D)"); 5084 break; 5085 default: 5086 printf("(? ? ?)"); 5087 break; 5088 } 5089 printf("\n"); 5090 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 5091 printf(" Bridge control register: 0x%04x\n", rval); 5092 onoff("Parity error response", rval, __BIT(0)); 5093 onoff("SERR# enable", rval, __BIT(1)); 5094 onoff("ISA enable", rval, __BIT(2)); 5095 onoff("VGA enable", rval, __BIT(3)); 5096 onoff("Master abort mode", rval, __BIT(5)); 5097 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 5098 onoff("Functional interrupts routed by ExCA registers", rval, 5099 __BIT(7)); 5100 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 5101 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 5102 onoff("Write posting enable", rval, __BIT(10)); 5103 5104 rval = regs[o2i(0x40)]; 5105 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 5106 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 5107 5108 #ifdef _KERNEL 5109 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 5110 #else 5111 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 5112 #endif 5113 } 5114 5115 void 5116 pci_conf_print( 5117 #ifdef _KERNEL 5118 pci_chipset_tag_t pc, pcitag_t tag, 5119 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 5120 #else 5121 int pcifd, u_int bus, u_int dev, u_int func 5122 #endif 5123 ) 5124 { 5125 pcireg_t *regs; 5126 int off, capoff, endoff, hdrtype; 5127 const char *type_name; 5128 #ifdef _KERNEL 5129 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 5130 #else 5131 void (*type_printfn)(const pcireg_t *); 5132 #endif 5133 5134 regs = MALLOC(PCI_EXTCONF_SIZE); 5135 5136 printf("PCI configuration registers:\n"); 5137 5138 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 5139 #ifdef _KERNEL 5140 regs[o2i(off)] = pci_conf_read(pc, tag, off); 5141 #else 5142 if (pcibus_conf_read(pcifd, bus, dev, func, off, 5143 ®s[o2i(off)]) == -1) 5144 regs[o2i(off)] = 0; 5145 #endif 5146 } 5147 5148 /* common header */ 5149 printf(" Common header:\n"); 5150 pci_conf_print_regs(regs, 0, 16); 5151 5152 printf("\n"); 5153 #ifdef _KERNEL 5154 pci_conf_print_common(pc, tag, regs); 5155 #else 5156 pci_conf_print_common(regs); 5157 #endif 5158 printf("\n"); 5159 5160 /* type-dependent header */ 5161 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 5162 switch (hdrtype) { /* XXX make a table, eventually */ 5163 case 0: 5164 /* Standard device header */ 5165 type_name = "\"normal\" device"; 5166 type_printfn = &pci_conf_print_type0; 5167 capoff = PCI_CAPLISTPTR_REG; 5168 endoff = 64; 5169 break; 5170 case 1: 5171 /* PCI-PCI bridge header */ 5172 type_name = "PCI-PCI bridge"; 5173 type_printfn = &pci_conf_print_type1; 5174 capoff = PCI_CAPLISTPTR_REG; 5175 endoff = 64; 5176 break; 5177 case 2: 5178 /* PCI-CardBus bridge header */ 5179 type_name = "PCI-CardBus bridge"; 5180 type_printfn = &pci_conf_print_type2; 5181 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 5182 endoff = 72; 5183 break; 5184 default: 5185 type_name = NULL; 5186 type_printfn = 0; 5187 capoff = -1; 5188 endoff = 64; 5189 break; 5190 } 5191 printf(" Type %d ", hdrtype); 5192 if (type_name != NULL) 5193 printf("(%s) ", type_name); 5194 printf("header:\n"); 5195 pci_conf_print_regs(regs, 16, endoff); 5196 printf("\n"); 5197 if (type_printfn) { 5198 #ifdef _KERNEL 5199 (*type_printfn)(pc, tag, regs); 5200 #else 5201 (*type_printfn)(regs); 5202 #endif 5203 } else 5204 printf(" Don't know how to pretty-print type %d header.\n", 5205 hdrtype); 5206 printf("\n"); 5207 5208 /* capability list, if present */ 5209 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 5210 && (capoff > 0)) { 5211 #ifdef _KERNEL 5212 pci_conf_print_caplist(pc, tag, regs, capoff); 5213 #else 5214 pci_conf_print_caplist(regs, capoff); 5215 #endif 5216 printf("\n"); 5217 } 5218 5219 /* device-dependent header */ 5220 printf(" Device-dependent header:\n"); 5221 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 5222 #ifdef _KERNEL 5223 printf("\n"); 5224 if (printfn) 5225 (*printfn)(pc, tag, regs); 5226 else 5227 printf(" Don't know how to pretty-print device-dependent header.\n"); 5228 #endif /* _KERNEL */ 5229 5230 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 5231 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 5232 goto out; 5233 5234 printf("\n"); 5235 #ifdef _KERNEL 5236 pci_conf_print_extcaplist(pc, tag, regs); 5237 #else 5238 pci_conf_print_extcaplist(regs); 5239 #endif 5240 printf("\n"); 5241 5242 /* Extended Configuration Space, if present */ 5243 printf(" Extended Configuration Space:\n"); 5244 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 5245 5246 out: 5247 FREE(regs, PCI_EXTCONF_SIZE); 5248 } 5249
Indexes created Sun Sep 21 18:09:52 GMT 2025