1 /* $NetBSD: nouveau_nvkm_nvfw_acr.c,v 1.3 2021/12/19 10:51:57 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_nvfw_acr.c,v 1.3 2021/12/19 10:51:57 riastradh Exp $"); 26 27 #include <core/subdev.h> 28 #include <nvfw/acr.h> 29 30 void 31 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr) 32 { 33 nvkm_debug(subdev, "wprHeader\n"); 34 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); 35 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); 36 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); 37 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); 38 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); 39 } 40 41 void 42 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr) 43 { 44 nvkm_debug(subdev, "wprHeader\n"); 45 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); 46 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); 47 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); 48 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); 49 nvkm_debug(subdev, "\tbinVersion : %d\n", hdr->bin_version); 50 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); 51 } 52 53 static void 54 lsb_header_tail_dump(struct nvkm_subdev *subdev, 55 struct lsb_header_tail *hdr) 56 { 57 nvkm_debug(subdev, "lsbHeader\n"); 58 nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off); 59 nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size); 60 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); 61 nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size); 62 nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off); 63 nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off); 64 nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size); 65 nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off); 66 nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size); 67 nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off); 68 nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size); 69 nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags); 70 } 71 72 void 73 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr) 74 { 75 lsb_header_tail_dump(subdev, &hdr->tail); 76 } 77 78 void 79 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr) 80 { 81 lsb_header_tail_dump(subdev, &hdr->tail); 82 } 83 84 void 85 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr) 86 { 87 int i; 88 89 nvkm_debug(subdev, "acrDesc\n"); 90 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); 91 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); 92 nvkm_debug(subdev, "\tmmuMemRange : 0x%x\n", 93 hdr->mmu_mem_range); 94 nvkm_debug(subdev, "\tnoRegions : %d\n", 95 hdr->regions.no_regions); 96 97 for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) { 98 nvkm_debug(subdev, "\tregion[%d] :\n", i); 99 nvkm_debug(subdev, "\t startAddr : 0x%x\n", 100 hdr->regions.region_props[i].start_addr); 101 nvkm_debug(subdev, "\t endAddr : 0x%x\n", 102 hdr->regions.region_props[i].end_addr); 103 nvkm_debug(subdev, "\t regionId : %d\n", 104 hdr->regions.region_props[i].region_id); 105 nvkm_debug(subdev, "\t readMask : 0x%x\n", 106 hdr->regions.region_props[i].read_mask); 107 nvkm_debug(subdev, "\t writeMask : 0x%x\n", 108 hdr->regions.region_props[i].write_mask); 109 nvkm_debug(subdev, "\t clientMask : 0x%x\n", 110 hdr->regions.region_props[i].client_mask); 111 } 112 113 nvkm_debug(subdev, "\tucodeBlobSize: %d\n", 114 hdr->ucode_blob_size); 115 nvkm_debug(subdev, "\tucodeBlobBase: 0x%"PRIx64"\n", 116 hdr->ucode_blob_base); 117 nvkm_debug(subdev, "\tvprEnabled : %d\n", 118 hdr->vpr_desc.vpr_enabled); 119 nvkm_debug(subdev, "\tvprStart : 0x%x\n", 120 hdr->vpr_desc.vpr_start); 121 nvkm_debug(subdev, "\tvprEnd : 0x%x\n", 122 hdr->vpr_desc.vpr_end); 123 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n", 124 hdr->vpr_desc.hdcp_policies); 125 } 126 127 void 128 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr) 129 { 130 int i; 131 132 nvkm_debug(subdev, "acrDesc\n"); 133 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); 134 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); 135 nvkm_debug(subdev, "\tmmuMemoryRange : 0x%x\n", 136 hdr->mmu_memory_range); 137 nvkm_debug(subdev, "\tnoRegions : %d\n", 138 hdr->regions.no_regions); 139 140 for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) { 141 nvkm_debug(subdev, "\tregion[%d] :\n", i); 142 nvkm_debug(subdev, "\t startAddr : 0x%x\n", 143 hdr->regions.region_props[i].start_addr); 144 nvkm_debug(subdev, "\t endAddr : 0x%x\n", 145 hdr->regions.region_props[i].end_addr); 146 nvkm_debug(subdev, "\t regionId : %d\n", 147 hdr->regions.region_props[i].region_id); 148 nvkm_debug(subdev, "\t readMask : 0x%x\n", 149 hdr->regions.region_props[i].read_mask); 150 nvkm_debug(subdev, "\t writeMask : 0x%x\n", 151 hdr->regions.region_props[i].write_mask); 152 nvkm_debug(subdev, "\t clientMask : 0x%x\n", 153 hdr->regions.region_props[i].client_mask); 154 nvkm_debug(subdev, "\t shadowMemStartAddr: 0x%x\n", 155 hdr->regions.region_props[i].shadow_mem_start_addr); 156 } 157 158 nvkm_debug(subdev, "\tucodeBlobSize : %d\n", 159 hdr->ucode_blob_size); 160 nvkm_debug(subdev, "\tucodeBlobBase : 0x%"PRIx64"\n", 161 hdr->ucode_blob_base); 162 nvkm_debug(subdev, "\tvprEnabled : %d\n", 163 hdr->vpr_desc.vpr_enabled); 164 nvkm_debug(subdev, "\tvprStart : 0x%x\n", 165 hdr->vpr_desc.vpr_start); 166 nvkm_debug(subdev, "\tvprEnd : 0x%x\n", 167 hdr->vpr_desc.vpr_end); 168 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n", 169 hdr->vpr_desc.hdcp_policies); 170 } 171
Indexes created Thu Sep 25 16:09:42 GMT 2025