1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 /* 30 * Authors: 31 * Kevin E. Martin <martin (at) xfree86.org> 32 * 33 * Modified by Marc Aurele La France <tsi (at) xfree86.org> for ATI driver merge. 34 */ 35 36 #ifndef _RADEON_PROBE_H_ 37 #define _RADEON_PROBE_H_ 1 38 39 #include <stdint.h> 40 #include "xf86str.h" 41 #include "xf86DDC.h" 42 #include "randrstr.h" 43 44 #include "xf86Crtc.h" 45 46 #include "compat-api.h" 47 #ifdef USE_EXA 48 #include "exa.h" 49 #endif 50 #ifdef USE_XAA 51 #include "xaa.h" 52 #endif 53 54 extern DriverRec RADEON; 55 56 #define RADEON_MAX_CRTC 6 57 #define RADEON_MAX_BIOS_CONNECTOR 16 58 59 typedef enum { 60 CHIP_FAMILY_UNKNOW, 61 CHIP_FAMILY_LEGACY, 62 CHIP_FAMILY_RADEON, 63 CHIP_FAMILY_RV100, 64 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ 65 CHIP_FAMILY_RV200, 66 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ 67 CHIP_FAMILY_R200, 68 CHIP_FAMILY_RV250, 69 CHIP_FAMILY_RS300, /* RS300/RS350 */ 70 CHIP_FAMILY_RV280, 71 CHIP_FAMILY_R300, 72 CHIP_FAMILY_R350, 73 CHIP_FAMILY_RV350, 74 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ 75 CHIP_FAMILY_R420, /* R420/R423/M18 */ 76 CHIP_FAMILY_RV410, /* RV410, M26 */ 77 CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ 78 CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ 79 CHIP_FAMILY_RV515, /* rv515 */ 80 CHIP_FAMILY_R520, /* r520 */ 81 CHIP_FAMILY_RV530, /* rv530 */ 82 CHIP_FAMILY_R580, /* r580 */ 83 CHIP_FAMILY_RV560, /* rv560 */ 84 CHIP_FAMILY_RV570, /* rv570 */ 85 CHIP_FAMILY_RS600, 86 CHIP_FAMILY_RS690, 87 CHIP_FAMILY_RS740, 88 CHIP_FAMILY_R600, /* r600 */ 89 CHIP_FAMILY_RV610, 90 CHIP_FAMILY_RV630, 91 CHIP_FAMILY_RV670, 92 CHIP_FAMILY_RV620, 93 CHIP_FAMILY_RV635, 94 CHIP_FAMILY_RS780, 95 CHIP_FAMILY_RS880, 96 CHIP_FAMILY_RV770, /* r700 */ 97 CHIP_FAMILY_RV730, 98 CHIP_FAMILY_RV710, 99 CHIP_FAMILY_RV740, 100 CHIP_FAMILY_CEDAR, /* evergreen */ 101 CHIP_FAMILY_REDWOOD, 102 CHIP_FAMILY_JUNIPER, 103 CHIP_FAMILY_CYPRESS, 104 CHIP_FAMILY_HEMLOCK, 105 CHIP_FAMILY_PALM, 106 CHIP_FAMILY_SUMO, 107 CHIP_FAMILY_SUMO2, 108 CHIP_FAMILY_BARTS, 109 CHIP_FAMILY_TURKS, 110 CHIP_FAMILY_CAICOS, 111 CHIP_FAMILY_CAYMAN, 112 CHIP_FAMILY_ARUBA, 113 CHIP_FAMILY_LAST 114 } RADEONChipFamily; 115 116 typedef struct { 117 uint32_t pci_device_id; 118 RADEONChipFamily chip_family; 119 int mobility; 120 int igp; 121 int nocrtc2; 122 int nointtvout; 123 int singledac; 124 } RADEONCardInfo; 125 126 typedef enum 127 { 128 MT_UNKNOWN = -1, 129 MT_NONE = 0, 130 MT_CRT = 1, 131 MT_LCD = 2, 132 MT_DFP = 3, 133 MT_CTV = 4, 134 MT_STV = 5, 135 MT_CV = 6, 136 MT_HDMI = 7, // this should really just be MT_DFP 137 MT_DP = 8 138 } RADEONMonitorType; 139 140 typedef enum 141 { 142 CONNECTOR_NONE, 143 CONNECTOR_VGA, 144 CONNECTOR_DVI_I, 145 CONNECTOR_DVI_D, 146 CONNECTOR_DVI_A, 147 CONNECTOR_STV, 148 CONNECTOR_CTV, 149 CONNECTOR_LVDS, 150 CONNECTOR_DIGITAL, 151 CONNECTOR_SCART, 152 CONNECTOR_HDMI_TYPE_A, 153 CONNECTOR_HDMI_TYPE_B, 154 CONNECTOR_0XC, 155 CONNECTOR_0XD, 156 CONNECTOR_DIN, 157 CONNECTOR_DISPLAY_PORT, 158 CONNECTOR_EDP, 159 CONNECTOR_UNSUPPORTED 160 } RADEONConnectorType; 161 162 typedef enum 163 { 164 DVI_AUTO, 165 DVI_DIGITAL, 166 DVI_ANALOG 167 } RADEONDviType; 168 169 typedef enum 170 { 171 RMX_OFF, 172 RMX_FULL, 173 RMX_CENTER, 174 RMX_ASPECT 175 } RADEONRMXType; 176 177 typedef struct { 178 uint32_t freq; 179 uint32_t value; 180 }RADEONTMDSPll; 181 182 /* standards */ 183 typedef enum 184 { 185 TV_STD_NTSC = 1, 186 TV_STD_PAL = 2, 187 TV_STD_PAL_M = 4, 188 TV_STD_PAL_60 = 8, 189 TV_STD_NTSC_J = 16, 190 TV_STD_SCART_PAL = 32, 191 TV_STD_SECAM = 64, 192 TV_STD_PAL_CN = 128, 193 } TVStd; 194 195 typedef struct 196 { 197 Bool valid; 198 uint32_t mask_clk_reg; 199 uint32_t mask_data_reg; 200 uint32_t a_clk_reg; 201 uint32_t a_data_reg; 202 uint32_t put_clk_reg; 203 uint32_t put_data_reg; 204 uint32_t get_clk_reg; 205 uint32_t get_data_reg; 206 uint32_t mask_clk_mask; 207 uint32_t mask_data_mask; 208 uint32_t put_clk_mask; 209 uint32_t put_data_mask; 210 uint32_t get_clk_mask; 211 uint32_t get_data_mask; 212 uint32_t a_clk_mask; 213 uint32_t a_data_mask; 214 int hw_line; 215 Bool hw_capable; 216 } RADEONI2CBusRec, *RADEONI2CBusPtr; 217 218 enum radeon_pll_algo { 219 RADEON_PLL_OLD, 220 RADEON_PLL_NEW 221 }; 222 223 typedef struct _RADEONCrtcPrivateRec { 224 void *crtc_rotate_mem; 225 void *cursor_mem; 226 int crtc_id; 227 int binding; 228 uint32_t cursor_offset; 229 /* Lookup table values to be set when the CRTC is enabled */ 230 uint16_t lut_r[256], lut_g[256], lut_b[256]; 231 232 uint32_t crtc_offset; 233 int can_tile; 234 Bool enabled; 235 Bool initialized; 236 Bool scaler_enabled; 237 float vsc; 238 float hsc; 239 int pll_id; 240 enum radeon_pll_algo pll_algo; 241 } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; 242 243 typedef struct _radeon_encoder { 244 uint16_t encoder_id; 245 int devices; 246 void *dev_priv; 247 } radeon_encoder_rec, *radeon_encoder_ptr; 248 249 typedef struct _radeon_tvout { 250 /* TV out */ 251 TVStd default_tvStd; 252 TVStd tvStd; 253 int hPos; 254 int vPos; 255 int hSize; 256 float TVRefClk; 257 int SupportedTVStds; 258 Bool tv_on; 259 } radeon_tvout_rec, *radeon_tvout_ptr; 260 261 typedef struct _radeon_native_mode { 262 /* panel stuff */ 263 int PanelXRes; 264 int PanelYRes; 265 int HOverPlus; 266 int HSyncWidth; 267 int HBlank; 268 int VOverPlus; 269 int VSyncWidth; 270 int VBlank; 271 int Flags; 272 int DotClock; 273 } radeon_native_mode_rec, *radeon_native_mode_ptr; 274 275 typedef struct _radeon_tvdac { 276 // tv dac 277 uint32_t ps2_tvdac_adj; 278 uint32_t pal_tvdac_adj; 279 uint32_t ntsc_tvdac_adj; 280 } radeon_tvdac_rec, *radeon_tvdac_ptr; 281 282 typedef struct _radeon_tmds { 283 // tmds 284 RADEONTMDSPll tmds_pll[4]; 285 } radeon_tmds_rec, *radeon_tmds_ptr; 286 287 typedef struct _radeon_lvds { 288 // panel mode 289 radeon_native_mode_rec native_mode; 290 // lvds 291 int PanelPwrDly; 292 int lvds_misc; 293 int lvds_ss_id; 294 } radeon_lvds_rec, *radeon_lvds_ptr; 295 296 typedef struct _radeon_dvo { 297 /* dvo */ 298 I2CBusPtr pI2CBus; 299 I2CDevPtr DVOChip; 300 RADEONI2CBusRec dvo_i2c; 301 int dvo_i2c_slave_addr; 302 Bool dvo_duallink; 303 } radeon_dvo_rec, *radeon_dvo_ptr; 304 305 typedef struct { 306 RADEONConnectorType ConnectorType; 307 Bool valid; 308 int output_id; 309 int devices; 310 int hpd_mask; 311 RADEONI2CBusRec ddc_i2c; 312 int igp_lane_info; 313 Bool shared_ddc; 314 int i2c_line_mux; 315 Bool load_detection; 316 Bool linkb; 317 uint16_t connector_object; 318 uint16_t connector_object_id; 319 uint8_t ucI2cId; 320 uint8_t hpd_id; 321 } RADEONBIOSConnector; 322 323 typedef struct _RADEONOutputPrivateRec { 324 uint16_t connector_id; 325 uint32_t devices; 326 uint32_t active_device; 327 Bool enabled; 328 329 int load_detection; 330 331 // DVI/HDMI 332 Bool coherent_mode; 333 Bool linkb; 334 335 RADEONConnectorType ConnectorType; 336 uint16_t connector_object_id; 337 RADEONDviType DVIType; 338 RADEONMonitorType MonType; 339 340 // DDC info 341 I2CBusPtr pI2CBus; 342 RADEONI2CBusRec ddc_i2c; 343 Bool shared_ddc; 344 345 Bool custom_edid; 346 xf86MonPtr custom_mon; 347 // router info 348 // HDP info 349 350 // panel mode 351 radeon_native_mode_rec native_mode; 352 353 // RMX 354 RADEONRMXType rmx_type; 355 int Flags; 356 357 //tvout - move to encoder 358 radeon_tvout_rec tvout; 359 360 /* dce 3.x dig block */ 361 int igp_lane_info; 362 int dig_encoder; 363 364 int pixel_clock; 365 366 /* DP - aux bus*/ 367 I2CBusPtr dp_pI2CBus; 368 uint8_t ucI2cId; 369 char dp_bus_name[20]; 370 uint32_t dp_i2c_addr; 371 Bool dp_i2c_running; 372 /* DP - general config */ 373 uint8_t dpcd[8]; 374 int dp_lane_count; 375 int dp_clock; 376 uint8_t hpd_id; 377 int pll_id; 378 } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; 379 380 struct avivo_pll_state { 381 uint32_t ref_div_src; 382 uint32_t ref_div; 383 uint32_t fb_div; 384 uint32_t post_div_src; 385 uint32_t post_div; 386 uint32_t ext_ppll_cntl; 387 uint32_t pll_cntl; 388 uint32_t int_ss_cntl; 389 }; 390 391 struct avivo_crtc_state { 392 uint32_t pll_source; 393 uint32_t h_total; 394 uint32_t h_blank_start_end; 395 uint32_t h_sync_a; 396 uint32_t h_sync_a_cntl; 397 uint32_t h_sync_b; 398 uint32_t h_sync_b_cntl; 399 uint32_t v_total; 400 uint32_t v_blank_start_end; 401 uint32_t v_sync_a; 402 uint32_t v_sync_a_cntl; 403 uint32_t v_sync_b; 404 uint32_t v_sync_b_cntl; 405 uint32_t control; 406 uint32_t blank_control; 407 uint32_t interlace_control; 408 uint32_t stereo_control; 409 uint32_t cursor_control; 410 }; 411 412 struct avivo_grph_state { 413 uint32_t enable; 414 uint32_t control; 415 uint32_t swap_control; 416 uint32_t prim_surf_addr; 417 uint32_t sec_surf_addr; 418 uint32_t pitch; 419 uint32_t prim_surf_addr_hi; 420 uint32_t sec_surf_addr_hi; 421 uint32_t x_offset; 422 uint32_t y_offset; 423 uint32_t x_start; 424 uint32_t y_start; 425 uint32_t x_end; 426 uint32_t y_end; 427 428 uint32_t desktop_height; 429 uint32_t viewport_start; 430 uint32_t viewport_size; 431 uint32_t mode_data_format; 432 }; 433 434 struct dce4_main_block_state { 435 struct avivo_grph_state grph; 436 uint32_t scl[6]; 437 uint32_t crtc[15]; 438 uint32_t fmt[10]; 439 uint32_t dig[20]; 440 }; 441 442 struct dce4_state 443 { 444 445 uint32_t vga1_cntl; 446 uint32_t vga2_cntl; 447 uint32_t vga3_cntl; 448 uint32_t vga4_cntl; 449 uint32_t vga5_cntl; 450 uint32_t vga6_cntl; 451 uint32_t vga_render_control; 452 453 struct dce4_main_block_state block[6]; 454 455 uint32_t vga_pll[3][3]; 456 uint32_t pll[2][15]; 457 uint32_t pll_route[6]; 458 459 uint32_t dac[2][26]; 460 uint32_t uniphy[6][10]; 461 462 uint32_t dig[20]; 463 }; 464 465 struct avivo_state 466 { 467 uint32_t hdp_fb_location; 468 uint32_t mc_memory_map; 469 uint32_t vga_memory_base; 470 uint32_t vga_fb_start; 471 472 uint32_t vga1_cntl; 473 uint32_t vga2_cntl; 474 uint32_t vga3_cntl; 475 uint32_t vga4_cntl; 476 uint32_t vga5_cntl; 477 uint32_t vga6_cntl; 478 uint32_t vga_render_control; 479 480 uint32_t crtc_master_en; 481 uint32_t crtc_tv_control; 482 uint32_t dc_lb_memory_split; 483 484 struct avivo_pll_state pll[2]; 485 486 struct avivo_pll_state vga25_ppll; 487 struct avivo_pll_state vga28_ppll; 488 struct avivo_pll_state vga41_ppll; 489 490 struct avivo_crtc_state crtc[2]; 491 492 struct avivo_grph_state grph[2]; 493 494 /* DDIA block on RS6xx chips */ 495 uint32_t ddia[37]; 496 497 /* scalers */ 498 uint32_t d1scl[40]; 499 uint32_t d2scl[40]; 500 uint32_t dxscl[6+2]; 501 502 /* dac regs */ 503 uint32_t daca[26]; 504 uint32_t dacb[26]; 505 506 /* tmdsa */ 507 uint32_t tmdsa[31]; 508 509 /* lvtma */ 510 uint32_t lvtma[39]; 511 512 /* dvoa */ 513 uint32_t dvoa[16]; 514 515 /* DCE3+ chips */ 516 uint32_t fmt1[18]; 517 uint32_t fmt2[18]; 518 uint32_t dig1[19]; 519 uint32_t dig2[19]; 520 uint32_t hdmi1[57]; 521 uint32_t hdmi2[57]; 522 uint32_t aux_cntl1[14]; 523 uint32_t aux_cntl2[14]; 524 uint32_t aux_cntl3[14]; 525 uint32_t aux_cntl4[14]; 526 uint32_t aux_cntl5[14]; 527 uint32_t aux_cntl6[14]; 528 uint32_t phy[10]; 529 uint32_t uniphy1[8]; 530 uint32_t uniphy2[8]; 531 uint32_t uniphy3[8]; 532 uint32_t uniphy4[8]; 533 uint32_t uniphy5[8]; 534 uint32_t uniphy6[8]; 535 536 }; 537 538 /* 539 * Maximum length of horizontal/vertical code timing tables for state storage 540 */ 541 #define MAX_H_CODE_TIMING_LEN 32 542 #define MAX_V_CODE_TIMING_LEN 32 543 544 typedef struct { 545 struct avivo_state avivo; 546 struct dce4_state dce4; 547 548 /* Common registers */ 549 uint32_t ovr_clr; 550 uint32_t ovr_wid_left_right; 551 uint32_t ovr_wid_top_bottom; 552 uint32_t ov0_scale_cntl; 553 uint32_t mpp_tb_config; 554 uint32_t mpp_gp_config; 555 uint32_t subpic_cntl; 556 uint32_t viph_control; 557 uint32_t i2c_cntl_1; 558 uint32_t gen_int_cntl; 559 uint32_t cap0_trig_cntl; 560 uint32_t cap1_trig_cntl; 561 uint32_t bus_cntl; 562 563 uint32_t bios_0_scratch; 564 uint32_t bios_1_scratch; 565 uint32_t bios_2_scratch; 566 uint32_t bios_3_scratch; 567 uint32_t bios_4_scratch; 568 uint32_t bios_5_scratch; 569 uint32_t bios_6_scratch; 570 uint32_t bios_7_scratch; 571 572 uint32_t surface_cntl; 573 uint32_t surfaces[8][3]; 574 uint32_t mc_agp_location; 575 uint32_t mc_agp_location_hi; 576 uint32_t mc_fb_location; 577 uint32_t display_base_addr; 578 uint32_t display2_base_addr; 579 uint32_t ov0_base_addr; 580 581 /* Other registers to save for VT switches */ 582 uint32_t dp_datatype; 583 uint32_t rbbm_soft_reset; 584 uint32_t clock_cntl_index; 585 uint32_t amcgpio_en_reg; 586 uint32_t amcgpio_mask; 587 588 /* CRTC registers */ 589 uint32_t crtc_gen_cntl; 590 uint32_t crtc_ext_cntl; 591 uint32_t dac_cntl; 592 uint32_t crtc_h_total_disp; 593 uint32_t crtc_h_sync_strt_wid; 594 uint32_t crtc_v_total_disp; 595 uint32_t crtc_v_sync_strt_wid; 596 uint32_t crtc_offset; 597 uint32_t crtc_offset_cntl; 598 uint32_t crtc_pitch; 599 uint32_t disp_merge_cntl; 600 uint32_t grph_buffer_cntl; 601 uint32_t crtc_more_cntl; 602 uint32_t crtc_tile_x0_y0; 603 604 /* CRTC2 registers */ 605 uint32_t crtc2_gen_cntl; 606 uint32_t dac_macro_cntl; 607 uint32_t dac2_cntl; 608 uint32_t disp_output_cntl; 609 uint32_t disp_tv_out_cntl; 610 uint32_t disp_hw_debug; 611 uint32_t disp2_merge_cntl; 612 uint32_t grph2_buffer_cntl; 613 uint32_t crtc2_h_total_disp; 614 uint32_t crtc2_h_sync_strt_wid; 615 uint32_t crtc2_v_total_disp; 616 uint32_t crtc2_v_sync_strt_wid; 617 uint32_t crtc2_offset; 618 uint32_t crtc2_offset_cntl; 619 uint32_t crtc2_pitch; 620 uint32_t crtc2_tile_x0_y0; 621 622 /* Flat panel registers */ 623 uint32_t fp_crtc_h_total_disp; 624 uint32_t fp_crtc_v_total_disp; 625 uint32_t fp_gen_cntl; 626 uint32_t fp2_gen_cntl; 627 uint32_t fp_h_sync_strt_wid; 628 uint32_t fp_h2_sync_strt_wid; 629 uint32_t fp_horz_stretch; 630 uint32_t fp_horz_vert_active; 631 uint32_t fp_panel_cntl; 632 uint32_t fp_v_sync_strt_wid; 633 uint32_t fp_v2_sync_strt_wid; 634 uint32_t fp_vert_stretch; 635 uint32_t lvds_gen_cntl; 636 uint32_t lvds_pll_cntl; 637 uint32_t tmds_pll_cntl; 638 uint32_t tmds_transmitter_cntl; 639 640 /* Computed values for PLL */ 641 uint32_t dot_clock_freq; 642 uint32_t pll_output_freq; 643 int feedback_div; 644 int reference_div; 645 int post_div; 646 647 /* PLL registers */ 648 unsigned ppll_ref_div; 649 unsigned ppll_div_3; 650 uint32_t htotal_cntl; 651 uint32_t vclk_ecp_cntl; 652 653 /* Computed values for PLL2 */ 654 uint32_t dot_clock_freq_2; 655 uint32_t pll_output_freq_2; 656 int feedback_div_2; 657 int reference_div_2; 658 int post_div_2; 659 660 /* PLL2 registers */ 661 uint32_t p2pll_ref_div; 662 uint32_t p2pll_div_0; 663 uint32_t htotal_cntl2; 664 uint32_t pixclks_cntl; 665 666 /* Pallet */ 667 Bool palette_valid; 668 Bool palette_saved[2]; 669 uint32_t palette[2][256]; 670 671 uint32_t disp2_req_cntl1; 672 uint32_t disp2_req_cntl2; 673 uint32_t dmif_mem_cntl1; 674 uint32_t disp1_req_cntl1; 675 676 uint32_t fp_2nd_gen_cntl; 677 uint32_t fp2_2_gen_cntl; 678 uint32_t tmds2_cntl; 679 uint32_t tmds2_transmitter_cntl; 680 681 682 /* TV out registers */ 683 uint32_t tv_master_cntl; 684 uint32_t tv_htotal; 685 uint32_t tv_hsize; 686 uint32_t tv_hdisp; 687 uint32_t tv_hstart; 688 uint32_t tv_vtotal; 689 uint32_t tv_vdisp; 690 uint32_t tv_timing_cntl; 691 uint32_t tv_vscaler_cntl1; 692 uint32_t tv_vscaler_cntl2; 693 uint32_t tv_sync_size; 694 uint32_t tv_vrestart; 695 uint32_t tv_hrestart; 696 uint32_t tv_frestart; 697 uint32_t tv_ftotal; 698 uint32_t tv_clock_sel_cntl; 699 uint32_t tv_clkout_cntl; 700 uint32_t tv_data_delay_a; 701 uint32_t tv_data_delay_b; 702 uint32_t tv_dac_cntl; 703 uint32_t tv_pll_cntl; 704 uint32_t tv_pll_cntl1; 705 uint32_t tv_pll_fine_cntl; 706 uint32_t tv_modulator_cntl1; 707 uint32_t tv_modulator_cntl2; 708 uint32_t tv_frame_lock_cntl; 709 uint32_t tv_pre_dac_mux_cntl; 710 uint32_t tv_rgb_cntl; 711 uint32_t tv_y_saw_tooth_cntl; 712 uint32_t tv_y_rise_cntl; 713 uint32_t tv_y_fall_cntl; 714 uint32_t tv_uv_adr; 715 uint32_t tv_upsamp_and_gain_cntl; 716 uint32_t tv_gain_limit_settings; 717 uint32_t tv_linear_gain_settings; 718 uint32_t tv_crc_cntl; 719 uint32_t tv_sync_cntl; 720 uint32_t gpiopad_a; 721 uint32_t pll_test_cntl; 722 723 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 724 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 725 726 } RADEONSaveRec, *RADEONSavePtr; 727 728 typedef struct 729 { 730 Bool HasSecondary; 731 Bool HasCRTC2; /* All cards except original Radeon */ 732 /* 733 * The next two are used to make sure CRTC2 is restored before CRTC_EXT, 734 * otherwise it could lead to blank screens. 735 */ 736 Bool IsSecondaryRestored; 737 Bool RestorePrimary; 738 739 Bool ReversedDAC; /* TVDAC used as primary dac */ 740 Bool ReversedTMDS; /* DDC_DVI is used for external TMDS */ 741 xf86CrtcPtr pCrtc[RADEON_MAX_CRTC]; 742 RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC]; 743 744 ScrnInfoPtr pSecondaryScrn; 745 ScrnInfoPtr pPrimaryScrn; 746 747 RADEONSaveRec ModeReg; /* Current mode */ 748 RADEONSaveRec SavedReg; /* Original (text) mode */ 749 750 void *MMIO; /* Map of MMIO region */ 751 int MMIO_cnt; /* Map of FB region refcount */ 752 void *FB; /* Map of FB region */ 753 int FB_cnt; /* Map of FB region refcount */ 754 int fd; /* for sharing across zaphod heads */ 755 unsigned long fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */ 756 int dri2_info_cnt; 757 } RADEONEntRec, *RADEONEntPtr; 758 759 /* radeon_probe.c */ 760 extern PciChipsets RADEONPciChipsets[]; 761 762 /* radeon_driver.c */ 763 extern Bool RADEONPreInit(ScrnInfoPtr, int); 764 extern Bool RADEONScreenInit(SCREEN_INIT_ARGS_DECL); 765 extern Bool RADEONSwitchMode(SWITCH_MODE_ARGS_DECL); 766 #ifdef X_XF86MiscPassMessage 767 extern Bool RADEONHandleMessage(int, const char*, const char*, 768 char**); 769 #endif 770 extern void RADEONAdjustFrame(ADJUST_FRAME_ARGS_DECL); 771 extern Bool RADEONEnterVT(VT_FUNC_ARGS_DECL); 772 extern void RADEONLeaveVT(VT_FUNC_ARGS_DECL); 773 extern void RADEONFreeScreen(FREE_SCREEN_ARGS_DECL); 774 extern ModeStatus RADEONValidMode(SCRN_ARG_TYPE, DisplayModePtr, Bool, int); 775 776 extern const OptionInfoRec *RADEONOptionsWeak(void); 777 778 #ifdef XF86DRM_MODE 779 extern Bool RADEONPreInit_KMS(ScrnInfoPtr, int); 780 extern Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL); 781 extern Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL); 782 extern void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL); 783 extern Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL); 784 extern void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL); 785 extern void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL); 786 #endif 787 788 #endif /* _RADEON_PROBE_H_ */ 789
Indexes created Sun Jul 19 00:25:04 UTC 2026