1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 26 #ifndef AC_GPU_INFO_H 27 #define AC_GPU_INFO_H 28 29 #include "amd_family.h" 30 31 #include <stdbool.h> 32 #include <stddef.h> 33 #include <stdint.h> 34 #include <stdio.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 struct amdgpu_gpu_info; 41 42 struct radeon_info { 43 /* PCI info: domain:bus:dev:func */ 44 uint32_t pci_domain; 45 uint32_t pci_bus; 46 uint32_t pci_dev; 47 uint32_t pci_func; 48 49 /* Device info. */ 50 const char *name; 51 const char *marketing_name; 52 bool is_pro_graphics; 53 uint32_t pci_id; 54 uint32_t pci_rev_id; 55 enum radeon_family family; 56 enum chip_class chip_class; 57 uint32_t family_id; 58 uint32_t chip_external_rev; 59 uint32_t clock_crystal_freq; 60 61 /* Features. */ 62 bool has_graphics; /* false if the chip is compute-only */ 63 uint32_t num_rings[NUM_RING_TYPES]; 64 uint32_t ib_pad_dw_mask[NUM_RING_TYPES]; 65 bool has_clear_state; 66 bool has_distributed_tess; 67 bool has_dcc_constant_encode; 68 bool has_rbplus; /* if RB+ registers exist */ 69 bool rbplus_allowed; /* if RB+ is allowed */ 70 bool has_load_ctx_reg_pkt; 71 bool has_out_of_order_rast; 72 bool has_packed_math_16bit; 73 bool has_accelerated_dot_product; 74 bool cpdma_prefetch_writes_memory; 75 bool has_gfx9_scissor_bug; 76 bool has_tc_compat_zrange_bug; 77 bool has_msaa_sample_loc_bug; 78 bool has_ls_vgpr_init_bug; 79 bool has_zero_index_buffer_bug; 80 bool has_image_load_dcc_bug; 81 bool has_two_planes_iterate256_bug; 82 bool has_vgt_flush_ngg_legacy_bug; 83 bool has_cs_regalloc_hang_bug; 84 bool has_32bit_predication; 85 bool has_3d_cube_border_color_mipmap; 86 87 /* Display features. */ 88 /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ 89 /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ 90 bool use_display_dcc_unaligned; 91 /* Allocate both aligned and unaligned DCC and use the retile blit. */ 92 bool use_display_dcc_with_retile_blit; 93 94 /* Memory info. */ 95 uint32_t pte_fragment_size; 96 uint32_t gart_page_size; 97 uint32_t gart_size_kb; 98 uint32_t vram_size_kb; 99 uint64_t gart_size; 100 uint64_t vram_size; 101 uint64_t vram_vis_size; 102 uint32_t vram_bit_width; 103 uint32_t vram_type; 104 unsigned gds_size; 105 unsigned gds_gfx_partition_size; 106 uint64_t max_alloc_size; 107 uint32_t min_alloc_size; 108 uint32_t address32_hi; 109 bool has_dedicated_vram; 110 bool all_vram_visible; 111 bool smart_access_memory; 112 bool has_l2_uncached; 113 bool r600_has_virtual_memory; 114 uint32_t max_tcc_blocks; 115 uint32_t num_tcc_blocks; 116 uint32_t tcc_cache_line_size; 117 bool tcc_rb_non_coherent; /* whether L2 inv is needed for render->texture transitions */ 118 unsigned pc_lines; 119 uint32_t lds_size_per_workgroup; 120 uint32_t lds_alloc_granularity; 121 uint32_t lds_encode_granularity; 122 uint32_t max_memory_clock; 123 uint32_t ce_ram_size; 124 uint32_t l1_cache_size; 125 uint32_t l2_cache_size; 126 127 /* CP info. */ 128 bool gfx_ib_pad_with_type2; 129 unsigned ib_alignment; /* both start and size alignment */ 130 uint32_t me_fw_version; 131 uint32_t me_fw_feature; 132 uint32_t pfp_fw_version; 133 uint32_t pfp_fw_feature; 134 uint32_t ce_fw_version; 135 uint32_t ce_fw_feature; 136 137 /* Multimedia info. */ 138 struct { 139 bool uvd_decode; 140 bool vcn_decode; 141 bool jpeg_decode; 142 bool vce_encode; 143 bool uvd_encode; 144 bool vcn_encode; 145 } has_video_hw; 146 147 uint32_t uvd_fw_version; 148 uint32_t vce_fw_version; 149 uint32_t vce_harvest_config; 150 struct video_caps_info { 151 struct { 152 uint32_t valid; 153 uint32_t max_width; 154 uint32_t max_height; 155 uint32_t max_pixels_per_frame; 156 uint32_t max_level; 157 uint32_t pad; 158 } codec_info[8]; /* the number of available codecs */ 159 } dec_caps, enc_caps; 160 161 /* Kernel & winsys capabilities. */ 162 uint32_t drm_major; /* version */ 163 uint32_t drm_minor; 164 uint32_t drm_patchlevel; 165 bool is_amdgpu; 166 bool has_userptr; 167 bool has_syncobj; 168 bool has_timeline_syncobj; 169 bool has_fence_to_handle; 170 bool has_local_buffers; 171 bool kernel_flushes_hdp_before_ib; 172 bool htile_cmask_support_1d_tiling; 173 bool si_TA_CS_BC_BASE_ADDR_allowed; 174 bool has_bo_metadata; 175 bool has_gpu_reset_status_query; 176 bool has_eqaa_surface_allocator; 177 bool has_format_bc1_through_bc7; 178 bool kernel_flushes_tc_l2_after_ib; 179 bool has_indirect_compute_dispatch; 180 bool has_unaligned_shader_loads; 181 bool has_sparse_vm_mappings; 182 bool has_2d_tiling; 183 bool has_read_registers_query; 184 bool has_gds_ordered_append; 185 bool has_scheduled_fence_dependency; 186 /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */ 187 bool mid_command_buffer_preemption_enabled; 188 bool has_tmz_support; 189 bool kernel_has_modifiers; 190 191 /* Shader cores. */ 192 uint32_t cu_mask[4][2]; 193 uint32_t r600_max_quad_pipes; /* wave size / 16 */ 194 uint32_t max_shader_clock; 195 uint32_t num_good_compute_units; 196 uint32_t max_good_cu_per_sa; 197 uint32_t min_good_cu_per_sa; /* min != max if SAs have different # of CUs */ 198 uint32_t max_se; /* number of shader engines incl. disabled ones */ 199 uint32_t num_se; /* number of enabled shader engines */ 200 uint32_t max_sa_per_se; /* shader arrays per shader engine */ 201 uint32_t max_wave64_per_simd; 202 uint32_t num_physical_sgprs_per_simd; 203 uint32_t num_physical_wave64_vgprs_per_simd; 204 uint32_t num_simd_per_compute_unit; 205 uint32_t min_sgpr_alloc; 206 uint32_t max_sgpr_alloc; 207 uint32_t sgpr_alloc_granularity; 208 uint32_t min_wave64_vgpr_alloc; 209 uint32_t max_vgpr_alloc; 210 uint32_t wave64_vgpr_alloc_granularity; 211 212 /* Render backends (color + depth blocks). */ 213 uint32_t r300_num_gb_pipes; 214 uint32_t r300_num_z_pipes; 215 uint32_t r600_gb_backend_map; /* R600 harvest config */ 216 bool r600_gb_backend_map_valid; 217 uint32_t r600_num_banks; 218 uint32_t mc_arb_ramcfg; 219 uint32_t gb_addr_config; 220 uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */ 221 uint32_t max_render_backends; /* number of render backends incl. disabled ones */ 222 uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ 223 uint32_t pipe_interleave_bytes; 224 uint32_t enabled_rb_mask; /* GCN harvest config */ 225 uint64_t max_alignment; /* from addrlib */ 226 uint32_t pbb_max_alloc_count; 227 228 /* Tile modes. */ 229 uint32_t si_tile_mode_array[32]; 230 uint32_t cik_macrotile_mode_array[16]; 231 }; 232 233 bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, 234 struct amdgpu_gpu_info *amdinfo); 235 236 void ac_compute_driver_uuid(char *uuid, size_t size); 237 238 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size); 239 void ac_print_gpu_info(struct radeon_info *info, FILE *f); 240 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family); 241 void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p, 242 uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p); 243 void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, 244 unsigned *cik_raster_config_1_p, unsigned *raster_config_se); 245 unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves_per_threadgroup, 246 unsigned max_waves_per_sh, unsigned threadgroups_per_cu); 247 248 #ifdef __cplusplus 249 } 250 #endif 251 252 #endif /* AC_GPU_INFO_H */ 253
Indexes created Mon Aug 03 00:25:36 UTC 2026