| /src/sys/dev/mca/ |
| aha_mca.c | 106 mca_chipset_tag_t mc = ma->ma_mc; local in function:aha_mca_attach
168 sc->sc_ih = mca_intr_establish(mc, apd.sc_irq, IPL_BIO, aha_intr, sc);
|
| mca.c | 113 mca_chipset_tag_t mc; local in function:mca_attach
122 mc = mba->mba_mc;
142 ma.ma_mc = mc;
146 ma.ma_pos[reg]=mca_conf_read(mc, slot, reg);
|
| /src/lib/libskey/ |
| skey.h | 32 struct mc { struct
|
| /src/sys/dev/ic/ |
| msm6258.c | 69 pcm2adpcm_step(struct msm6258_codecvar *mc, int16_t a)
71 int estim = (int)mc->mc_estim;
77 df = a - mc->mc_amp;
90 mc->mc_amp += (short)(adpcm_estimindex[(int)s] * dl);
97 mc->mc_estim = estim;
104 struct msm6258_codecvar *mc; local in function:msm6258_internal_to_adpcm
112 mc = arg->context;
122 f = pcm2adpcm_step(mc, s);
126 f |= pcm2adpcm_step(mc, s) << 4;
137 adpcm2pcm_step(struct msm6258_codecvar *mc, uint8_t b
157 struct msm6258_codecvar *mc; local in function:msm6258_adpcm_to_internal
[all...] |
| ld_mlx.c | 155 struct mlx_ccb *mc; local in function:ld_mlx_dobio
162 if ((rv = mlx_ccb_alloc(mlx, &mc, bp == NULL)) != 0)
166 rv = mlx_ccb_map(mlx, mc, data, datasize,
169 mlx_ccb_free(mlx, mc);
174 sgphys = mlx->mlx_sgls_paddr + (MLX_SGL_SIZE * mc->mc_ident);
178 mlx_make_type1(mc,
181 mc->mc_nsgent);
183 mlx_make_type5(mc,
187 blkno, sgphys, mc->mc_nsgent);
191 rv = mlx_ccb_poll(mlx, mc, 10000)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mc/ |
| nouveau_nvkm_subdev_mc_gp100.c | 40 gp100_mc_intr_update(struct gp100_mc *mc)
42 struct nvkm_device *device = mc->base.subdev.device;
43 u32 mask = mc->intr ? mc->mask : 0, i;
53 struct gp100_mc *mc = gp100_mc(base); local in function:gp100_mc_intr_unarm
55 spin_lock_irqsave(&mc->lock, flags);
56 mc->intr = false;
57 gp100_mc_intr_update(mc);
58 spin_unlock_irqrestore(&mc->lock, flags);
64 struct gp100_mc *mc = gp100_mc(base) local in function:gp100_mc_intr_rearm
75 struct gp100_mc *mc = gp100_mc(base); local in function:gp100_mc_intr_mask
124 struct gp100_mc *mc; local in function:gp100_mc_new_
[all...] |
| nouveau_nvkm_subdev_mc_base.c | 37 struct nvkm_mc *mc = device->mc; local in function:nvkm_mc_unk260
38 if (likely(mc) && mc->func->unk260)
39 mc->func->unk260(mc, data);
45 struct nvkm_mc *mc = device->mc; local in function:nvkm_mc_intr_mask
47 if (likely(mc) && mc->func->intr_mask)
60 struct nvkm_mc *mc = device->mc; local in function:nvkm_mc_intr_unarm
68 struct nvkm_mc *mc = device->mc; local in function:nvkm_mc_intr_rearm
85 struct nvkm_mc *mc = device->mc; local in function:nvkm_mc_intr
125 struct nvkm_mc *mc = device->mc; local in function:nvkm_mc_reset_mask
192 struct nvkm_mc *mc = nvkm_mc(subdev); local in function:nvkm_mc_init
202 struct nvkm_mc *mc = nvkm_mc(subdev); local in function:nvkm_mc_dtor
227 struct nvkm_mc *mc; local in function:nvkm_mc_new_
[all...] |
| /src/lib/libossaudio/ |
| oss4_mixer.c | 60 struct mixer_ctrl mc; local in function:_oss4_mixer_ioctl
453 mdi.index = mc.dev = mv->ctrl - 1;
461 mc.type = mdi.type;
469 mc.un.ord = mdi.un.e.member[mv->value].ord;
478 mc.un.mask = 0;
481 mc.un.mask |= mdi.un.s.member[mv->value].mask;
485 mc.un.mask = mdi.un.s.member[mv->value].mask;
489 mc.un.value.num_channels = mdi.un.v.num_channels;
492 mc.un.value.level[i] = mv->value;
495 mc.un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
[all...] |
| oss3_mixer.c | 61 mixer_ctrl_t mc; local in function:_oss3_mixer_ioctl
92 mc.dev = di->source;
94 mc.type = AUDIO_MIXER_ENUM;
95 retval = ioctl(fd, AUDIO_MIXER_READ, &mc);
98 e = opaque_to_enum(di, NULL, mc.un.ord);
102 mc.type = AUDIO_MIXER_SET;
103 retval = ioctl(fd, AUDIO_MIXER_READ, &mc);
106 e = opaque_to_enum(di, NULL, mc.un.mask);
129 mc.dev = di->source;
132 mc.type = AUDIO_MIXER_ENUM
[all...] |
| /src/sys/crypto/aes/arch/arm/ |
| aes_neon_32.S | 57 .type mc,_ASM_TYPE_OBJECT
58 mc: label
76 END(mc)
203 * r4: mc
217 * q12={d24-d25}: ir/iak/iakr/sb1_0(io)/mc[rmod4].backward
218 * q13={d26-d27}: jr/jak/jakr/sb1_1(jo)/mc[rmod4].forward
246 /* r4 := mc */
247 add r4, ip, #(mc - .Lconstants)
282 add r6, r4, r3, lsl #5 /* r6 := &mc[rmod4] */
285 /* (q12, q13) := (mc[rmod4].forward, mc[rmod4].backward) *
[all...] |
| /src/sys/dev/fdt/ |
| fdt_mbox.c | 63 struct fdtbus_mbox_controller *mc; local in function:fdtbus_register_mbox_controller
71 mc = kmem_alloc(sizeof(*mc), KM_SLEEP);
72 mc->mc_dev = dev;
73 mc->mc_phandle = phandle;
74 mc->mc_funcs = funcs;
75 mc->mc_cells = cells;
77 LIST_INSERT_HEAD(&fdtbus_mbox_controllers, mc, mc_next);
85 struct fdtbus_mbox_controller *mc; local in function:fdtbus_mbox_lookup
87 LIST_FOREACH(mc, &fdtbus_mbox_controllers, mc_next)
98 struct fdtbus_mbox_controller *mc; local in function:fdtbus_mbox_get_index
163 struct fdtbus_mbox_controller *mc = mbox->mb_ctlr; local in function:fdtbus_mbox_put
172 struct fdtbus_mbox_controller * const mc = mbox->mb_ctlr; local in function:fdtbus_mbox_send
180 struct fdtbus_mbox_controller * const mc = mbox->mb_ctlr; local in function:fdtbus_mbox_recv
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| tegra114.dtsi | 4 #include <dt-bindings/memory/tegra114-mc.h>
30 iommus = <&mc TEGRA_SWGROUP_HC>;
45 iommus = <&mc TEGRA_SWGROUP_G2>;
55 iommus = <&mc TEGRA_SWGROUP_NV>;
68 iommus = <&mc TEGRA_SWGROUP_DC>;
87 iommus = <&mc TEGRA_SWGROUP_DCB>;
537 mc: memory-controller@70019000 { label
538 compatible = "nvidia,tegra114-mc";
541 clock-names = "mc";
|
| tegra20.dtsi | 4 #include <dt-bindings/memory/tegra20-mc.h>
116 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
117 <&mc TEGRA20_MC_DISPLAY0B &emc>,
118 <&mc TEGRA20_MC_DISPLAY1B &emc>,
119 <&mc TEGRA20_MC_DISPLAY0C &emc>,
120 <&mc TEGRA20_MC_DISPLAYHC &emc>;
144 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
145 <&mc TEGRA20_MC_DISPLAY0BB &emc>,
146 <&mc TEGRA20_MC_DISPLAY1BB &emc>,
147 <&mc TEGRA20_MC_DISPLAY0CB &emc>
648 mc: memory-controller@7000f000 { label
[all...] |
| tegra124.dtsi | 4 #include <dt-bindings/memory/tegra124-mc.h>
99 iommus = <&mc TEGRA_SWGROUP_HC>;
115 iommus = <&mc TEGRA_SWGROUP_DC>;
119 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>,
120 <&mc TEGRA124_MC_DISPLAY0B &emc>,
121 <&mc TEGRA124_MC_DISPLAY0C &emc>,
122 <&mc TEGRA124_MC_DISPLAYHC &emc>,
123 <&mc TEGRA124_MC_DISPLAYD &emc>,
124 <&mc TEGRA124_MC_DISPLAYT &emc>;
142 iommus = <&mc TEGRA_SWGROUP_DCB>
649 mc: memory-controller@70019000 { label
[all...] |
| tegra30.dtsi | 4 #include <dt-bindings/memory/tegra30-mc.h>
126 iommus = <&mc TEGRA_SWGROUP_HC>;
141 iommus = <&mc TEGRA_SWGROUP_MPE>;
152 iommus = <&mc TEGRA_SWGROUP_VI>;
163 iommus = <&mc TEGRA_SWGROUP_EPP>;
174 iommus = <&mc TEGRA_SWGROUP_ISP>;
185 iommus = <&mc TEGRA_SWGROUP_G2>;
198 iommus = <&mc TEGRA_SWGROUP_NV>,
199 <&mc TEGRA_SWGROUP_NV2>;
212 iommus = <&mc TEGRA_SWGROUP_DC>
770 mc: memory-controller@7000f000 { label
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/ |
| tegra132.dtsi | 4 #include <dt-bindings/memory/tegra124-mc.h>
108 iommus = <&mc TEGRA_SWGROUP_DC>;
122 iommus = <&mc TEGRA_SWGROUP_DCB>;
601 mc: memory-controller@70019000 { label
602 compatible = "nvidia,tegra132-mc";
605 clock-names = "mc";
618 nvidia,memory-controller = <&mc>;
|
| /src/tests/lib/libc/string/ |
| t_memcpy.c | 43 MD5_CTX mc[1]; variable in typeref:typename:MD5_CTX[1]
71 MD5Update(mc, b1, sizeof(testBlock_t));
72 MD5Update(mc, b2, sizeof(testBlock_t));
93 MD5Init(mc);
98 MD5End(mc, result);
|
| /src/usr.sbin/mrouted/ |
| kern.c | 151 struct mfcctl mc; local in function:k_add_rg
158 mc.mfcc_origin.s_addr = origin;
160 mc.mfcc_originmask.s_addr = 0xffffffff;
162 mc.mfcc_mcastgrp.s_addr = g->gt_mcastgrp;
163 mc.mfcc_parent = g->gt_route ? g->gt_route->rt_parent : NO_VIF;
165 mc.mfcc_ttls[i] = g->gt_ttls[i];
169 (char *)&mc, sizeof(mc)) < 0) {
183 struct mfcctl mc; local in function:k_del_rg
190 mc.mfcc_origin.s_addr = origin
[all...] |
| /src/sys/arch/amiga/stand/bootblock/boot/ |
| console.c | 109 struct Console *mc; local in function:consinit
113 mc = consptr; /* Use existing console */
117 mc = &myConsole;
122 mc->s = OpenScreenTagList(0, screentags);
123 if (!mc->s)
126 windowtags[1] = (u_int32_t)mc->s;
127 mc->w = OpenWindowTagList(0, windowtags);
128 if (!mc->w)
131 mc->cnmp = CreateMsgPort();
133 if (!mc->cnmp
201 struct Console *mc = ConsoleBase; local in function:consclose
233 struct Console *mc = ConsoleBase; local in function:putchar
251 struct Console *mc = ConsoleBase; local in function:puts
272 struct Console *mc = ConsoleBase; local in function:getchar
[all...] |
| /src/sys/dev/mscp/ |
| mscp.c | 170 struct mscp_ctlr *mc = mi->mi_mc; local in function:mscp_dorsp
423 (*mc->mc_ctlrdone)(device_parent(mi->mi_dev));
|
| /src/sys/kern/ |
| kern_ctf.c | 75 mod_ctf_t *mc; local in function:mod_ctf_get
88 * Return the cached mc if there is one already.
93 mc = module_getspecific(mod, fbt_module_key);
94 if (mc != NULL) {
95 *mcp = mc;
100 * Allocate and initialize a new mc.
103 mc = kmem_zalloc(sizeof(mod_ctf_t), KM_SLEEP);
106 mc->nmap = st->sd_nmap;
107 mc->nmapsize = st->sd_nmapsize;
120 mc->symtab = st->sd_symstart
[all...] |
| /src/sys/arch/cesfic/cesfic/ |
| dp8570a.h | 17 u_int8_t s100c, sc, minc, hc, dmc, mc, yc, jc, j100c, dwc; member in struct:dp8570reg
|
| /src/sys/arch/mips/mips/ |
| netbsd32_machdep.c | 215 mcontext_t mc; local in function:cpu_getmcontext32
223 cpu_getmcontext(l, &mc, flagsp);
224 for (i = 1; i < __arraycount(mc.__gregs); i++)
225 mco32->__gregs[i] = mc.__gregs[i];
227 memcpy(&mco32->__fpregs, &mc.__fpregs,
229 mco32->_mc_tlsbase = mc._mc_tlsbase;
243 mcontext_t mc; local in function:cpu_setmcontext32
255 for (i = 0; i < __arraycount(mc.__gregs); i++)
256 mc.__gregs[i] = mco32->__gregs[i];
258 memcpy(&mc.__fpregs, &mco32->__fpregs
[all...] |
| /src/sys/arch/emips/ebus/ |
| clock_ebus.c | 287 struct _Tc *mc = (struct _Tc *)ia->ia_vaddr; local in function:eclock_ebus_match
291 if ((mc == NULL) ||
292 (mc->Tag != PMTTAG_TIMER))
|
| /src/games/rogue/ |
| score.c | 168 boolean mc; local in function:quit
171 mc = FALSE;
178 mc = msg_cleared;
193 msg_cleared = mc;
|
