1 /* $NetBSD: smu7_hwmgr.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef _SMU7_HWMGR_H 27 #define _SMU7_HWMGR_H 28 29 #include "hwmgr.h" 30 #include "ppatomctrl.h" 31 32 #define SMU7_MAX_HARDWARE_POWERLEVELS 2 33 34 #define SMU7_VOLTAGE_CONTROL_NONE 0x0 35 #define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1 36 #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2 37 #define SMU7_VOLTAGE_CONTROL_MERGED 0x3 38 39 enum gpu_pt_config_reg_type { 40 GPU_CONFIGREG_MMR = 0, 41 GPU_CONFIGREG_SMC_IND, 42 GPU_CONFIGREG_DIDT_IND, 43 GPU_CONFIGREG_GC_CAC_IND, 44 GPU_CONFIGREG_CACHE, 45 GPU_CONFIGREG_MAX 46 }; 47 48 struct gpu_pt_config_reg { 49 uint32_t offset; 50 uint32_t mask; 51 uint32_t shift; 52 uint32_t value; 53 enum gpu_pt_config_reg_type type; 54 }; 55 56 struct smu7_performance_level { 57 uint32_t memory_clock; 58 uint32_t engine_clock; 59 uint16_t pcie_gen; 60 uint16_t pcie_lane; 61 }; 62 63 struct smu7_thermal_temperature_setting { 64 long temperature_low; 65 long temperature_high; 66 long temperature_shutdown; 67 }; 68 69 struct smu7_uvd_clocks { 70 uint32_t vclk; 71 uint32_t dclk; 72 }; 73 74 struct smu7_vce_clocks { 75 uint32_t evclk; 76 uint32_t ecclk; 77 }; 78 79 struct smu7_power_state { 80 uint32_t magic; 81 struct smu7_uvd_clocks uvd_clks; 82 struct smu7_vce_clocks vce_clks; 83 uint32_t sam_clk; 84 uint16_t performance_level_count; 85 bool dc_compatible; 86 uint32_t sclk_threshold; 87 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; 88 }; 89 90 struct smu7_dpm_level { 91 bool enabled; 92 uint32_t value; 93 uint32_t param1; 94 }; 95 96 #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5 97 #define MAX_REGULAR_DPM_NUMBER 8 98 #define SMU7_MINIMUM_ENGINE_CLOCK 2500 99 100 struct smu7_single_dpm_table { 101 uint32_t count; 102 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 103 }; 104 105 struct smu7_dpm_table { 106 struct smu7_single_dpm_table sclk_table; 107 struct smu7_single_dpm_table mclk_table; 108 struct smu7_single_dpm_table pcie_speed_table; 109 struct smu7_single_dpm_table vddc_table; 110 struct smu7_single_dpm_table vddci_table; 111 struct smu7_single_dpm_table mvdd_table; 112 }; 113 114 struct smu7_clock_registers { 115 uint32_t vCG_SPLL_FUNC_CNTL; 116 uint32_t vCG_SPLL_FUNC_CNTL_2; 117 uint32_t vCG_SPLL_FUNC_CNTL_3; 118 uint32_t vCG_SPLL_FUNC_CNTL_4; 119 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 120 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 121 uint32_t vDLL_CNTL; 122 uint32_t vMCLK_PWRMGT_CNTL; 123 uint32_t vMPLL_AD_FUNC_CNTL; 124 uint32_t vMPLL_DQ_FUNC_CNTL; 125 uint32_t vMPLL_FUNC_CNTL; 126 uint32_t vMPLL_FUNC_CNTL_1; 127 uint32_t vMPLL_FUNC_CNTL_2; 128 uint32_t vMPLL_SS1; 129 uint32_t vMPLL_SS2; 130 }; 131 132 #define DISABLE_MC_LOADMICROCODE 1 133 #define DISABLE_MC_CFGPROGRAMMING 2 134 135 struct smu7_voltage_smio_registers { 136 uint32_t vS0_VID_LOWER_SMIO_CNTL; 137 }; 138 139 #define SMU7_MAX_LEAKAGE_COUNT 8 140 141 struct smu7_leakage_voltage { 142 uint16_t count; 143 uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT]; 144 uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT]; 145 }; 146 147 struct smu7_vbios_boot_state { 148 uint16_t mvdd_bootup_value; 149 uint16_t vddc_bootup_value; 150 uint16_t vddci_bootup_value; 151 uint16_t vddgfx_bootup_value; 152 uint32_t sclk_bootup_value; 153 uint32_t mclk_bootup_value; 154 uint16_t pcie_gen_bootup_value; 155 uint16_t pcie_lane_bootup_value; 156 }; 157 158 struct smu7_display_timing { 159 uint32_t min_clock_in_sr; 160 uint32_t num_existing_displays; 161 uint32_t vrefresh; 162 }; 163 164 struct smu7_dpmlevel_enable_mask { 165 uint32_t uvd_dpm_enable_mask; 166 uint32_t vce_dpm_enable_mask; 167 uint32_t acp_dpm_enable_mask; 168 uint32_t samu_dpm_enable_mask; 169 uint32_t sclk_dpm_enable_mask; 170 uint32_t mclk_dpm_enable_mask; 171 uint32_t pcie_dpm_enable_mask; 172 }; 173 174 struct smu7_pcie_perf_range { 175 uint16_t max; 176 uint16_t min; 177 }; 178 179 struct smu7_odn_clock_voltage_dependency_table { 180 uint32_t count; 181 phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 182 }; 183 184 struct smu7_odn_dpm_table { 185 struct phm_odn_clock_levels odn_core_clock_dpm_levels; 186 struct phm_odn_clock_levels odn_memory_clock_dpm_levels; 187 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; 188 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; 189 uint32_t odn_mclk_min_limit; 190 uint32_t min_vddc; 191 uint32_t max_vddc; 192 }; 193 194 struct profile_mode_setting { 195 uint8_t bupdate_sclk; 196 uint8_t sclk_up_hyst; 197 uint8_t sclk_down_hyst; 198 uint16_t sclk_activity; 199 uint8_t bupdate_mclk; 200 uint8_t mclk_up_hyst; 201 uint8_t mclk_down_hyst; 202 uint16_t mclk_activity; 203 }; 204 205 struct smu7_hwmgr { 206 struct smu7_dpm_table dpm_table; 207 struct smu7_dpm_table golden_dpm_table; 208 struct smu7_odn_dpm_table odn_dpm_table; 209 210 uint32_t voting_rights_clients[8]; 211 uint32_t static_screen_threshold_unit; 212 uint32_t static_screen_threshold; 213 uint32_t voltage_control; 214 uint32_t vdd_gfx_control; 215 uint32_t vddc_vddgfx_delta; 216 uint32_t active_auto_throttle_sources; 217 218 struct smu7_clock_registers clock_registers; 219 220 bool is_memory_gddr5; 221 uint16_t acpi_vddc; 222 bool pspp_notify_required; 223 uint16_t force_pcie_gen; 224 uint16_t acpi_pcie_gen; 225 uint32_t pcie_gen_cap; 226 uint32_t pcie_lane_cap; 227 uint32_t pcie_spc_cap; 228 struct smu7_leakage_voltage vddc_leakage; 229 struct smu7_leakage_voltage vddci_leakage; 230 struct smu7_leakage_voltage vddcgfx_leakage; 231 232 uint32_t mvdd_control; 233 uint32_t vddc_mask_low; 234 uint32_t mvdd_mask_low; 235 uint16_t max_vddc_in_pptable; 236 uint16_t min_vddc_in_pptable; 237 uint16_t max_vddci_in_pptable; 238 uint16_t min_vddci_in_pptable; 239 bool is_uvd_enabled; 240 struct smu7_vbios_boot_state vbios_boot_state; 241 242 bool pcie_performance_request; 243 bool battery_state; 244 bool is_tlu_enabled; 245 bool disable_handshake; 246 bool smc_voltage_control_enabled; 247 bool vbi_time_out_support; 248 249 uint32_t soft_regs_start; 250 /* ---- Stuff originally coming from Evergreen ---- */ 251 uint32_t vddci_control; 252 struct pp_atomctrl_voltage_table vddc_voltage_table; 253 struct pp_atomctrl_voltage_table vddci_voltage_table; 254 struct pp_atomctrl_voltage_table mvdd_voltage_table; 255 struct pp_atomctrl_voltage_table vddgfx_voltage_table; 256 257 uint32_t mgcg_cgtt_local2; 258 uint32_t mgcg_cgtt_local3; 259 uint32_t gpio_debug; 260 uint32_t mc_micro_code_feature; 261 uint32_t highest_mclk; 262 uint16_t acpi_vddci; 263 uint8_t mvdd_high_index; 264 uint8_t mvdd_low_index; 265 bool dll_default_on; 266 bool performance_request_registered; 267 268 /* ---- Low Power Features ---- */ 269 bool ulv_supported; 270 271 /* ---- CAC Stuff ---- */ 272 uint32_t cac_table_start; 273 bool cac_configuration_required; 274 bool driver_calculate_cac_leakage; 275 bool cac_enabled; 276 277 /* ---- DPM2 Parameters ---- */ 278 uint32_t power_containment_features; 279 bool enable_dte_feature; 280 bool enable_tdc_limit_feature; 281 bool enable_pkg_pwr_tracking_feature; 282 bool disable_uvd_power_tune_feature; 283 284 285 uint32_t dte_tj_offset; 286 uint32_t fast_watermark_threshold; 287 288 /* ---- Phase Shedding ---- */ 289 uint8_t vddc_phase_shed_control; 290 291 /* ---- DI/DT ---- */ 292 struct smu7_display_timing display_timing; 293 294 /* ---- Thermal Temperature Setting ---- */ 295 struct smu7_thermal_temperature_setting thermal_temp_setting; 296 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; 297 uint32_t need_update_smu7_dpm_table; 298 uint32_t sclk_dpm_key_disabled; 299 uint32_t mclk_dpm_key_disabled; 300 uint32_t pcie_dpm_key_disabled; 301 uint32_t min_engine_clocks; 302 struct smu7_pcie_perf_range pcie_gen_performance; 303 struct smu7_pcie_perf_range pcie_lane_performance; 304 struct smu7_pcie_perf_range pcie_gen_power_saving; 305 struct smu7_pcie_perf_range pcie_lane_power_saving; 306 bool use_pcie_performance_levels; 307 bool use_pcie_power_saving_levels; 308 uint32_t mclk_dpm0_activity_target; 309 uint32_t low_sclk_interrupt_threshold; 310 uint32_t last_mclk_dpm_enable_mask; 311 bool uvd_enabled; 312 313 /* ---- Power Gating States ---- */ 314 bool uvd_power_gated; 315 bool vce_power_gated; 316 bool need_long_memory_training; 317 318 /* Application power optimization parameters */ 319 bool update_up_hyst; 320 bool update_down_hyst; 321 uint32_t down_hyst; 322 uint32_t up_hyst; 323 uint32_t disable_dpm_mask; 324 bool apply_optimized_settings; 325 326 uint32_t avfs_vdroop_override_setting; 327 bool apply_avfs_cks_off_voltage; 328 uint32_t frame_time_x2; 329 uint16_t mem_latency_high; 330 uint16_t mem_latency_low; 331 uint32_t vr_config; 332 struct profile_mode_setting current_profile_setting; 333 }; 334 335 /* To convert to Q8.8 format for firmware */ 336 #define SMU7_Q88_FORMAT_CONVERSION_UNIT 256 337 338 enum SMU7_I2CLineID { 339 SMU7_I2CLineID_DDC1 = 0x90, 340 SMU7_I2CLineID_DDC2 = 0x91, 341 SMU7_I2CLineID_DDC3 = 0x92, 342 SMU7_I2CLineID_DDC4 = 0x93, 343 SMU7_I2CLineID_DDC5 = 0x94, 344 SMU7_I2CLineID_DDC6 = 0x95, 345 SMU7_I2CLineID_SCLSDA = 0x96, 346 SMU7_I2CLineID_DDCVGA = 0x97 347 }; 348 349 #define SMU7_I2C_DDC1DATA 0 350 #define SMU7_I2C_DDC1CLK 1 351 #define SMU7_I2C_DDC2DATA 2 352 #define SMU7_I2C_DDC2CLK 3 353 #define SMU7_I2C_DDC3DATA 4 354 #define SMU7_I2C_DDC3CLK 5 355 #define SMU7_I2C_SDA 40 356 #define SMU7_I2C_SCL 41 357 #define SMU7_I2C_DDC4DATA 65 358 #define SMU7_I2C_DDC4CLK 66 359 #define SMU7_I2C_DDC5DATA 0x48 360 #define SMU7_I2C_DDC5CLK 0x49 361 #define SMU7_I2C_DDC6DATA 0x4a 362 #define SMU7_I2C_DDC6CLK 0x4b 363 #define SMU7_I2C_DDCVGADATA 0x4c 364 #define SMU7_I2C_DDCVGACLK 0x4d 365 366 #define SMU7_UNUSED_GPIO_PIN 0x7F 367 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 368 uint32_t clock_insr); 369 #endif 370 371
Indexes created Sat Sep 20 22:09:52 GMT 2025