| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_smu_v12_0.c | 383 uint32_t mclk_mask, soc_mask; local in function:smu_v12_0_get_dpm_ultimate_freq
388 &mclk_mask,
408 ret = smu_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
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| amdgpu_renoir_ppt.c | 549 uint32_t *mclk_mask,
557 if (mclk_mask)
558 *mclk_mask = 0;
564 if(mclk_mask)
565 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
726 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:renoir_set_performance_level
743 &mclk_mask,
748 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
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| amdgpu_navi10_ppt.c | 1420 uint32_t *mclk_mask,
1430 if (mclk_mask)
1431 *mclk_mask = 0;
1440 if(mclk_mask) {
1444 *mclk_mask = level_count - 1;
1768 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:navi10_set_performance_level
1787 &mclk_mask,
1792 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
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| amdgpu_smu_v11_0.c | 1911 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:smu_v11_0_set_performance_level
1929 &mclk_mask,
1934 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega12_hwmgr.c | 1588 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1596 *mclk_mask = 0;
1603 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1610 *mclk_mask = 0;
1613 *mclk_mask = mem_dpm_table->count - 1;
1643 uint32_t mclk_mask = 0; local in function:vega12_dpm_force_dpm_level
1660 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1664 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
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| amdgpu_vega20_hwmgr.c | 2484 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2492 *mclk_mask = 0;
2499 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2506 *mclk_mask = 0;
2509 *mclk_mask = mem_dpm_table->count - 1;
2683 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:vega20_dpm_force_dpm_level
2702 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2706 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
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| amdgpu_vega10_hwmgr.c | 4086 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4096 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4104 *mclk_mask = 0;
4114 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4206 uint32_t mclk_mask = 0; local in function:vega10_dpm_force_dpm_level
4210 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4226 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4230 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
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| amdgpu_smu7_hwmgr.c | 2735 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2753 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2756 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2798 *mclk_mask = 0;
2800 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2814 uint32_t mclk_mask = 0; local in function:smu7_force_dpm_level
2818 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2834 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2838 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
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