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    Searched defs:mclk_table (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega10_processpptables.c 614 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; local in function:get_mclk_voltage_dependency_table
623 mclk_table = kzalloc(table_size, GFP_KERNEL);
625 if (!mclk_table)
628 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
631 mclk_table->entries[i].vddInd =
633 mclk_table->entries[i].vddciInd =
635 mclk_table->entries[i].mvddInd =
637 mclk_table->entries[i].clk =
641 *pp_vega10_mclk_dep_table = mclk_table;
amdgpu_process_pptables_v1_0.c 379 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; local in function:get_mclk_voltage_dependency_table
389 mclk_table = kzalloc(table_size, GFP_KERNEL);
391 if (NULL == mclk_table)
394 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
399 entries, mclk_table, i);
410 *pp_tonga_mclk_dep_table = mclk_table;
amdgpu_smu10_hwmgr.c 841 struct smu10_voltage_dependency_table *mclk_table = local in function:smu10_force_clock_level
869 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
874 mclk_table->entries[low].clk/100);
878 mclk_table->entries[high].clk/100);
892 struct smu10_voltage_dependency_table *mclk_table = local in function:smu10_print_clock_levels
923 for (i = 0; i < mclk_table->count; i++)
926 mclk_table->entries[i].clk / 100,
927 ((mclk_table->entries[i].clk / 100)
amdgpu_vega20_hwmgr.c 1498 struct vega20_single_dpm_table *mclk_table = local in function:vega20_get_mclk_od
1502 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
smu7_hwmgr.h 107 struct smu7_single_dpm_table mclk_table; member in struct:smu7_dpm_table
amdgpu_vega10_hwmgr.c 674 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = local in function:vega10_patch_voltage_dependency_tables_with_lookup_table
701 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
702 voltage_id = mclk_table->entries[entry_id].vddInd;
703 mclk_table->entries[entry_id].vddc =
705 voltage_id = mclk_table->entries[entry_id].vddciInd;
706 mclk_table->entries[entry_id].vddci =
708 voltage_id = mclk_table->entries[entry_id].mvddInd;
709 mclk_table->entries[entry_id].mvdd =
3332 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); local in function:vega10_find_dpm_states_clocks_in_dpm_table
3349 for (i = 0; i < mclk_table->count; i++)
3972 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; local in function:vega10_notify_smc_display_config_after_ps_adjustment
4538 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); local in function:vega10_print_clock_levels
4876 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); local in function:vega10_get_mclk_od
    [all...]
amdgpu_smu7_hwmgr.c 647 &data->dpm_table.mclk_table,
715 data->dpm_table.mclk_table.count = 0;
717 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
719 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
721 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
722 data->dpm_table.mclk_table.count++;
810 data->dpm_table.mclk_table.count = 0
1862 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = local in function:smu7_patch_voltage_dependency_tables_with_lookup_table
1942 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; local in function:smu7_calc_voltage_dependency_tables
3609 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local in function:smu7_find_dpm_states_clocks_in_dpm_table
4455 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local in function:smu7_print_clock_levels
4620 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local in function:smu7_get_mclk_od
4703 struct phm_clock_voltage_dependency_table *mclk_table; local in function:smu7_get_mclks
4787 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); local in function:smu7_get_max_high_clocks
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
ci_dpm.h 72 struct ci_single_dpm_table mclk_table; member in struct:ci_dpm_table
radeon_ci_dpm.c 2562 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2565 pi->dpm_table.mclk_table.dpm_levels[j].value,
3342 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3343 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3346 dpm_table->mclk_table.dpm_levels[i].value,
3354 if ((dpm_table->mclk_table.count >= 2) &&
3364 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3366 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3368 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3473 &pi->dpm_table.mclk_table,
3868 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; local in function:ci_find_dpm_states_clocks_in_dpm_table
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