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      1 /*	$NetBSD: iomod.h,v 1.1 2014/02/24 07:23:43 skrll Exp $	*/
      2 
      3 /*	$OpenBSD: iomod.h,v 1.18 2007/10/20 16:41:45 miod Exp $	*/
      4 
      5 /*
      6  * Copyright (c) 2000-2004 Michael Shalayeff
      7  * All rights reserved.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
     22  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     23  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     24  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     26  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     27  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     28  * THE POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 /*
     31  * Copyright (c) 1990 mt Xinu, Inc.  All rights reserved.
     32  * Copyright (c) 1990,1991,1992,1994 University of Utah.  All rights reserved.
     33  *
     34  * Permission to use, copy, modify and distribute this software is hereby
     35  * granted provided that (1) source code retains these copyright, permission,
     36  * and disclaimer notices, and (2) redistributions including binaries
     37  * reproduce the notices in supporting documentation, and (3) all advertising
     38  * materials mentioning features or use of this software display the following
     39  * acknowledgement: ``This product includes software developed by the
     40  * Computer Systems Laboratory at the University of Utah.''
     41  *
     42  * Copyright (c) 1990 mt Xinu, Inc.
     43  * This file may be freely distributed in any form as long as
     44  * this copyright notice is included.
     45  * MTXINU, THE UNIVERSITY OF UTAH, AND CSL PROVIDE THIS SOFTWARE ``AS
     46  * IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
     47  * WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
     48  * FITNESS FOR A PARTICULAR PURPOSE.
     49  *
     50  * CSL requests users of this software to return to csl-dist (at) cs.utah.edu any
     51  * improvements that they make and grant CSL redistribution rights.
     52  *
     53  *	Utah $Hdr: iomod.h 1.6 94/12/14$
     54  */
     55 
     56 #ifndef	_MACHINE_IOMOD_H_
     57 #define	_MACHINE_IOMOD_H_
     58 
     59 #include <machine/pdc.h>
     60 
     61 /*
     62  * Structures and definitions for I/O Modules on HP-PA (9000/800).
     63  *
     64  * Memory layout:
     65  *
     66  *	0x00000000	+---------------------------------+
     67  *			|           Page Zero             |
     68  *	0x00000800	+ - - - - - - - - - - - - - - - - +
     69  *			|                                 |
     70  *			|                                 |
     71  *			|      Memory Address Space       |
     72  *			|                                 |
     73  *			|                                 |
     74  *	0xEF000000	+---------------------------------+
     75  *			|                                 |
     76  *			|        PDC Address Space        |
     77  *			|                                 |
     78  *	0xF1000000	+---------------------------------+
     79  *			|                                 |
     80  *			|                                 |
     81  *			|        I/O Address Space        |
     82  *			|                                 |
     83  *			|                                 |
     84  *	0xFFF80000	+ - - - - - - - - - - - - - - - - +
     85  *			|  Fixed Physical Address Space   |
     86  *	0xFFFC0000	+ - - - - - - - - - - - - - - - - +
     87  *			|  Local Broadcast Address Space  |
     88  *	0xFFFE0000	+ - - - - - - - - - - - - - - - - +
     89  *			| Global Broadcast Address Space  |
     90  *	0xFFFFFFFF	+---------------------------------+
     91  *
     92  * "Memory Address Space" is used by memory modules,
     93  *   "Page Zero" is described below.
     94  * "PDC Address Space" is used by Processor-Dependent Code.
     95  * "I/O Address Space" is used by I/O modules (and is not cached),
     96  *   "Fixed Physical" is used by modules on the central bus,
     97  *   "Local Broadcast" is used to reach all modules on the same bus, and
     98  *   "Global Broadcast" is used to reach all modules (thru bus converters).
     99  *
    100  * SPA space (see below) ranges from 0xF1000000 thru 0xFFFC0000.
    101  */
    102 
    103 #define	HPPA_IOBEGIN	0xF0000000
    104 #define	HPPA_IOLEN	0x10000000
    105 #define	PDC_ADDR	0xEF000000	/* explained above */
    106 #define	IO_ADDR		0xF1000000
    107 #define	SGC_SLOT1	0xF4000000	/* (hppa) */
    108 #define	SGC_SLOT2	0xF8000000	/* (hppa) */
    109 #define	SGC_SIZE	0x02000000	/* (hppa) */
    110 #define	FP_ADDR		0xFFF80000
    111 #define	LBCAST_ADDR	0xFFFC0000
    112 #define	GBCAST_ADDR	0xFFFE0000
    113 
    114 #define	PDC_LOW		PDC_ADDR	/* define some ranges */
    115 #define	PDC_HIGH	IO_ADDR
    116 #define	FPA_LOW		FP_ADDR
    117 #define	FPA_HIGH	LBCAST_ADDR
    118 #define	SPA_LOW		IO_ADDR
    119 #define	SPA_HIGH	LBCAST_ADDR
    120 #define	SGC_LOW		SGC_SLOT1
    121 #define	SGC_HIGH	(SGC_SLOT2+SGC_SIZE)
    122 
    123 #define	FPA_IOMOD	((FPA_HIGH-FPA_LOW)/sizeof(struct iomod))
    124 #define	MAXMODBUS	((int)(FPA_IOMOD))	/* maximum modules/bus */
    125 
    126 #define	HPPA_FLEX_COUNT	0x4000		/* number of "flex" blocks */
    127 #define	HPPA_FLEX_MASK	0xFFFC0000	/* (see below) */
    128 #define	HPPA_FLEX_SIZE	(~HPPA_FLEX_MASK + 1)
    129 #define	HPPA_FLEX(a)	(((a) & HPPA_FLEX_MASK) >> 18)
    130 
    131 /* size of HPA space for any device */
    132 #define	IOMOD_HPASIZE	0x1000
    133 
    134 /* offset to the device-specific registers,
    135  * basically sizeof(struct iomod) (see later)
    136  */
    137 #define	IOMOD_DEVOFFSET	0x800
    138 
    139 #if !defined(_LOCORE)
    140 
    141 /*
    142  * The first 2K of Soft Physical Address space on the Initial Memory Module
    143  * is aptly called "page zero".  The following structure defines the format
    144  * of page zero.  Individual members of this structure should be accessed
    145  * as "PAGE0->member".
    146  */
    147 
    148 #define	PAGE0	((struct pagezero *)0)	/* can't get any lower than this! */
    149 
    150 struct pagezero {
    151 	/* [0x000] Initialize Vectors */
    152 	int	ivec_special;		/* must be zero */
    153 	int	(*ivec_mempf)(void);	/* powerfail recovery software */
    154 	int	(*ivec_toc)(void);	/* exec'd after Transfer Of Control */
    155 	u_int	ivec_toclen;		/* bytes of ivec_toc code */
    156 	int	(*ivec_rendz)(void);	/* exec'd after Rendezvous Signal */
    157 	u_int	ivec_mempflen;		/* bytes of ivec_mempf code */
    158 	u_int	ivec_resv[2];		/* (reserved) */
    159 	u_int	ivec_mbz;		/* must be zero */
    160 	u_int	ivec_resv2[7];		/* (reserved) */
    161 
    162 	/* [0x040] Processor Dependent */
    163 	union	{
    164 		u_int	pd_Resv1[112];	/* (reserved) processor dependent */
    165 		struct	{		/* Viper-specific data */
    166 			u_int	v_Resv1[39];
    167 			u_int	v_Ctrlcpy;	/* copy of Viper `vi_control' */
    168 			u_int	v_Resv2[72];
    169 		} pd_Viper;
    170 	} pz_Pdep;
    171 
    172 	/* [0x200] IODC Data Area Descriptors
    173 		   use PDC_ALLOC to allocate these memory regions */
    174 	u_int	iodc_cons_base;		/* */
    175 	u_int	iodc_cons_size;		/* */
    176 	u_int	iodc_kbrd_base;		/* */
    177 	u_int	iodc_kbrd_size;		/* */
    178 	u_int	iodc_boot_base;		/* */
    179 	u_int	iodc_boot_size;		/* */
    180 
    181 	/* [0x218] */
    182 	u_int	resv1[0x41];
    183 
    184 	/* [0x31C] Capability Flags */
    185 	u_int	cap_flags;		/* system capabitlities */
    186 #define	HPPA_CAP_WIDESCSI	0x00000001
    187 
    188 	/* [0x320] Keyboard Extensions */
    189 	u_int	kbrd_ext[2];
    190 
    191 	/* [0x328] Boot Device Extensions */
    192 	u_int	boot_ext[2];
    193 
    194 	/* [0x330] Console/Display Extensions */
    195 	u_int	cons_ext[2];
    196 
    197 	/* [0x338] Initial Memory Module Extensions */
    198 	u_int	imm_ext[2];
    199 
    200 	/* [0x340] Memory Configuration */
    201 	u_int	memc_cont_l;		/* memc_cont low part */
    202 	u_int	memc_phsize_l;		/* memc_phsize low part */
    203 	u_int	memc_adsize_l;		/* memc_adsize low part */
    204 	u_int	memc_resv;		/* (reserved) */
    205 	u_int	memc_cont;		/* bytes of contiguous valid memory */
    206 	u_int	memc_phsize;		/* bytes of valid physical memory */
    207 	u_int	memc_adsize;		/* bytes of SPA space used by PDC */
    208 	u_int	memc_hpa_h;		/* HPA of CPU (high) */
    209 
    210 	/* [0x360] Miscellaneous */
    211 	struct boot_err mem_be[8];	/* boot errors (see above) */
    212 	u_int	mem_free;		/* first free phys. memory location */
    213 	u_int	mem_hpa;		/* HPA of CPU */
    214 	int	(*mem_pdc)(void);	/* PDC entry point */
    215 	u_int	mem_10msec;		/* # of Interval Timer ticks in 10msec*/
    216 
    217 	/* [0x390] Initial Memory Module */
    218 	struct iomod *imm_hpa;		/* HPA of Initial Memory module */
    219 	u_int	imm_soft_boot;		/* 0 == hard boot, 1 == soft boot */
    220 	u_int	imm_spa_size;		/* bytes of SPA in IMM */
    221 	u_int	imm_max_mem;		/* bytes of mem in IMM (<= spa_size) */
    222 
    223 	/* [0x3A0] Boot Console/Display, Device, and Keyboard */
    224 	struct pz_device mem_cons;	/* description of console device */
    225 	struct pz_device mem_boot;	/* description of boot device */
    226 	struct pz_device mem_kbd;	/* description of keyboard device */
    227 
    228 	/* [0x430] Reserved */
    229 	u_int	resv2[116];		/* (reserved) */
    230 
    231 	/* [0x600] Processor Dependent */
    232 	u_int	pd_resv2[128];		/* (reserved) processor dependent */
    233 };
    234 #define	v_ctrlcpy	pz_Pdep.pd_Viper.v_Ctrlcpy
    235 
    236 
    237 /*
    238  * Every module has 4K-bytes of address space associated with it.
    239  * A Hard Physical Address (HPA) can be broken down as follows.
    240  *
    241  * Since this is an I/O space, the high 4 bits are always 1's.
    242  *
    243  * The "flex" address specifies which bus a module is on; there are
    244  * 256K-bytes of HPA space for each bus, however only values from
    245  * 64 - 1022 are valid for the "flex" field (1022 designates the
    246  * central bus).  The "flex" addr is set at bus configuration time.
    247  *
    248  * The "fixed" address specifies a particular module on the same
    249  * bus (i.e. among modules with the same "flex" address).  This
    250  * value can also be found in "device_path.dp_mod" in "pdc.h".
    251  *
    252  * A modules HPA space consists of 2 pages; the "up" bit specifies
    253  * which of these pages is being addressed.  In general, the lower
    254  * page is privileged and the upper page it module-type dependent.
    255  *
    256  */
    257 
    258 struct hpa {
    259 	u_int	hpa_ones: 4,	/* must be 1's; this is an I/O space addr */
    260 		hpa_flex:10,	/* bus address for this module */
    261 		hpa_fixed:6,	/* location of module on bus */
    262 		hpa_up	: 1,	/* 1 == upper page, 0 == lower page */
    263 		hpa_set	: 5,	/* register set */
    264 		hpa_reg	: 4,	/* register number within a register set */
    265 		hpa_zeros:2;	/* must be 0's; addrs are word aligned */
    266 };
    267 
    268 
    269 /*
    270  * Certain modules require additional memory (i.e. more than that
    271  * provided by the HPA space).  A Soft Physical Address (SPA) can be
    272  * broken down as follows, on a module-type specific basis (either
    273  * Memory SPA or I/O SPA).
    274  *
    275  * SPA space must be a power of 2, and aligned accordingly.  The IODC
    276  * provides all information needed by software to configure SPA space
    277  * for a particular module.
    278  */
    279 
    280 struct memspa {
    281 	u_int	spa_page:21,	/* page of memory */
    282 		spa_off	:11;	/* offset into memory page */
    283 };
    284 
    285 struct iospa {
    286 	u_int	spa_ones: 4,	/* must be 1's; this is an I/O space addr */
    287 		spa_iopg:17,	/* page in I/O address space */
    288 		spa_set	: 5,	/* register set */
    289 		spa_reg	: 4,	/* register number within a register set */
    290 		spa_mode: 2;	/* aligned according to bus transaction mode */
    291 };
    292 
    293 
    294 /*
    295  * It is possible to send a command to all modules on a particular bus
    296  * (local broadcast), or all modules (global broadcast).  A Broadcast
    297  * Physical Address (BPA) can be broken down as follows.
    298  *
    299  * Read and Clear transactions are not allowed in BPA space.  All pages
    300  * in BPA space are privileged.
    301  */
    302 
    303 struct bpa {
    304 	u_int	bpa_ones:14,	/* must be 1's; this is in BPA space */
    305 		bpa_gbl	: 1,	/* 0 == local, 1 == global broadcast */
    306 		bpa_page: 6,	/* page in local/global BPA space */
    307 		bpa_set	: 5,	/* register set */
    308 		bpa_reg	: 4,	/* register number within a register set */
    309 		bpa_zeros:2;	/* must be 0's; addrs are word aligned */
    310 };
    311 
    312 
    313 /*
    314  * All I/O and Memory modules have 4K-bytes of HPA space associated with
    315  * it (described above), however not all modules implement every register.
    316  * The first 2K-bytes of registers are "privileged".
    317  *
    318  * (WO) == Write Only, (RO) == Read Only
    319  */
    320 
    321 struct iomod {
    322 /* SRS (Supervisor Register Set) */
    323 	u_int	io_eir;		/* (WO) interrupt CPU; set bits in EIR CR */
    324 	u_int	io_eim;		/* (WO) External Interrupt Message address */
    325 	u_int	io_dc_rw;	/* write address of IODC to read IODC data */
    326 	u_int	io_ii_rw;	/* read/clear external intrpt msg (bit-26) */
    327 	void *	io_dma_link;	/* pointer to "next quad" in DMA chain */
    328 	u_int	io_dma_command;	/* (RO) chain command to exec on "next quad" */
    329 	void *	io_dma_address;	/* (RO) start of DMA */
    330 	u_int	io_dma_count;	/* (RO) number of bytes remaining to xfer */
    331 	void *	io_flex;	/* (WO) HPA flex addr, LSB: bus master flag */
    332 	void *	io_spa;		/* (WO) SPA space; 0-20:addr, 24-31:iodc_spa */
    333 	u_int	resv1[2];	/* (reserved) */
    334 	u_int	io_command;	/* (WO) module commands (see below) */
    335 	u_int	io_status;	/* (RO) error returns (see below) */
    336 	u_int	io_control;	/* memory err logging (bit-9), bc forwarding */
    337 	u_int	io_test;	/* (RO) self-test information */
    338 /* ARS (Auxiliary Register Set) */
    339 	u_int	io_err_sadd;	/* (RO) slave bus error or memory error addr */
    340 	void *	chain_addr;	/* start address of chain RAM */
    341 	u_int	sub_mask_clr;	/* ignore intrpts on sub-channel (bitmask) */
    342 	u_int	sub_mask_set;	/* service intrpts on sub-channel (bitmask) */
    343 	u_int	diagnostic;	/* diagnostic use (reserved) */
    344 	u_int	resv2[2];	/* (reserved) */
    345 	void *	nmi_address;	/* address to send data to when NMI detected */
    346 	void *	nmi_data;	/* NMI data to be sent */
    347 	u_int	resv3[3];	/* (reserved) */
    348 	u_int	io_mem_low;	/* bottom of memory address range */
    349 	u_int	io_mem_high;	/* top of memory address range */
    350 	u_int	io_io_low;	/* bottom of I/O HPA address Range */
    351 	u_int	io_io_high;	/* top of I/O HPA address Range */
    352 
    353 	u_int	priv_trs[160];	/* TRSes (Type-dependent Reg Sets) */
    354 
    355 	u_int	priv_hvrs[320];	/* HVRSes (HVERSION-dependent Register Sets) */
    356 
    357 	u_int	hvrs[512];	/* HVRSes (HVERSION-dependent Register Sets) */
    358 };
    359 
    360 #define IOMOD_IO_IO_LOW(mod)	(((struct iomod *)(mod))->io_io_low)
    361 #define IOMOD_IO_IO_HIGH(mod)	(((struct iomod *)(mod))->io_io_high)
    362 
    363 #endif	/* !_LOCORE */
    364 
    365 /* primarily for a "reboot" and "_rtt" routines */
    366 #define	iomod_command	(4*12)
    367 
    368 /* io_flex */
    369 #define	DMA_ENABLE	0x1	/* flex register enable DMA bit */
    370 
    371 /* io_spa */
    372 #define	IOSPA(spa,iodc_data)	\
    373 	((volatile void *)		\
    374 	 (spa | iodc_data.iodc_spa_shift | iodc_data.iodc_spa_enb << 5 | \
    375 	  iodc_data.iodc_spa_pack << 6 | iodc_data.iodc_spa_io << 7))
    376 
    377 /* io_command */
    378 #define	CMD_STOP	0	/* halt any I/O, enable diagnostic access */
    379 #define	CMD_FLUSH	1	/* abort DMA */
    380 #define	CMD_CHAIN	2	/* initiate DMA */
    381 #define	CMD_CLEAR	3	/* clear errors */
    382 #define	CMD_RESET	5	/* reset any module */
    383 
    384 /* io_status */
    385 #define	IO_ERR_MEM_SL	0x10000	/* SPA space lost or corrupted */
    386 #define	IO_ERR_MEM_SE	0x00200	/* severity: minor */
    387 #define	IO_ERR_MEM_HE	0x00100	/* severity: affects invalid parts */
    388 #define	IO_ERR_MEM_FE	0x00080	/* severity: bad */
    389 #define	IO_ERR_MEM_RY	0x00040	/* IO_COMMAND register ready for command */
    390 #define	IO_ERR_DMA_DG	0x00010	/* module in diagnostic mode */
    391 #define	IO_ERR_DMA_PW	0x00004	/* Power Failing */
    392 #define	IO_ERR_DMA_PL	0x00002	/* Power Lost */
    393 #define	IO_ERR_VAL(x)	 (((x) >> 10) & 0x3f)
    394 #define	IO_ERR_DEPEND	 0	/* unspecified error */
    395 #define	IO_ERR_SPA	 1	/* (module-type specific) */
    396 #define	IO_ERR_INTERNAL	 2	/* (module-type specific) */
    397 #define	IO_ERR_MODE	 3	/* invalid mode or address space mapping */
    398 #define	IO_ERR_ERROR_M	 4	/* bus error (master detect) */
    399 #define	IO_ERR_DPARITY_S 5	/* data parity (slave detect) */
    400 #define	IO_ERR_PROTO_M	 6	/* protocol error (master detect) */
    401 #define	IO_ERR_ADDRESS	 7	/* no slave acknowledgement in transaction */
    402 #define	IO_ERR_MORE	 8	/* device transferred more data than expected */
    403 #define	IO_ERR_LESS	 9	/* device transferred less data than expected */
    404 #define	IO_ERR_SAPARITY	10	/* slave address phase parity */
    405 #define	IO_ERR_MAPARITY	11	/* master address phase parity */
    406 #define	IO_ERR_MDPARITY	12	/* mode phase parity */
    407 #define	IO_ERR_STPARITY	13	/* status phase parity */
    408 #define	IO_ERR_CMD	14	/* unimplemented I/O Command */
    409 #define	IO_ERR_BUS	15	/* generic bus error */
    410 #define	IO_ERR_CORR	24	/* correctable memory error */
    411 #define	IO_ERR_UNCORR	25	/* uncorrectable memory error */
    412 #define	IO_ERR_MAP	26	/* equivalent to IO_ERR_CORR */
    413 #define	IO_ERR_LINK	28	/* Bus Converter "link" (connection) error */
    414 #define	IO_ERR_CCMD	32	/* Illegal DMA command */
    415 #define	IO_ERR_ERROR_S	52	/* bus error (slave detect) */
    416 #define	IO_ERR_DPARITY_M 53	/* data parity (master detect) */
    417 #define	IO_ERR_PROTOCOL	54	/* protocol error (slave detect) */
    418 #define	IO_ERR_SELFTEST	58	/* (module-type specific) */
    419 #define	IO_ERR_BUSY	59	/* slave was busy too often or too long */
    420 #define	IO_ERR_RETRY	60	/* "busied" transaction not retried soon enough */
    421 #define	IO_ERR_ACCESS	61	/* illegal register access */
    422 #define	IO_ERR_IMPROP	62	/* "improper" data written */
    423 #define	IO_ERR_UNKNOWN	63
    424 
    425 /* io_control (memory) */
    426 #define	IO_CTL_MEMINIT	0x0	/* prevent some bus errors during memory init */
    427 #define	IO_CTL_MEMOKAY	0x100	/* enable all bus error logging */
    428 
    429 /* io_spa */
    430 #define	SPA_ENABLE	0x20	/* io_spa register enable spa bit */
    431 
    432 #define	EIM_GRPMASK	0x1F	/* EIM register group mask */
    433 #define	EIEM_MASK(eim)	(0x80000000 >> (eim & EIM_GRPMASK))
    434 #define	EIEM_BITCNT	32	/* number of bits in EIEM register */
    435 
    436 #endif	/* _MACHINE_IOMOD_H_ */
    437