1 /* $NetBSD: svga3d_surfacedefs.h,v 1.3 2021/12/18 23:45:45 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 4 /************************************************************************** 5 * 6 * Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 24 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 25 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 26 * USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 **************************************************************************/ 29 30 /* 31 * svga3d_surfacedefs.h -- 32 * 33 * Surface definitions and inlineable utilities for SVGA3d. 34 */ 35 36 #ifndef _SVGA3D_SURFACEDEFS_H_ 37 #define _SVGA3D_SURFACEDEFS_H_ 38 39 #define INCLUDE_ALLOW_USERLEVEL 40 #define INCLUDE_ALLOW_MODULE 41 #include "includeCheck.h" 42 43 #include <linux/kernel.h> 44 #include <drm/vmwgfx_drm.h> 45 46 #include "svga3d_reg.h" 47 48 #define surf_size_struct struct drm_vmw_size 49 50 /* 51 * enum svga3d_block_desc - describes generic properties about formats. 52 */ 53 enum svga3d_block_desc { 54 /* Nothing special can be said about this format. */ 55 SVGA3DBLOCKDESC_NONE = 0, 56 57 /* Format contains Blue/U data */ 58 SVGA3DBLOCKDESC_BLUE = 1 << 0, 59 SVGA3DBLOCKDESC_W = 1 << 0, 60 SVGA3DBLOCKDESC_BUMP_L = 1 << 0, 61 62 /* Format contains Green/V data */ 63 SVGA3DBLOCKDESC_GREEN = 1 << 1, 64 SVGA3DBLOCKDESC_V = 1 << 1, 65 66 /* Format contains Red/W/Luminance data */ 67 SVGA3DBLOCKDESC_RED = 1 << 2, 68 SVGA3DBLOCKDESC_U = 1 << 2, 69 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, 70 71 /* Format contains Alpha/Q data */ 72 SVGA3DBLOCKDESC_ALPHA = 1 << 3, 73 SVGA3DBLOCKDESC_Q = 1 << 3, 74 75 /* Format is a buffer */ 76 SVGA3DBLOCKDESC_BUFFER = 1 << 4, 77 78 /* Format is compressed */ 79 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, 80 81 /* Format uses IEEE floating point */ 82 SVGA3DBLOCKDESC_FP = 1 << 6, 83 84 /* Three separate blocks store data. */ 85 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7, 86 87 /* 2 planes of Y, UV, e.g., NV12. */ 88 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8, 89 90 /* 3 planes of separate Y, U, V, e.g., YV12. */ 91 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9, 92 93 /* Block with a stencil channel */ 94 SVGA3DBLOCKDESC_STENCIL = 1 << 11, 95 96 /* Typeless format */ 97 SVGA3DBLOCKDESC_TYPELESS = 1 << 12, 98 99 /* Channels are signed integers */ 100 SVGA3DBLOCKDESC_SINT = 1 << 13, 101 102 /* Channels are unsigned integers */ 103 SVGA3DBLOCKDESC_UINT = 1 << 14, 104 105 /* Channels are normalized (when sampling) */ 106 SVGA3DBLOCKDESC_NORM = 1 << 15, 107 108 /* Channels are in SRGB */ 109 SVGA3DBLOCKDESC_SRGB = 1 << 16, 110 111 /* Shared exponent */ 112 SVGA3DBLOCKDESC_EXP = 1 << 17, 113 114 /* Format contains color data. */ 115 SVGA3DBLOCKDESC_COLOR = 1 << 18, 116 /* Format contains depth data. */ 117 SVGA3DBLOCKDESC_DEPTH = 1 << 19, 118 /* Format contains bump data. */ 119 SVGA3DBLOCKDESC_BUMP = 1 << 20, 120 121 /* Format contains YUV video data. */ 122 SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21, 123 124 /* For mixed unsigned/signed formats. */ 125 SVGA3DBLOCKDESC_MIXED = 1 << 22, 126 127 /* For distingushing CxV8U8. */ 128 SVGA3DBLOCKDESC_CX = 1 << 23, 129 130 /* Different compressed format groups. */ 131 SVGA3DBLOCKDESC_BC1 = 1 << 24, 132 SVGA3DBLOCKDESC_BC2 = 1 << 25, 133 SVGA3DBLOCKDESC_BC3 = 1 << 26, 134 SVGA3DBLOCKDESC_BC4 = 1 << 27, 135 SVGA3DBLOCKDESC_BC5 = 1 << 28, 136 137 SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA | 138 SVGA3DBLOCKDESC_UINT | 139 SVGA3DBLOCKDESC_COLOR, 140 SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | 141 SVGA3DBLOCKDESC_NORM, 142 SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED | 143 SVGA3DBLOCKDESC_UINT | 144 SVGA3DBLOCKDESC_COLOR, 145 SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | 146 SVGA3DBLOCKDESC_NORM, 147 SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED | 148 SVGA3DBLOCKDESC_SINT | 149 SVGA3DBLOCKDESC_COLOR, 150 SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | 151 SVGA3DBLOCKDESC_NORM, 152 SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN | 153 SVGA3DBLOCKDESC_UINT | 154 SVGA3DBLOCKDESC_COLOR, 155 SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | 156 SVGA3DBLOCKDESC_GREEN | 157 SVGA3DBLOCKDESC_UINT | 158 SVGA3DBLOCKDESC_COLOR, 159 SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT | 160 SVGA3DBLOCKDESC_NORM, 161 SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | 162 SVGA3DBLOCKDESC_GREEN | 163 SVGA3DBLOCKDESC_SINT | 164 SVGA3DBLOCKDESC_COLOR, 165 SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT | 166 SVGA3DBLOCKDESC_NORM, 167 SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | 168 SVGA3DBLOCKDESC_GREEN | 169 SVGA3DBLOCKDESC_BLUE | 170 SVGA3DBLOCKDESC_UINT | 171 SVGA3DBLOCKDESC_COLOR, 172 SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | 173 SVGA3DBLOCKDESC_GREEN | 174 SVGA3DBLOCKDESC_BLUE | 175 SVGA3DBLOCKDESC_SINT | 176 SVGA3DBLOCKDESC_COLOR, 177 SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT | 178 SVGA3DBLOCKDESC_NORM, 179 SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM | 180 SVGA3DBLOCKDESC_SRGB, 181 SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED | 182 SVGA3DBLOCKDESC_GREEN | 183 SVGA3DBLOCKDESC_BLUE | 184 SVGA3DBLOCKDESC_ALPHA | 185 SVGA3DBLOCKDESC_UINT | 186 SVGA3DBLOCKDESC_COLOR, 187 SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT | 188 SVGA3DBLOCKDESC_NORM, 189 SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM | 190 SVGA3DBLOCKDESC_SRGB, 191 SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED | 192 SVGA3DBLOCKDESC_GREEN | 193 SVGA3DBLOCKDESC_BLUE | 194 SVGA3DBLOCKDESC_ALPHA | 195 SVGA3DBLOCKDESC_SINT | 196 SVGA3DBLOCKDESC_COLOR, 197 SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT | 198 SVGA3DBLOCKDESC_NORM, 199 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | 200 SVGA3DBLOCKDESC_GREEN | 201 SVGA3DBLOCKDESC_BLUE | 202 SVGA3DBLOCKDESC_ALPHA | 203 SVGA3DBLOCKDESC_FP | 204 SVGA3DBLOCKDESC_COLOR, 205 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U | 206 SVGA3DBLOCKDESC_V | 207 SVGA3DBLOCKDESC_BUMP, 208 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | 209 SVGA3DBLOCKDESC_BUMP_L | 210 SVGA3DBLOCKDESC_MIXED | 211 SVGA3DBLOCKDESC_BUMP, 212 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV | 213 SVGA3DBLOCKDESC_W | 214 SVGA3DBLOCKDESC_BUMP, 215 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | 216 SVGA3DBLOCKDESC_ALPHA | 217 SVGA3DBLOCKDESC_MIXED | 218 SVGA3DBLOCKDESC_BUMP, 219 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | 220 SVGA3DBLOCKDESC_V | 221 SVGA3DBLOCKDESC_W | 222 SVGA3DBLOCKDESC_Q | 223 SVGA3DBLOCKDESC_BUMP, 224 SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 225 SVGA3DBLOCKDESC_UINT | 226 SVGA3DBLOCKDESC_NORM | 227 SVGA3DBLOCKDESC_COLOR, 228 SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 229 SVGA3DBLOCKDESC_ALPHA | 230 SVGA3DBLOCKDESC_UINT | 231 SVGA3DBLOCKDESC_NORM | 232 SVGA3DBLOCKDESC_COLOR, 233 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | 234 SVGA3DBLOCKDESC_FP | 235 SVGA3DBLOCKDESC_COLOR, 236 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | 237 SVGA3DBLOCKDESC_GREEN | 238 SVGA3DBLOCKDESC_COLOR, 239 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | 240 SVGA3DBLOCKDESC_BLUE | 241 SVGA3DBLOCKDESC_COLOR, 242 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | 243 SVGA3DBLOCKDESC_COLOR, 244 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA | 245 SVGA3DBLOCKDESC_YUV_VIDEO | 246 SVGA3DBLOCKDESC_COLOR, 247 SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | 248 SVGA3DBLOCKDESC_GREEN | 249 SVGA3DBLOCKDESC_BLUE | 250 SVGA3DBLOCKDESC_EXP | 251 SVGA3DBLOCKDESC_COLOR, 252 253 SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED | 254 SVGA3DBLOCKDESC_TYPELESS, 255 SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED | 256 SVGA3DBLOCKDESC_UINT | 257 SVGA3DBLOCKDESC_NORM | 258 SVGA3DBLOCKDESC_COLOR, 259 SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED | 260 SVGA3DBLOCKDESC_SINT | 261 SVGA3DBLOCKDESC_NORM | 262 SVGA3DBLOCKDESC_COLOR, 263 SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM | 264 SVGA3DBLOCKDESC_SRGB, 265 SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 | 266 SVGA3DBLOCKDESC_COMP_TYPELESS, 267 SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 | 268 SVGA3DBLOCKDESC_COMP_UNORM, 269 SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM | 270 SVGA3DBLOCKDESC_SRGB, 271 SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 | 272 SVGA3DBLOCKDESC_COMP_TYPELESS, 273 SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 | 274 SVGA3DBLOCKDESC_COMP_UNORM, 275 SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM | 276 SVGA3DBLOCKDESC_SRGB, 277 SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 | 278 SVGA3DBLOCKDESC_COMP_TYPELESS, 279 SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 | 280 SVGA3DBLOCKDESC_COMP_UNORM, 281 SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM | 282 SVGA3DBLOCKDESC_SRGB, 283 SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 | 284 SVGA3DBLOCKDESC_COMP_TYPELESS, 285 SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 | 286 SVGA3DBLOCKDESC_COMP_UNORM, 287 SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 | 288 SVGA3DBLOCKDESC_COMP_SNORM, 289 SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 | 290 SVGA3DBLOCKDESC_COMP_TYPELESS, 291 SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 | 292 SVGA3DBLOCKDESC_COMP_UNORM, 293 SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 | 294 SVGA3DBLOCKDESC_COMP_SNORM, 295 296 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 297 SVGA3DBLOCKDESC_PLANAR_YUV | 298 SVGA3DBLOCKDESC_2PLANAR_YUV | 299 SVGA3DBLOCKDESC_COLOR, 300 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 301 SVGA3DBLOCKDESC_PLANAR_YUV | 302 SVGA3DBLOCKDESC_3PLANAR_YUV | 303 SVGA3DBLOCKDESC_COLOR, 304 305 SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH | 306 SVGA3DBLOCKDESC_UINT, 307 SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT | 308 SVGA3DBLOCKDESC_NORM, 309 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | 310 SVGA3DBLOCKDESC_STENCIL, 311 SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH | 312 SVGA3DBLOCKDESC_STENCIL | 313 SVGA3DBLOCKDESC_UINT, 314 SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT | 315 SVGA3DBLOCKDESC_NORM, 316 SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | 317 SVGA3DBLOCKDESC_FP, 318 319 SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | 320 SVGA3DBLOCKDESC_UINT, 321 SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV | 322 SVGA3DBLOCKDESC_SINT | 323 SVGA3DBLOCKDESC_NORM, 324 SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM | 325 SVGA3DBLOCKDESC_CX, 326 SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ | 327 SVGA3DBLOCKDESC_SINT | 328 SVGA3DBLOCKDESC_NORM, 329 }; 330 331 struct svga3d_channel_def { 332 union { 333 u8 blue; 334 u8 w_bump; 335 u8 l_bump; 336 u8 uv_video; 337 u8 u_video; 338 }; 339 union { 340 u8 green; 341 u8 stencil; 342 u8 v_bump; 343 u8 v_video; 344 }; 345 union { 346 u8 red; 347 u8 u_bump; 348 u8 luminance; 349 u8 y_video; 350 u8 depth; 351 u8 data; 352 }; 353 union { 354 u8 alpha; 355 u8 q_bump; 356 u8 exp; 357 }; 358 }; 359 360 /* 361 * struct svga3d_surface_desc - describes the actual pixel data. 362 * 363 * @format: Format 364 * @block_desc: Block description 365 * @block_size: Dimensions in pixels of a block 366 * @bytes_per_block: Size of block in bytes 367 * @pitch_bytes_per_block: Size of a block in bytes for purposes of pitch 368 * @bit_depth: Channel bit depths 369 * @bit_offset: Channel bit masks (in bits offset from the start of the pointer) 370 */ 371 struct svga3d_surface_desc { 372 SVGA3dSurfaceFormat format; 373 enum svga3d_block_desc block_desc; 374 375 surf_size_struct block_size; 376 u32 bytes_per_block; 377 u32 pitch_bytes_per_block; 378 379 struct svga3d_channel_def bit_depth; 380 struct svga3d_channel_def bit_offset; 381 }; 382 383 static const struct svga3d_surface_desc svga3d_surface_descs[] = { 384 {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE, 385 {1, 1, 1}, 0, 0, 386 {{0}, {0}, {0}, {0}}, 387 {{0}, {0}, {0}, {0}}}, 388 389 {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM, 390 {1, 1, 1}, 4, 4, 391 {{8}, {8}, {8}, {0}}, 392 {{0}, {8}, {16}, {24}}}, 393 394 {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM, 395 {1, 1, 1}, 4, 4, 396 {{8}, {8}, {8}, {8}}, 397 {{0}, {8}, {16}, {24}}}, 398 399 {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM, 400 {1, 1, 1}, 2, 2, 401 {{5}, {6}, {5}, {0}}, 402 {{0}, {5}, {11}, {0}}}, 403 404 {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM, 405 {1, 1, 1}, 2, 2, 406 {{5}, {5}, {5}, {0}}, 407 {{0}, {5}, {10}, {0}}}, 408 409 {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM, 410 {1, 1, 1}, 2, 2, 411 {{5}, {5}, {5}, {1}}, 412 {{0}, {5}, {10}, {15}}}, 413 414 {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM, 415 {1, 1, 1}, 2, 2, 416 {{4}, {4}, {4}, {4}}, 417 {{0}, {4}, {8}, {12}}}, 418 419 {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM, 420 {1, 1, 1}, 4, 4, 421 {{0}, {0}, {32}, {0}}, 422 {{0}, {0}, {0}, {0}}}, 423 424 {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM, 425 {1, 1, 1}, 2, 2, 426 {{0}, {0}, {16}, {0}}, 427 {{0}, {0}, {0}, {0}}}, 428 429 {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM, 430 {1, 1, 1}, 4, 4, 431 {{0}, {8}, {24}, {0}}, 432 {{0}, {0}, {8}, {0}}}, 433 434 {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM, 435 {1, 1, 1}, 2, 2, 436 {{0}, {1}, {15}, {0}}, 437 {{0}, {0}, {1}, {0}}}, 438 439 {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM, 440 {1, 1, 1}, 1, 1, 441 {{0}, {0}, {8}, {0}}, 442 {{0}, {0}, {0}, {0}}}, 443 444 {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM, 445 {1, 1, 1}, 1, 1, 446 {{0}, {0}, {4}, {4}}, 447 {{0}, {0}, {0}, {4}}}, 448 449 {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM, 450 {1, 1, 1}, 2, 2, 451 {{0}, {0}, {16}, {0}}, 452 {{0}, {0}, {0}, {0}}}, 453 454 {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM, 455 {1, 1, 1}, 2, 2, 456 {{0}, {0}, {8}, {8}}, 457 {{0}, {0}, {0}, {8}}}, 458 459 {SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 460 {4, 4, 1}, 8, 8, 461 {{0}, {0}, {64}, {0}}, 462 {{0}, {0}, {0}, {0}}}, 463 464 {SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 465 {4, 4, 1}, 16, 16, 466 {{0}, {0}, {128}, {0}}, 467 {{0}, {0}, {0}, {0}}}, 468 469 {SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 470 {4, 4, 1}, 16, 16, 471 {{0}, {0}, {128}, {0}}, 472 {{0}, {0}, {0}, {0}}}, 473 474 {SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 475 {4, 4, 1}, 16, 16, 476 {{0}, {0}, {128}, {0}}, 477 {{0}, {0}, {0}, {0}}}, 478 479 {SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 480 {4, 4, 1}, 16, 16, 481 {{0}, {0}, {128}, {0}}, 482 {{0}, {0}, {0}, {0}}}, 483 484 {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM, 485 {1, 1, 1}, 2, 2, 486 {{0}, {8}, {8}, {0}}, 487 {{0}, {8}, {0}, {0}}}, 488 489 {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL, 490 {1, 1, 1}, 2, 2, 491 {{6}, {5}, {5}, {0}}, 492 {{10}, {5}, {0}, {0}}}, 493 494 {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL, 495 {1, 1, 1}, 4, 4, 496 {{8}, {8}, {8}, {0}}, 497 {{16}, {8}, {0}, {0}}}, 498 499 {SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_UVL, 500 {1, 1, 1}, 3, 3, 501 {{8}, {8}, {8}, {0}}, 502 {{16}, {8}, {0}, {0}}}, 503 504 {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP, 505 {1, 1, 1}, 8, 8, 506 {{16}, {16}, {16}, {16}}, 507 {{32}, {16}, {0}, {48}}}, 508 509 {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP, 510 {1, 1, 1}, 16, 16, 511 {{32}, {32}, {32}, {32}}, 512 {{64}, {32}, {0}, {96}}}, 513 514 {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM, 515 {1, 1, 1}, 4, 4, 516 {{10}, {10}, {10}, {2}}, 517 {{0}, {10}, {20}, {30}}}, 518 519 {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM, 520 {1, 1, 1}, 2, 2, 521 {{0}, {8}, {8}, {0}}, 522 {{0}, {8}, {0}, {0}}}, 523 524 {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM, 525 {1, 1, 1}, 4, 4, 526 {{8}, {8}, {8}, {8}}, 527 {{16}, {8}, {0}, {24}}}, 528 529 {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM, 530 {1, 1, 1}, 2, 2, 531 {{0}, {8}, {8}, {0}}, 532 {{0}, {8}, {0}, {0}}}, 533 534 {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL, 535 {1, 1, 1}, 4, 4, 536 {{8}, {8}, {8}, {0}}, 537 {{16}, {8}, {0}, {0}}}, 538 539 {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA, 540 {1, 1, 1}, 4, 4, 541 {{10}, {10}, {10}, {2}}, 542 {{20}, {10}, {0}, {30}}}, 543 544 {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM, 545 {1, 1, 1}, 1, 1, 546 {{0}, {0}, {0}, {8}}, 547 {{0}, {0}, {0}, {0}}}, 548 549 {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP, 550 {1, 1, 1}, 2, 2, 551 {{0}, {0}, {16}, {0}}, 552 {{0}, {0}, {0}, {0}}}, 553 554 {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP, 555 {1, 1, 1}, 4, 4, 556 {{0}, {0}, {32}, {0}}, 557 {{0}, {0}, {0}, {0}}}, 558 559 {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP, 560 {1, 1, 1}, 4, 4, 561 {{0}, {16}, {16}, {0}}, 562 {{0}, {16}, {0}, {0}}}, 563 564 {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP, 565 {1, 1, 1}, 8, 8, 566 {{0}, {32}, {32}, {0}}, 567 {{0}, {32}, {0}, {0}}}, 568 569 {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER, 570 {1, 1, 1}, 1, 1, 571 {{0}, {0}, {8}, {0}}, 572 {{0}, {0}, {0}, {0}}}, 573 574 {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM, 575 {1, 1, 1}, 4, 4, 576 {{0}, {0}, {24}, {0}}, 577 {{0}, {0}, {8}, {0}}}, 578 579 {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM, 580 {1, 1, 1}, 4, 4, 581 {{0}, {16}, {16}, {0}}, 582 {{0}, {16}, {0}, {0}}}, 583 584 {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM, 585 {1, 1, 1}, 4, 4, 586 {{0}, {16}, {16}, {0}}, 587 {{0}, {16}, {0}, {0}}}, 588 589 {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM, 590 {1, 1, 1}, 8, 8, 591 {{16}, {16}, {16}, {16}}, 592 {{32}, {16}, {0}, {48}}}, 593 594 {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV, 595 {2, 1, 1}, 4, 4, 596 {{8}, {0}, {8}, {0}}, 597 {{0}, {0}, {8}, {0}}}, 598 599 {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV, 600 {2, 1, 1}, 4, 4, 601 {{8}, {0}, {8}, {0}}, 602 {{8}, {0}, {0}, {0}}}, 603 604 {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12, 605 {2, 2, 1}, 6, 2, 606 {{0}, {0}, {48}, {0}}, 607 {{0}, {0}, {0}, {0}}}, 608 609 {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV, 610 {1, 1, 1}, 4, 4, 611 {{8}, {8}, {8}, {8}}, 612 {{0}, {8}, {16}, {24}}}, 613 614 {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 615 {1, 1, 1}, 16, 16, 616 {{32}, {32}, {32}, {32}}, 617 {{64}, {32}, {0}, {96}}}, 618 619 {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 620 {1, 1, 1}, 16, 16, 621 {{32}, {32}, {32}, {32}}, 622 {{64}, {32}, {0}, {96}}}, 623 624 {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT, 625 {1, 1, 1}, 16, 16, 626 {{32}, {32}, {32}, {32}}, 627 {{64}, {32}, {0}, {96}}}, 628 629 {SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 630 {1, 1, 1}, 12, 12, 631 {{32}, {32}, {32}, {0}}, 632 {{64}, {32}, {0}, {0}}}, 633 634 {SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP, 635 {1, 1, 1}, 12, 12, 636 {{32}, {32}, {32}, {0}}, 637 {{64}, {32}, {0}, {0}}}, 638 639 {SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB_UINT, 640 {1, 1, 1}, 12, 12, 641 {{32}, {32}, {32}, {0}}, 642 {{64}, {32}, {0}, {0}}}, 643 644 {SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_RGB_SINT, 645 {1, 1, 1}, 12, 12, 646 {{32}, {32}, {32}, {0}}, 647 {{64}, {32}, {0}, {0}}}, 648 649 {SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 650 {1, 1, 1}, 8, 8, 651 {{16}, {16}, {16}, {16}}, 652 {{32}, {16}, {0}, {48}}}, 653 654 {SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 655 {1, 1, 1}, 8, 8, 656 {{16}, {16}, {16}, {16}}, 657 {{32}, {16}, {0}, {48}}}, 658 659 {SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM, 660 {1, 1, 1}, 8, 8, 661 {{16}, {16}, {16}, {16}}, 662 {{32}, {16}, {0}, {48}}}, 663 664 {SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_RGBA_SINT, 665 {1, 1, 1}, 8, 8, 666 {{16}, {16}, {16}, {16}}, 667 {{32}, {16}, {0}, {48}}}, 668 669 {SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 670 {1, 1, 1}, 8, 8, 671 {{0}, {32}, {32}, {0}}, 672 {{0}, {32}, {0}, {0}}}, 673 674 {SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG_UINT, 675 {1, 1, 1}, 8, 8, 676 {{0}, {32}, {32}, {0}}, 677 {{0}, {32}, {0}, {0}}}, 678 679 {SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_RG_SINT, 680 {1, 1, 1}, 8, 8, 681 {{0}, {32}, {32}, {0}}, 682 {{0}, {32}, {0}, {0}}}, 683 684 {SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 685 {1, 1, 1}, 8, 8, 686 {{0}, {8}, {32}, {0}}, 687 {{0}, {32}, {0}, {0}}}, 688 689 {SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS, 690 {1, 1, 1}, 8, 8, 691 {{0}, {8}, {32}, {0}}, 692 {{0}, {32}, {0}, {0}}}, 693 694 {SVGA3D_R32_FLOAT_X8X24, SVGA3DBLOCKDESC_R_FP, 695 {1, 1, 1}, 8, 8, 696 {{0}, {0}, {32}, {0}}, 697 {{0}, {0}, {0}, {0}}}, 698 699 {SVGA3D_X32_G8X24_UINT, SVGA3DBLOCKDESC_G_UINT, 700 {1, 1, 1}, 8, 8, 701 {{0}, {8}, {0}, {0}}, 702 {{0}, {32}, {0}, {0}}}, 703 704 {SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 705 {1, 1, 1}, 4, 4, 706 {{10}, {10}, {10}, {2}}, 707 {{20}, {10}, {0}, {30}}}, 708 709 {SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 710 {1, 1, 1}, 4, 4, 711 {{10}, {10}, {10}, {2}}, 712 {{20}, {10}, {0}, {30}}}, 713 714 {SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP, 715 {1, 1, 1}, 4, 4, 716 {{10}, {11}, {11}, {0}}, 717 {{22}, {11}, {0}, {0}}}, 718 719 {SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 720 {1, 1, 1}, 4, 4, 721 {{8}, {8}, {8}, {8}}, 722 {{16}, {8}, {0}, {24}}}, 723 724 {SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 725 {1, 1, 1}, 4, 4, 726 {{8}, {8}, {8}, {8}}, 727 {{16}, {8}, {0}, {24}}}, 728 729 {SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, 730 {1, 1, 1}, 4, 4, 731 {{8}, {8}, {8}, {8}}, 732 {{16}, {8}, {0}, {24}}}, 733 734 {SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 735 {1, 1, 1}, 4, 4, 736 {{8}, {8}, {8}, {8}}, 737 {{16}, {8}, {0}, {24}}}, 738 739 {SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA_SINT, 740 {1, 1, 1}, 4, 4, 741 {{8}, {8}, {8}, {8}}, 742 {{16}, {8}, {0}, {24}}}, 743 744 {SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 745 {1, 1, 1}, 4, 4, 746 {{0}, {16}, {16}, {0}}, 747 {{0}, {16}, {0}, {0}}}, 748 749 {SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_UINT, 750 {1, 1, 1}, 4, 4, 751 {{0}, {16}, {16}, {0}}, 752 {{0}, {16}, {0}, {0}}}, 753 754 {SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_RG_SINT, 755 {1, 1, 1}, 4, 4, 756 {{0}, {16}, {16}, {0}}, 757 {{0}, {16}, {0}, {0}}}, 758 759 {SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 760 {1, 1, 1}, 4, 4, 761 {{0}, {0}, {32}, {0}}, 762 {{0}, {0}, {0}, {0}}}, 763 764 {SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH_FP, 765 {1, 1, 1}, 4, 4, 766 {{0}, {0}, {32}, {0}}, 767 {{0}, {0}, {0}, {0}}}, 768 769 {SVGA3D_R32_UINT, SVGA3DBLOCKDESC_R_UINT, 770 {1, 1, 1}, 4, 4, 771 {{0}, {0}, {32}, {0}}, 772 {{0}, {0}, {0}, {0}}}, 773 774 {SVGA3D_R32_SINT, SVGA3DBLOCKDESC_R_SINT, 775 {1, 1, 1}, 4, 4, 776 {{0}, {0}, {32}, {0}}, 777 {{0}, {0}, {0}, {0}}}, 778 779 {SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 780 {1, 1, 1}, 4, 4, 781 {{0}, {8}, {24}, {0}}, 782 {{0}, {24}, {0}, {0}}}, 783 784 {SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS_UNORM, 785 {1, 1, 1}, 4, 4, 786 {{0}, {8}, {24}, {0}}, 787 {{0}, {24}, {0}, {0}}}, 788 789 {SVGA3D_R24_UNORM_X8, SVGA3DBLOCKDESC_R_UNORM, 790 {1, 1, 1}, 4, 4, 791 {{0}, {0}, {24}, {0}}, 792 {{0}, {0}, {0}, {0}}}, 793 794 {SVGA3D_X24_G8_UINT, SVGA3DBLOCKDESC_G_UINT, 795 {1, 1, 1}, 4, 4, 796 {{0}, {8}, {0}, {0}}, 797 {{0}, {24}, {0}, {0}}}, 798 799 {SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 800 {1, 1, 1}, 2, 2, 801 {{0}, {8}, {8}, {0}}, 802 {{0}, {8}, {0}, {0}}}, 803 804 {SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG_UNORM, 805 {1, 1, 1}, 2, 2, 806 {{0}, {8}, {8}, {0}}, 807 {{0}, {8}, {0}, {0}}}, 808 809 {SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG_UINT, 810 {1, 1, 1}, 2, 2, 811 {{0}, {8}, {8}, {0}}, 812 {{0}, {8}, {0}, {0}}}, 813 814 {SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_RG_SINT, 815 {1, 1, 1}, 2, 2, 816 {{0}, {8}, {8}, {0}}, 817 {{0}, {8}, {0}, {0}}}, 818 819 {SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 820 {1, 1, 1}, 2, 2, 821 {{0}, {0}, {16}, {0}}, 822 {{0}, {0}, {0}, {0}}}, 823 824 {SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_R_UNORM, 825 {1, 1, 1}, 2, 2, 826 {{0}, {0}, {16}, {0}}, 827 {{0}, {0}, {0}, {0}}}, 828 829 {SVGA3D_R16_UINT, SVGA3DBLOCKDESC_R_UINT, 830 {1, 1, 1}, 2, 2, 831 {{0}, {0}, {16}, {0}}, 832 {{0}, {0}, {0}, {0}}}, 833 834 {SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_R_SNORM, 835 {1, 1, 1}, 2, 2, 836 {{0}, {0}, {16}, {0}}, 837 {{0}, {0}, {0}, {0}}}, 838 839 {SVGA3D_R16_SINT, SVGA3DBLOCKDESC_R_SINT, 840 {1, 1, 1}, 2, 2, 841 {{0}, {0}, {16}, {0}}, 842 {{0}, {0}, {0}, {0}}}, 843 844 {SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 845 {1, 1, 1}, 1, 1, 846 {{0}, {0}, {8}, {0}}, 847 {{0}, {0}, {0}, {0}}}, 848 849 {SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_R_UNORM, 850 {1, 1, 1}, 1, 1, 851 {{0}, {0}, {8}, {0}}, 852 {{0}, {0}, {0}, {0}}}, 853 854 {SVGA3D_R8_UINT, SVGA3DBLOCKDESC_R_UINT, 855 {1, 1, 1}, 1, 1, 856 {{0}, {0}, {8}, {0}}, 857 {{0}, {0}, {0}, {0}}}, 858 859 {SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_R_SNORM, 860 {1, 1, 1}, 1, 1, 861 {{0}, {0}, {8}, {0}}, 862 {{0}, {0}, {0}, {0}}}, 863 864 {SVGA3D_R8_SINT, SVGA3DBLOCKDESC_R_SINT, 865 {1, 1, 1}, 1, 1, 866 {{0}, {0}, {8}, {0}}, 867 {{0}, {0}, {0}, {0}}}, 868 869 {SVGA3D_P8, SVGA3DBLOCKDESC_NONE, 870 {1, 1, 1}, 1, 1, 871 {{0}, {0}, {8}, {0}}, 872 {{0}, {0}, {0}, {0}}}, 873 874 {SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGB_EXP, 875 {1, 1, 1}, 4, 4, 876 {{9}, {9}, {9}, {5}}, 877 {{18}, {9}, {0}, {27}}}, 878 879 {SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_NONE, 880 {2, 1, 1}, 4, 4, 881 {{0}, {8}, {8}, {0}}, 882 {{0}, {0}, {8}, {0}}}, 883 884 {SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_NONE, 885 {2, 1, 1}, 4, 4, 886 {{0}, {8}, {8}, {0}}, 887 {{0}, {8}, {0}, {0}}}, 888 889 {SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_BC1_COMP_TYPELESS, 890 {4, 4, 1}, 8, 8, 891 {{0}, {0}, {64}, {0}}, 892 {{0}, {0}, {0}, {0}}}, 893 894 {SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB, 895 {4, 4, 1}, 8, 8, 896 {{0}, {0}, {64}, {0}}, 897 {{0}, {0}, {0}, {0}}}, 898 899 {SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_BC2_COMP_TYPELESS, 900 {4, 4, 1}, 16, 16, 901 {{0}, {0}, {128}, {0}}, 902 {{0}, {0}, {0}, {0}}}, 903 904 {SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB, 905 {4, 4, 1}, 16, 16, 906 {{0}, {0}, {128}, {0}}, 907 {{0}, {0}, {0}, {0}}}, 908 909 {SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_BC3_COMP_TYPELESS, 910 {4, 4, 1}, 16, 16, 911 {{0}, {0}, {128}, {0}}, 912 {{0}, {0}, {0}, {0}}}, 913 914 {SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB, 915 {4, 4, 1}, 16, 16, 916 {{0}, {0}, {128}, {0}}, 917 {{0}, {0}, {0}, {0}}}, 918 919 {SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_BC4_COMP_TYPELESS, 920 {4, 4, 1}, 8, 8, 921 {{0}, {0}, {64}, {0}}, 922 {{0}, {0}, {0}, {0}}}, 923 924 {SVGA3D_ATI1, SVGA3DBLOCKDESC_BC4_COMP_UNORM, 925 {4, 4, 1}, 8, 8, 926 {{0}, {0}, {64}, {0}}, 927 {{0}, {0}, {0}, {0}}}, 928 929 {SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_BC4_COMP_SNORM, 930 {4, 4, 1}, 8, 8, 931 {{0}, {0}, {64}, {0}}, 932 {{0}, {0}, {0}, {0}}}, 933 934 {SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_BC5_COMP_TYPELESS, 935 {4, 4, 1}, 16, 16, 936 {{0}, {0}, {128}, {0}}, 937 {{0}, {0}, {0}, {0}}}, 938 939 {SVGA3D_ATI2, SVGA3DBLOCKDESC_BC5_COMP_UNORM, 940 {4, 4, 1}, 16, 16, 941 {{0}, {0}, {128}, {0}}, 942 {{0}, {0}, {0}, {0}}}, 943 944 {SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_BC5_COMP_SNORM, 945 {4, 4, 1}, 16, 16, 946 {{0}, {0}, {128}, {0}}, 947 {{0}, {0}, {0}, {0}}}, 948 949 {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 950 {1, 1, 1}, 4, 4, 951 {{10}, {10}, {10}, {2}}, 952 {{20}, {10}, {0}, {30}}}, 953 954 {SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 955 {1, 1, 1}, 4, 4, 956 {{8}, {8}, {8}, {8}}, 957 {{0}, {8}, {16}, {24}}}, 958 959 {SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, 960 {1, 1, 1}, 4, 4, 961 {{8}, {8}, {8}, {8}}, 962 {{0}, {8}, {16}, {24}}}, 963 964 {SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 965 {1, 1, 1}, 4, 4, 966 {{8}, {8}, {8}, {0}}, 967 {{0}, {8}, {16}, {24}}}, 968 969 {SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_UNORM_SRGB, 970 {1, 1, 1}, 4, 4, 971 {{8}, {8}, {8}, {0}}, 972 {{0}, {8}, {16}, {24}}}, 973 974 {SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH_UNORM, 975 {1, 1, 1}, 2, 2, 976 {{0}, {0}, {16}, {0}}, 977 {{0}, {0}, {0}, {0}}}, 978 979 {SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH_UNORM, 980 {1, 1, 1}, 4, 4, 981 {{0}, {0}, {24}, {0}}, 982 {{0}, {0}, {8}, {0}}}, 983 984 {SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS_UNORM, 985 {1, 1, 1}, 4, 4, 986 {{0}, {8}, {24}, {0}}, 987 {{0}, {0}, {8}, {0}}}, 988 989 {SVGA3D_YV12, SVGA3DBLOCKDESC_YV12, 990 {2, 2, 1}, 6, 2, 991 {{0}, {0}, {48}, {0}}, 992 {{0}, {0}, {0}, {0}}}, 993 994 {SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, 995 {1, 1, 1}, 16, 16, 996 {{32}, {32}, {32}, {32}}, 997 {{64}, {32}, {0}, {96}}}, 998 999 {SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, 1000 {1, 1, 1}, 8, 8, 1001 {{16}, {16}, {16}, {16}}, 1002 {{32}, {16}, {0}, {48}}}, 1003 1004 {SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1005 {1, 1, 1}, 8, 8, 1006 {{16}, {16}, {16}, {16}}, 1007 {{32}, {16}, {0}, {48}}}, 1008 1009 {SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1010 {1, 1, 1}, 8, 8, 1011 {{0}, {32}, {32}, {0}}, 1012 {{0}, {32}, {0}, {0}}}, 1013 1014 {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1015 {1, 1, 1}, 4, 4, 1016 {{10}, {10}, {10}, {2}}, 1017 {{20}, {10}, {0}, {30}}}, 1018 1019 {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM, 1020 {1, 1, 1}, 4, 4, 1021 {{8}, {8}, {8}, {8}}, 1022 {{16}, {8}, {0}, {24}}}, 1023 1024 {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1025 {1, 1, 1}, 4, 4, 1026 {{0}, {16}, {16}, {0}}, 1027 {{0}, {16}, {0}, {0}}}, 1028 1029 {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM, 1030 {1, 1, 1}, 4, 4, 1031 {{0}, {16}, {16}, {0}}, 1032 {{0}, {16}, {0}, {0}}}, 1033 1034 {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM, 1035 {1, 1, 1}, 4, 4, 1036 {{0}, {16}, {16}, {0}}, 1037 {{0}, {16}, {0}, {0}}}, 1038 1039 {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP, 1040 {1, 1, 1}, 4, 4, 1041 {{0}, {0}, {32}, {0}}, 1042 {{0}, {0}, {0}, {0}}}, 1043 1044 {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM, 1045 {1, 1, 1}, 2, 2, 1046 {{0}, {8}, {8}, {0}}, 1047 {{0}, {8}, {0}, {0}}}, 1048 1049 {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP, 1050 {1, 1, 1}, 2, 2, 1051 {{0}, {0}, {16}, {0}}, 1052 {{0}, {0}, {0}, {0}}}, 1053 1054 {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM, 1055 {1, 1, 1}, 2, 2, 1056 {{0}, {0}, {16}, {0}}, 1057 {{0}, {0}, {0}, {0}}}, 1058 1059 {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM, 1060 {1, 1, 1}, 1, 1, 1061 {{0}, {0}, {0}, {8}}, 1062 {{0}, {0}, {0}, {0}}}, 1063 1064 {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 1065 {4, 4, 1}, 8, 8, 1066 {{0}, {0}, {64}, {0}}, 1067 {{0}, {0}, {0}, {0}}}, 1068 1069 {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 1070 {4, 4, 1}, 16, 16, 1071 {{0}, {0}, {128}, {0}}, 1072 {{0}, {0}, {0}, {0}}}, 1073 1074 {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 1075 {4, 4, 1}, 16, 16, 1076 {{0}, {0}, {128}, {0}}, 1077 {{0}, {0}, {0}, {0}}}, 1078 1079 {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1080 {1, 1, 1}, 2, 2, 1081 {{5}, {6}, {5}, {0}}, 1082 {{0}, {5}, {11}, {0}}}, 1083 1084 {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1085 {1, 1, 1}, 2, 2, 1086 {{5}, {5}, {5}, {1}}, 1087 {{0}, {5}, {10}, {15}}}, 1088 1089 {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1090 {1, 1, 1}, 4, 4, 1091 {{8}, {8}, {8}, {8}}, 1092 {{0}, {8}, {16}, {24}}}, 1093 1094 {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1095 {1, 1, 1}, 4, 4, 1096 {{8}, {8}, {8}, {0}}, 1097 {{0}, {8}, {16}, {24}}}, 1098 1099 {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM, 1100 {4, 4, 1}, 8, 8, 1101 {{0}, {0}, {64}, {0}}, 1102 {{0}, {0}, {0}, {0}}}, 1103 1104 {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM, 1105 {4, 4, 1}, 16, 16, 1106 {{0}, {0}, {128}, {0}}, 1107 {{0}, {0}, {0}, {0}}}, 1108 }; 1109 1110 static inline u32 clamped_umul32(u32 a, u32 b) 1111 { 1112 uint64_t tmp = (uint64_t) a*b; 1113 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; 1114 } 1115 1116 /** 1117 * svga3dsurface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the 1118 * given format. 1119 */ 1120 static inline const struct svga3d_surface_desc * 1121 svga3dsurface_get_desc(SVGA3dSurfaceFormat format) 1122 { 1123 if (format < ARRAY_SIZE(svga3d_surface_descs)) 1124 return &svga3d_surface_descs[format]; 1125 1126 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID]; 1127 } 1128 1129 /** 1130 * svga3dsurface_get_mip_size - Given a base level size and the mip level, 1131 * compute the size of the mip level. 1132 */ 1133 static inline surf_size_struct 1134 svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level) 1135 { 1136 surf_size_struct size; 1137 1138 size.width = max_t(u32, base_level.width >> mip_level, 1); 1139 size.height = max_t(u32, base_level.height >> mip_level, 1); 1140 size.depth = max_t(u32, base_level.depth >> mip_level, 1); 1141 size.pad64 = 0; 1142 1143 return size; 1144 } 1145 1146 static inline void 1147 svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc, 1148 const surf_size_struct *pixel_size, 1149 surf_size_struct *block_size) 1150 { 1151 block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width, 1152 desc->block_size.width); 1153 block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height, 1154 desc->block_size.height); 1155 block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth, 1156 desc->block_size.depth); 1157 } 1158 1159 static inline bool 1160 svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc) 1161 { 1162 return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0; 1163 } 1164 1165 static inline u32 1166 svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc, 1167 const surf_size_struct *size) 1168 { 1169 u32 pitch; 1170 surf_size_struct blocks; 1171 1172 svga3dsurface_get_size_in_blocks(desc, size, &blocks); 1173 1174 pitch = blocks.width * desc->pitch_bytes_per_block; 1175 1176 return pitch; 1177 } 1178 1179 /** 1180 * svga3dsurface_get_image_buffer_size - Calculates image buffer size. 1181 * 1182 * Return the number of bytes of buffer space required to store one image of a 1183 * surface, optionally using the specified pitch. 1184 * 1185 * If pitch is zero, it is assumed that rows are tightly packed. 1186 * 1187 * This function is overflow-safe. If the result would have overflowed, instead 1188 * we return MAX_UINT32. 1189 */ 1190 static inline u32 1191 svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc, 1192 const surf_size_struct *size, 1193 u32 pitch) 1194 { 1195 surf_size_struct image_blocks; 1196 u32 slice_size, total_size; 1197 1198 svga3dsurface_get_size_in_blocks(desc, size, &image_blocks); 1199 1200 if (svga3dsurface_is_planar_surface(desc)) { 1201 total_size = clamped_umul32(image_blocks.width, 1202 image_blocks.height); 1203 total_size = clamped_umul32(total_size, image_blocks.depth); 1204 total_size = clamped_umul32(total_size, desc->bytes_per_block); 1205 return total_size; 1206 } 1207 1208 if (pitch == 0) 1209 pitch = svga3dsurface_calculate_pitch(desc, size); 1210 1211 slice_size = clamped_umul32(image_blocks.height, pitch); 1212 total_size = clamped_umul32(slice_size, image_blocks.depth); 1213 1214 return total_size; 1215 } 1216 1217 /** 1218 * svga3dsurface_get_serialized_size - Get the serialized size for the image. 1219 */ 1220 static inline u32 1221 svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, 1222 surf_size_struct base_level_size, 1223 u32 num_mip_levels, 1224 u32 num_layers) 1225 { 1226 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1227 u32 total_size = 0; 1228 u32 mip; 1229 1230 for (mip = 0; mip < num_mip_levels; mip++) { 1231 surf_size_struct size = 1232 svga3dsurface_get_mip_size(base_level_size, mip); 1233 total_size += svga3dsurface_get_image_buffer_size(desc, 1234 &size, 0); 1235 } 1236 1237 return total_size * num_layers; 1238 } 1239 1240 /** 1241 * svga3dsurface_get_serialized_size_extended - Returns the number of bytes 1242 * required for a surface with given parameters. Support for sample count. 1243 */ 1244 static inline u32 1245 svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format, 1246 surf_size_struct base_level_size, 1247 u32 num_mip_levels, 1248 u32 num_layers, 1249 u32 num_samples) 1250 { 1251 uint64_t total_size = 1252 svga3dsurface_get_serialized_size(format, 1253 base_level_size, 1254 num_mip_levels, 1255 num_layers); 1256 total_size *= max_t(u32, 1, num_samples); 1257 1258 return min_t(uint64_t, total_size, (uint64_t)U32_MAX); 1259 } 1260 1261 /** 1262 * svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel 1263 * in an image (or volume). 1264 * 1265 * @width: The image width in pixels. 1266 * @height: The image height in pixels 1267 */ 1268 static inline u32 1269 svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format, 1270 u32 width, u32 height, 1271 u32 x, u32 y, u32 z) 1272 { 1273 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1274 const u32 bw = desc->block_size.width, bh = desc->block_size.height; 1275 const u32 bd = desc->block_size.depth; 1276 const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) * 1277 desc->bytes_per_block; 1278 const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride; 1279 const u32 offset = (z / bd * imgstride + 1280 y / bh * rowstride + 1281 x / bw * desc->bytes_per_block); 1282 return offset; 1283 } 1284 1285 static inline u32 1286 svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format, 1287 surf_size_struct baseLevelSize, 1288 u32 numMipLevels, 1289 u32 face, 1290 u32 mip) 1291 1292 { 1293 u32 offset; 1294 u32 mipChainBytes; 1295 u32 mipChainBytesToLevel; 1296 u32 i; 1297 const struct svga3d_surface_desc *desc; 1298 surf_size_struct mipSize; 1299 u32 bytes; 1300 1301 desc = svga3dsurface_get_desc(format); 1302 1303 mipChainBytes = 0; 1304 mipChainBytesToLevel = 0; 1305 for (i = 0; i < numMipLevels; i++) { 1306 mipSize = svga3dsurface_get_mip_size(baseLevelSize, i); 1307 bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0); 1308 mipChainBytes += bytes; 1309 if (i < mip) 1310 mipChainBytesToLevel += bytes; 1311 } 1312 1313 offset = mipChainBytes * face + mipChainBytesToLevel; 1314 1315 return offset; 1316 } 1317 1318 1319 /** 1320 * svga3dsurface_is_gb_screen_target_format - Is the specified format usable as 1321 * a ScreenTarget? 1322 * (with just the GBObjects cap-bit 1323 * set) 1324 * @format: format to queried 1325 * 1326 * RETURNS: 1327 * true if queried format is valid for screen targets 1328 */ 1329 static inline bool 1330 svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format) 1331 { 1332 return (format == SVGA3D_X8R8G8B8 || 1333 format == SVGA3D_A8R8G8B8 || 1334 format == SVGA3D_R5G6B5 || 1335 format == SVGA3D_X1R5G5B5 || 1336 format == SVGA3D_A1R5G5B5 || 1337 format == SVGA3D_P8); 1338 } 1339 1340 1341 /** 1342 * svga3dsurface_is_dx_screen_target_format - Is the specified format usable as 1343 * a ScreenTarget? 1344 * (with DX10 enabled) 1345 * 1346 * @format: format to queried 1347 * 1348 * Results: 1349 * true if queried format is valid for screen targets 1350 */ 1351 static inline bool 1352 svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format) 1353 { 1354 return (format == SVGA3D_R8G8B8A8_UNORM || 1355 format == SVGA3D_B8G8R8A8_UNORM || 1356 format == SVGA3D_B8G8R8X8_UNORM); 1357 } 1358 1359 1360 /** 1361 * svga3dsurface_is_screen_target_format - Is the specified format usable as a 1362 * ScreenTarget? 1363 * (for some combination of caps) 1364 * 1365 * @format: format to queried 1366 * 1367 * Results: 1368 * true if queried format is valid for screen targets 1369 */ 1370 static inline bool 1371 svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format) 1372 { 1373 if (svga3dsurface_is_gb_screen_target_format(format)) { 1374 return true; 1375 } 1376 return svga3dsurface_is_dx_screen_target_format(format); 1377 } 1378 1379 /** 1380 * struct svga3dsurface_mip - Mimpmap level information 1381 * @bytes: Bytes required in the backing store of this mipmap level. 1382 * @img_stride: Byte stride per image. 1383 * @row_stride: Byte stride per block row. 1384 * @size: The size of the mipmap. 1385 */ 1386 struct svga3dsurface_mip { 1387 size_t bytes; 1388 size_t img_stride; 1389 size_t row_stride; 1390 struct drm_vmw_size size; 1391 1392 }; 1393 1394 /** 1395 * struct svga3dsurface_cache - Cached surface information 1396 * @desc: Pointer to the surface descriptor 1397 * @mip: Array of mipmap level information. Valid size is @num_mip_levels. 1398 * @mip_chain_bytes: Bytes required in the backing store for the whole chain 1399 * of mip levels. 1400 * @sheet_bytes: Bytes required in the backing store for a sheet 1401 * representing a single sample. 1402 * @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in 1403 * a chain. 1404 * @num_layers: Number of slices in an array texture or number of faces in 1405 * a cubemap texture. 1406 */ 1407 struct svga3dsurface_cache { 1408 const struct svga3d_surface_desc *desc; 1409 struct svga3dsurface_mip mip[DRM_VMW_MAX_MIP_LEVELS]; 1410 size_t mip_chain_bytes; 1411 size_t sheet_bytes; 1412 u32 num_mip_levels; 1413 u32 num_layers; 1414 }; 1415 1416 /** 1417 * struct svga3dsurface_loc - Surface location 1418 * @sub_resource: Surface subresource. Defined as layer * num_mip_levels + 1419 * mip_level. 1420 * @x: X coordinate. 1421 * @y: Y coordinate. 1422 * @z: Z coordinate. 1423 */ 1424 struct svga3dsurface_loc { 1425 u32 sub_resource; 1426 u32 x, y, z; 1427 }; 1428 1429 /** 1430 * svga3dsurface_subres - Compute the subresource from layer and mipmap. 1431 * @cache: Surface layout data. 1432 * @mip_level: The mipmap level. 1433 * @layer: The surface layer (face or array slice). 1434 * 1435 * Return: The subresource. 1436 */ 1437 static inline u32 svga3dsurface_subres(const struct svga3dsurface_cache *cache, 1438 u32 mip_level, u32 layer) 1439 { 1440 return cache->num_mip_levels * layer + mip_level; 1441 } 1442 1443 /** 1444 * svga3dsurface_setup_cache - Build a surface cache entry 1445 * @size: The surface base level dimensions. 1446 * @format: The surface format. 1447 * @num_mip_levels: Number of mipmap levels. 1448 * @num_layers: Number of layers. 1449 * @cache: Pointer to a struct svga3dsurface_cach object to be filled in. 1450 * 1451 * Return: Zero on success, -EINVAL on invalid surface layout. 1452 */ 1453 static inline int svga3dsurface_setup_cache(const struct drm_vmw_size *size, 1454 SVGA3dSurfaceFormat format, 1455 u32 num_mip_levels, 1456 u32 num_layers, 1457 u32 num_samples, 1458 struct svga3dsurface_cache *cache) 1459 { 1460 const struct svga3d_surface_desc *desc; 1461 u32 i; 1462 1463 memset(cache, 0, sizeof(*cache)); 1464 cache->desc = desc = svga3dsurface_get_desc(format); 1465 cache->num_mip_levels = num_mip_levels; 1466 cache->num_layers = num_layers; 1467 for (i = 0; i < cache->num_mip_levels; i++) { 1468 struct svga3dsurface_mip *mip = &cache->mip[i]; 1469 1470 mip->size = svga3dsurface_get_mip_size(*size, i); 1471 mip->bytes = svga3dsurface_get_image_buffer_size 1472 (desc, &mip->size, 0); 1473 mip->row_stride = 1474 __KERNEL_DIV_ROUND_UP(mip->size.width, 1475 desc->block_size.width) * 1476 desc->bytes_per_block * num_samples; 1477 if (!mip->row_stride) 1478 goto invalid_dim; 1479 1480 mip->img_stride = 1481 __KERNEL_DIV_ROUND_UP(mip->size.height, 1482 desc->block_size.height) * 1483 mip->row_stride; 1484 if (!mip->img_stride) 1485 goto invalid_dim; 1486 1487 cache->mip_chain_bytes += mip->bytes; 1488 } 1489 cache->sheet_bytes = cache->mip_chain_bytes * num_layers; 1490 if (!cache->sheet_bytes) 1491 goto invalid_dim; 1492 1493 return 0; 1494 1495 invalid_dim: 1496 VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n"); 1497 return -EINVAL; 1498 } 1499 1500 /** 1501 * svga3dsurface_get_loc - Get a surface location from an offset into the 1502 * backing store 1503 * @cache: Surface layout data. 1504 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1505 * @offset: Offset into the surface backing store. 1506 */ 1507 static inline void 1508 svga3dsurface_get_loc(const struct svga3dsurface_cache *cache, 1509 struct svga3dsurface_loc *loc, 1510 size_t offset) 1511 { 1512 const struct svga3dsurface_mip *mip = &cache->mip[0]; 1513 const struct svga3d_surface_desc *desc = cache->desc; 1514 u32 layer; 1515 int i; 1516 1517 if (offset >= cache->sheet_bytes) 1518 offset %= cache->sheet_bytes; 1519 1520 layer = offset / cache->mip_chain_bytes; 1521 offset -= layer * cache->mip_chain_bytes; 1522 for (i = 0; i < cache->num_mip_levels; ++i, ++mip) { 1523 if (mip->bytes > offset) 1524 break; 1525 offset -= mip->bytes; 1526 } 1527 1528 loc->sub_resource = svga3dsurface_subres(cache, i, layer); 1529 loc->z = offset / mip->img_stride; 1530 offset -= loc->z * mip->img_stride; 1531 loc->z *= desc->block_size.depth; 1532 loc->y = offset / mip->row_stride; 1533 offset -= loc->y * mip->row_stride; 1534 loc->y *= desc->block_size.height; 1535 loc->x = offset / desc->bytes_per_block; 1536 loc->x *= desc->block_size.width; 1537 } 1538 1539 /** 1540 * svga3dsurface_inc_loc - Clamp increment a surface location with one block 1541 * size 1542 * in each dimension. 1543 * @loc: Pointer to a struct svga3dsurface_loc to be incremented. 1544 * 1545 * When computing the size of a range as size = end - start, the range does not 1546 * include the end element. However a location representing the last byte 1547 * of a touched region in the backing store *is* included in the range. 1548 * This function modifies such a location to match the end definition 1549 * given as start + size which is the one used in a SVGA3dBox. 1550 */ 1551 static inline void 1552 svga3dsurface_inc_loc(const struct svga3dsurface_cache *cache, 1553 struct svga3dsurface_loc *loc) 1554 { 1555 const struct svga3d_surface_desc *desc = cache->desc; 1556 u32 mip = loc->sub_resource % cache->num_mip_levels; 1557 const struct drm_vmw_size *size = &cache->mip[mip].size; 1558 1559 loc->sub_resource++; 1560 loc->x += desc->block_size.width; 1561 if (loc->x > size->width) 1562 loc->x = size->width; 1563 loc->y += desc->block_size.height; 1564 if (loc->y > size->height) 1565 loc->y = size->height; 1566 loc->z += desc->block_size.depth; 1567 if (loc->z > size->depth) 1568 loc->z = size->depth; 1569 } 1570 1571 /** 1572 * svga3dsurface_min_loc - The start location in a subresource 1573 * @cache: Surface layout data. 1574 * @sub_resource: The subresource. 1575 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1576 */ 1577 static inline void 1578 svga3dsurface_min_loc(const struct svga3dsurface_cache *cache, 1579 u32 sub_resource, 1580 struct svga3dsurface_loc *loc) 1581 { 1582 loc->sub_resource = sub_resource; 1583 loc->x = loc->y = loc->z = 0; 1584 } 1585 1586 /** 1587 * svga3dsurface_min_loc - The end location in a subresource 1588 * @cache: Surface layout data. 1589 * @sub_resource: The subresource. 1590 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1591 * 1592 * Following the end definition given in svga3dsurface_inc_loc(), 1593 * Compute the end location of a surface subresource. 1594 */ 1595 static inline void 1596 svga3dsurface_max_loc(const struct svga3dsurface_cache *cache, 1597 u32 sub_resource, 1598 struct svga3dsurface_loc *loc) 1599 { 1600 const struct drm_vmw_size *size; 1601 u32 mip; 1602 1603 loc->sub_resource = sub_resource + 1; 1604 mip = sub_resource % cache->num_mip_levels; 1605 size = &cache->mip[mip].size; 1606 loc->x = size->width; 1607 loc->y = size->height; 1608 loc->z = size->depth; 1609 } 1610 1611 #endif /* _SVGA3D_SURFACEDEFS_H_ */ 1612
Indexes created Mon Sep 22 05:09:51 GMT 2025