1 /* $NetBSD: nbio_6_1_offset.h,v 1.2 2021/12/18 23:45:18 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _nbio_6_1_OFFSET_HEADER 24 #define _nbio_6_1_OFFSET_HEADER 25 26 27 28 // addressBlock: nbio_pcie_pswuscfg0_cfgdecp 29 // base address: 0x0 30 #define cfgPSWUSCFG0_VENDOR_ID 0x0000 31 #define cfgPSWUSCFG0_DEVICE_ID 0x0002 32 #define cfgPSWUSCFG0_COMMAND 0x0004 33 #define cfgPSWUSCFG0_STATUS 0x0006 34 #define cfgPSWUSCFG0_REVISION_ID 0x0008 35 #define cfgPSWUSCFG0_PROG_INTERFACE 0x0009 36 #define cfgPSWUSCFG0_SUB_CLASS 0x000a 37 #define cfgPSWUSCFG0_BASE_CLASS 0x000b 38 #define cfgPSWUSCFG0_CACHE_LINE 0x000c 39 #define cfgPSWUSCFG0_LATENCY 0x000d 40 #define cfgPSWUSCFG0_HEADER 0x000e 41 #define cfgPSWUSCFG0_BIST 0x000f 42 #define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018 43 #define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c 44 #define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e 45 #define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020 46 #define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024 47 #define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028 48 #define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c 49 #define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030 50 #define cfgPSWUSCFG0_CAP_PTR 0x0034 51 #define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c 52 #define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d 53 #define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e 54 #define cfgEXT_BRIDGE_CNTL 0x0040 55 #define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048 56 #define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c 57 #define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050 58 #define cfgPSWUSCFG0_PMI_CAP 0x0052 59 #define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054 60 #define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058 61 #define cfgPSWUSCFG0_PCIE_CAP 0x005a 62 #define cfgPSWUSCFG0_DEVICE_CAP 0x005c 63 #define cfgPSWUSCFG0_DEVICE_CNTL 0x0060 64 #define cfgPSWUSCFG0_DEVICE_STATUS 0x0062 65 #define cfgPSWUSCFG0_LINK_CAP 0x0064 66 #define cfgPSWUSCFG0_LINK_CNTL 0x0068 67 #define cfgPSWUSCFG0_LINK_STATUS 0x006a 68 #define cfgPSWUSCFG0_DEVICE_CAP2 0x007c 69 #define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080 70 #define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082 71 #define cfgPSWUSCFG0_LINK_CAP2 0x0084 72 #define cfgPSWUSCFG0_LINK_CNTL2 0x0088 73 #define cfgPSWUSCFG0_LINK_STATUS2 0x008a 74 #define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0 75 #define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2 76 #define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4 77 #define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8 78 #define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8 79 #define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac 80 #define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0 81 #define cfgPSWUSCFG0_SSID_CAP 0x00c4 82 #define cfgMSI_MAP_CAP_LIST 0x00c8 83 #define cfgMSI_MAP_CAP 0x00ca 84 #define cfgMSI_MAP_ADDR_LO 0x00cc 85 #define cfgMSI_MAP_ADDR_HI 0x00d0 86 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 87 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 88 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108 89 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c 90 #define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110 91 #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114 92 #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118 93 #define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c 94 #define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e 95 #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120 96 #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124 97 #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a 98 #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c 99 #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130 100 #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136 101 #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 102 #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 103 #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 104 #define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 105 #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154 106 #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158 107 #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c 108 #define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160 109 #define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164 110 #define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168 111 #define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c 112 #define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170 113 #define cfgPSWUSCFG0_PCIE_HDR_LOG2 0x0174 114 #define cfgPSWUSCFG0_PCIE_HDR_LOG3 0x0178 115 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 0x0188 116 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 0x018c 117 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 0x0190 118 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 0x0194 119 #define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 120 #define cfgPSWUSCFG0_PCIE_LINK_CNTL3 0x0274 121 #define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 0x0278 122 #define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 123 #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 124 #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 125 #define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 126 #define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 127 #define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 128 #define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 129 #define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 130 #define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 131 #define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 132 #define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 133 #define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 134 #define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 135 #define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 136 #define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 137 #define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 138 #define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 0x02a0 139 #define cfgPSWUSCFG0_PCIE_ACS_CAP 0x02a4 140 #define cfgPSWUSCFG0_PCIE_ACS_CNTL 0x02a6 141 #define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 0x02f0 142 #define cfgPSWUSCFG0_PCIE_MC_CAP 0x02f4 143 #define cfgPSWUSCFG0_PCIE_MC_CNTL 0x02f6 144 #define cfgPSWUSCFG0_PCIE_MC_ADDR0 0x02f8 145 #define cfgPSWUSCFG0_PCIE_MC_ADDR1 0x02fc 146 #define cfgPSWUSCFG0_PCIE_MC_RCV0 0x0300 147 #define cfgPSWUSCFG0_PCIE_MC_RCV1 0x0304 148 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 0x0308 149 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 0x030c 150 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 151 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 152 #define cfgPCIE_MC_OVERLAY_BAR0 0x0318 153 #define cfgPCIE_MC_OVERLAY_BAR1 0x031c 154 #define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 0x0320 155 #define cfgPSWUSCFG0_PCIE_LTR_CAP 0x0324 156 #define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 0x0328 157 #define cfgPSWUSCFG0_PCIE_ARI_CAP 0x032c 158 #define cfgPSWUSCFG0_PCIE_ARI_CNTL 0x032e 159 #define cfgPCIE_L1_PM_SUB_CAP_LIST 0x0370 160 #define cfgPCIE_L1_PM_SUB_CAP 0x0374 161 #define cfgPCIE_L1_PM_SUB_CNTL 0x0378 162 #define cfgPCIE_L1_PM_SUB_CNTL2 0x037c 163 #define cfgPCIE_ESM_CAP_LIST 0x03c4 164 #define cfgPCIE_ESM_HEADER_1 0x03c8 165 #define cfgPCIE_ESM_HEADER_2 0x03cc 166 #define cfgPCIE_ESM_STATUS 0x03ce 167 #define cfgPCIE_ESM_CTRL 0x03d0 168 #define cfgPCIE_ESM_CAP_1 0x03d4 169 #define cfgPCIE_ESM_CAP_2 0x03d8 170 #define cfgPCIE_ESM_CAP_3 0x03dc 171 #define cfgPCIE_ESM_CAP_4 0x03e0 172 #define cfgPCIE_ESM_CAP_5 0x03e4 173 #define cfgPCIE_ESM_CAP_6 0x03e8 174 #define cfgPCIE_ESM_CAP_7 0x03ec 175 176 177 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp 178 // base address: 0x0 179 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000 180 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002 181 #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004 182 #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006 183 #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008 184 #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009 185 #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a 186 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b 187 #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c 188 #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d 189 #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e 190 #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f 191 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010 192 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014 193 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018 194 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c 195 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020 196 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024 197 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c 198 #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030 199 #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034 200 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c 201 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d 202 #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e 203 #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f 204 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048 205 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c 206 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050 207 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052 208 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054 209 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064 210 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066 211 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068 212 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c 213 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e 214 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070 215 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074 216 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076 217 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088 218 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c 219 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e 220 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090 221 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094 222 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096 223 #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 0x0098 224 #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 0x009c 225 #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 0x009e 226 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0 227 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2 228 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 229 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 230 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8 231 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac 232 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac 233 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0 234 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0 235 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4 236 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0 237 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2 238 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4 239 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8 240 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 241 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 242 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 243 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 244 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 245 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 246 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 247 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c 248 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e 249 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 250 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 251 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a 252 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c 253 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 254 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 255 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 256 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 257 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 258 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 259 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 260 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 261 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 262 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 263 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 264 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 265 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c 266 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170 267 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174 268 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178 269 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 270 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 271 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 272 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 273 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 274 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204 275 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208 276 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c 277 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210 278 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214 279 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218 280 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c 281 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220 282 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224 283 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228 284 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c 285 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230 286 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 287 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 288 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 289 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c 290 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 291 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254 292 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 293 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c 294 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e 295 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 296 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 297 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 298 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 299 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 300 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 301 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 302 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 303 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 304 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274 305 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 306 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 307 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 308 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 309 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 310 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 311 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 312 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 313 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 314 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 315 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 316 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 317 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 318 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 319 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 320 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 321 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 322 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 323 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4 324 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6 325 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 326 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4 327 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6 328 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 329 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4 330 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6 331 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 332 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 333 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 334 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4 335 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6 336 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 337 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x02e4 338 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x02e8 339 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 340 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4 341 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6 342 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8 343 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc 344 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300 345 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304 346 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308 347 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c 348 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 349 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 350 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 351 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324 352 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 353 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c 354 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e 355 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 356 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334 357 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338 358 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a 359 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c 360 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e 361 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340 362 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 363 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 364 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346 365 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 366 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 367 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 368 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 369 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 370 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 371 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 372 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 373 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 374 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 375 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 376 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 377 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 378 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c 379 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 380 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 381 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 382 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c 383 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 384 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 385 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 386 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c 387 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 388 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 389 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 390 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c 391 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 392 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 393 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 394 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c 395 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 396 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 397 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 398 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c 399 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 400 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 401 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 402 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c 403 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 404 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 405 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 406 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c 407 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 408 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 409 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 410 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c 411 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 412 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 413 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 414 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 415 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac 416 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 417 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 418 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 419 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc 420 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 421 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 422 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 423 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 424 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc 425 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 426 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 427 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 428 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec 429 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 430 431 432 // addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp 433 // base address: 0x0 434 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 435 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 436 #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 437 #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 438 #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 439 #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 440 #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a 441 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b 442 #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c 443 #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d 444 #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e 445 #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f 446 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 447 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 448 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 449 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c 450 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 451 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 452 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c 453 #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 454 #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 455 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c 456 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d 457 #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e 458 #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f 459 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 460 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c 461 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 462 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 463 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 464 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 465 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 466 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 467 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c 468 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e 469 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 470 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 471 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 472 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 473 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c 474 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e 475 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 476 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 477 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 478 #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 479 #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c 480 #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e 481 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 482 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 483 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 484 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 485 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 486 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac 487 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac 488 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 489 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 490 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 491 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 492 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 493 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 494 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 495 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 496 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 497 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 498 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 499 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 500 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 501 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 502 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c 503 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e 504 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 505 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 506 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a 507 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c 508 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 509 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 510 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 511 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 512 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 513 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 514 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 515 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 516 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 517 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 518 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 519 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 520 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c 521 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 522 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 523 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 524 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 525 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 526 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 527 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 528 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 529 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 530 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 531 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c 532 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 533 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 534 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 535 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c 536 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 537 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 538 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 539 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c 540 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 541 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 542 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 543 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 544 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c 545 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 546 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 547 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 548 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c 549 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e 550 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 551 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 552 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 553 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 554 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 555 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 556 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 557 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 558 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 559 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 560 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 561 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 562 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 563 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 564 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 565 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 566 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 567 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 568 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 569 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 570 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 571 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 572 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 573 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 574 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 575 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 576 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 577 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 578 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 579 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 580 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 581 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 582 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 583 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 584 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 585 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 586 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 587 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 588 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 589 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 590 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 591 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 592 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x02e4 593 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x02e8 594 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 595 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 596 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 597 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 598 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc 599 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 600 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 601 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 602 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c 603 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 604 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 605 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 606 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 607 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 608 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c 609 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e 610 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 611 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 612 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 613 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a 614 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c 615 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e 616 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 617 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 618 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 619 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 620 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 621 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 622 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 623 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 624 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 625 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 626 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 627 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 628 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 629 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 630 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 631 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 632 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 633 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c 634 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 635 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 636 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 637 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c 638 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 639 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 640 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 641 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c 642 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 643 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 644 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 645 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c 646 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 647 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 648 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 649 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c 650 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 651 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 652 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 653 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c 654 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 655 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 656 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 657 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c 658 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 659 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 660 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 661 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c 662 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 663 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 664 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 665 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c 666 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 667 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 668 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 669 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 670 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac 671 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 672 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 673 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 674 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc 675 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 676 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 677 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 678 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 679 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc 680 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 681 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 682 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 683 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec 684 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 685 686 687 // addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp 688 // base address: 0x0 689 #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000 690 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002 691 #define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004 692 #define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006 693 #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008 694 #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009 695 #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a 696 #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b 697 #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c 698 #define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d 699 #define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e 700 #define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f 701 #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010 702 #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018 703 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c 704 #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e 705 #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020 706 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024 707 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028 708 #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c 709 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030 710 #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034 711 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c 712 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d 713 #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e 714 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050 715 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052 716 #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054 717 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058 718 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a 719 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c 720 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060 721 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062 722 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064 723 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068 724 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a 725 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c 726 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070 727 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072 728 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c 729 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080 730 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082 731 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084 732 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088 733 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a 734 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c 735 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090 736 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092 737 #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0 738 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2 739 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4 740 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8 741 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8 742 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac 743 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0 744 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4 745 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 746 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 747 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108 748 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c 749 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110 750 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114 751 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118 752 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c 753 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e 754 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120 755 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124 756 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a 757 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c 758 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130 759 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136 760 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 761 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 762 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 763 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 764 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154 765 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158 766 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c 767 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160 768 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164 769 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168 770 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c 771 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170 772 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174 773 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178 774 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188 775 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c 776 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190 777 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194 778 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 779 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274 780 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278 781 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 782 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 783 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 784 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 785 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 786 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 787 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 788 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 789 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 790 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 791 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 792 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 793 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 794 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 795 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 796 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 797 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0 798 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4 799 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6 800 801 802 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp 803 // base address: 0x0 804 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000 805 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002 806 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004 807 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006 808 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008 809 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009 810 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a 811 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b 812 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c 813 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d 814 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e 815 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f 816 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010 817 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014 818 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018 819 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c 820 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020 821 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024 822 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c 823 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030 824 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034 825 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c 826 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d 827 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064 828 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066 829 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068 830 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c 831 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e 832 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070 833 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074 834 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076 835 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088 836 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c 837 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e 838 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090 839 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094 840 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096 841 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 0x0098 842 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 0x009c 843 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 0x009e 844 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0 845 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2 846 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4 847 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8 848 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8 849 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac 850 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac 851 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0 852 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0 853 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4 854 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0 855 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2 856 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4 857 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8 858 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 859 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 860 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 861 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 862 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 863 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 864 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158 865 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 866 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160 867 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164 868 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 869 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c 870 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170 871 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174 872 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178 873 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 874 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 875 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 876 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 877 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 878 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4 879 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6 880 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 881 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c 882 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e 883 884 885 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp 886 // base address: 0x0 887 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000 888 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002 889 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004 890 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006 891 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008 892 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009 893 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a 894 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b 895 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c 896 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d 897 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e 898 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f 899 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010 900 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014 901 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018 902 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c 903 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020 904 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024 905 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c 906 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030 907 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034 908 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c 909 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d 910 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064 911 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066 912 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068 913 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c 914 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e 915 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070 916 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074 917 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076 918 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088 919 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c 920 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e 921 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090 922 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094 923 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096 924 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 0x0098 925 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 0x009c 926 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 0x009e 927 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0 928 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2 929 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4 930 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8 931 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8 932 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac 933 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac 934 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0 935 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0 936 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4 937 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0 938 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2 939 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4 940 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8 941 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 942 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 943 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 944 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 945 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 946 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 947 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158 948 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 949 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160 950 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164 951 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 952 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c 953 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170 954 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174 955 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178 956 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 957 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 958 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 959 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 960 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 961 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4 962 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6 963 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 964 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c 965 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e 966 967 968 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp 969 // base address: 0x0 970 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000 971 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002 972 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004 973 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006 974 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008 975 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009 976 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a 977 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b 978 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c 979 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d 980 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e 981 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f 982 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010 983 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014 984 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018 985 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c 986 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020 987 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024 988 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c 989 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030 990 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034 991 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c 992 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d 993 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064 994 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066 995 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068 996 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c 997 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e 998 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070 999 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074 1000 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076 1001 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088 1002 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c 1003 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e 1004 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090 1005 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094 1006 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096 1007 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 0x0098 1008 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 0x009c 1009 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 0x009e 1010 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0 1011 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2 1012 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4 1013 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8 1014 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8 1015 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac 1016 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac 1017 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0 1018 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0 1019 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4 1020 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0 1021 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2 1022 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4 1023 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8 1024 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1025 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1026 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 1027 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c 1028 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1029 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 1030 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158 1031 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1032 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160 1033 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164 1034 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1035 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c 1036 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170 1037 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174 1038 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178 1039 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 1040 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c 1041 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 1042 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 1043 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1044 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4 1045 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6 1046 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1047 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c 1048 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e 1049 1050 1051 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp 1052 // base address: 0x0 1053 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000 1054 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002 1055 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004 1056 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006 1057 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008 1058 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009 1059 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a 1060 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b 1061 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c 1062 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d 1063 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e 1064 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f 1065 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010 1066 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014 1067 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018 1068 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c 1069 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020 1070 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024 1071 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c 1072 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030 1073 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034 1074 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c 1075 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d 1076 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064 1077 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066 1078 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068 1079 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c 1080 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e 1081 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070 1082 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074 1083 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076 1084 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088 1085 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c 1086 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e 1087 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090 1088 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094 1089 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096 1090 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 0x0098 1091 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 0x009c 1092 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 0x009e 1093 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0 1094 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2 1095 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4 1096 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8 1097 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8 1098 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac 1099 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac 1100 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0 1101 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0 1102 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4 1103 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0 1104 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2 1105 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4 1106 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8 1107 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1108 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1109 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 1110 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c 1111 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1112 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 1113 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158 1114 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1115 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160 1116 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164 1117 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1118 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c 1119 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170 1120 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174 1121 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178 1122 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 1123 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c 1124 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 1125 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 1126 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1127 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4 1128 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6 1129 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1130 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c 1131 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e 1132 1133 1134 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp 1135 // base address: 0x0 1136 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000 1137 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002 1138 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004 1139 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006 1140 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008 1141 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009 1142 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a 1143 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b 1144 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c 1145 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d 1146 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e 1147 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f 1148 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010 1149 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014 1150 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018 1151 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c 1152 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020 1153 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024 1154 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c 1155 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030 1156 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034 1157 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c 1158 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d 1159 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064 1160 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066 1161 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068 1162 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c 1163 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e 1164 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070 1165 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074 1166 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076 1167 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088 1168 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c 1169 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e 1170 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090 1171 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094 1172 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096 1173 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 0x0098 1174 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 0x009c 1175 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 0x009e 1176 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0 1177 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2 1178 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4 1179 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8 1180 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8 1181 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac 1182 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac 1183 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0 1184 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0 1185 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4 1186 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0 1187 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2 1188 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4 1189 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8 1190 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1191 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1192 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 1193 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c 1194 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1195 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 1196 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158 1197 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1198 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160 1199 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164 1200 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1201 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c 1202 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170 1203 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174 1204 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178 1205 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 1206 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c 1207 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 1208 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 1209 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1210 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4 1211 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6 1212 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1213 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c 1214 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e 1215 1216 1217 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp 1218 // base address: 0x0 1219 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000 1220 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002 1221 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004 1222 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006 1223 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008 1224 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009 1225 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a 1226 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b 1227 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c 1228 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d 1229 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e 1230 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f 1231 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010 1232 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014 1233 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018 1234 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c 1235 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020 1236 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024 1237 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c 1238 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030 1239 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034 1240 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c 1241 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d 1242 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064 1243 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066 1244 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068 1245 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c 1246 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e 1247 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070 1248 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074 1249 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076 1250 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088 1251 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c 1252 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e 1253 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090 1254 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094 1255 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096 1256 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 0x0098 1257 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 0x009c 1258 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 0x009e 1259 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0 1260 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2 1261 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4 1262 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8 1263 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8 1264 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac 1265 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac 1266 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0 1267 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0 1268 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4 1269 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0 1270 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2 1271 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4 1272 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8 1273 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1274 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1275 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 1276 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c 1277 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1278 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 1279 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158 1280 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1281 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160 1282 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164 1283 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1284 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c 1285 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170 1286 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174 1287 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178 1288 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 1289 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c 1290 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 1291 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 1292 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1293 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4 1294 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6 1295 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1296 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c 1297 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e 1298 1299 1300 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp 1301 // base address: 0x0 1302 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000 1303 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002 1304 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004 1305 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006 1306 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008 1307 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009 1308 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a 1309 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b 1310 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c 1311 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d 1312 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e 1313 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f 1314 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010 1315 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014 1316 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018 1317 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c 1318 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020 1319 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024 1320 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c 1321 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030 1322 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034 1323 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c 1324 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d 1325 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064 1326 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066 1327 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068 1328 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c 1329 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e 1330 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070 1331 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074 1332 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076 1333 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088 1334 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c 1335 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e 1336 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090 1337 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094 1338 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096 1339 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 0x0098 1340 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 0x009c 1341 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 0x009e 1342 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0 1343 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2 1344 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4 1345 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8 1346 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8 1347 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac 1348 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac 1349 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0 1350 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0 1351 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4 1352 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0 1353 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2 1354 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4 1355 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8 1356 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1357 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1358 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 1359 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c 1360 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1361 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 1362 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158 1363 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1364 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160 1365 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164 1366 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1367 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c 1368 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170 1369 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174 1370 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178 1371 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 1372 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c 1373 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 1374 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 1375 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1376 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4 1377 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6 1378 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1379 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c 1380 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e 1381 1382 1383 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp 1384 // base address: 0x0 1385 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000 1386 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002 1387 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004 1388 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006 1389 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008 1390 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009 1391 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a 1392 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b 1393 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c 1394 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d 1395 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e 1396 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f 1397 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010 1398 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014 1399 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018 1400 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c 1401 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020 1402 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024 1403 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c 1404 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030 1405 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034 1406 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c 1407 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d 1408 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064 1409 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066 1410 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068 1411 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c 1412 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e 1413 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070 1414 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074 1415 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076 1416 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088 1417 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c 1418 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e 1419 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090 1420 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094 1421 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096 1422 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 0x0098 1423 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 0x009c 1424 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 0x009e 1425 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0 1426 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2 1427 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4 1428 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8 1429 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8 1430 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac 1431 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac 1432 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0 1433 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0 1434 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4 1435 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0 1436 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2 1437 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4 1438 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8 1439 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1440 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1441 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 1442 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c 1443 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1444 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 1445 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158 1446 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1447 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160 1448 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164 1449 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1450 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c 1451 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170 1452 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174 1453 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178 1454 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 1455 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c 1456 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 1457 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 1458 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1459 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4 1460 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6 1461 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1462 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c 1463 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e 1464 1465 1466 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp 1467 // base address: 0x0 1468 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000 1469 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002 1470 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004 1471 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006 1472 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008 1473 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009 1474 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a 1475 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b 1476 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c 1477 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d 1478 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e 1479 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f 1480 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010 1481 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014 1482 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018 1483 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c 1484 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020 1485 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024 1486 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c 1487 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030 1488 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034 1489 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c 1490 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d 1491 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064 1492 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066 1493 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068 1494 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c 1495 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e 1496 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070 1497 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074 1498 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076 1499 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088 1500 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c 1501 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e 1502 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090 1503 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094 1504 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096 1505 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 0x0098 1506 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 0x009c 1507 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 0x009e 1508 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0 1509 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2 1510 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4 1511 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8 1512 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8 1513 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac 1514 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac 1515 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0 1516 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0 1517 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4 1518 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0 1519 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2 1520 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4 1521 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8 1522 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1523 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1524 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108 1525 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c 1526 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1527 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154 1528 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158 1529 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1530 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160 1531 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164 1532 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1533 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c 1534 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170 1535 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174 1536 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178 1537 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188 1538 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c 1539 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190 1540 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194 1541 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1542 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4 1543 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6 1544 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1545 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c 1546 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e 1547 1548 1549 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp 1550 // base address: 0x0 1551 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000 1552 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002 1553 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004 1554 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006 1555 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008 1556 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009 1557 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a 1558 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b 1559 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c 1560 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d 1561 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e 1562 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f 1563 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010 1564 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014 1565 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018 1566 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c 1567 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020 1568 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024 1569 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c 1570 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030 1571 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034 1572 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c 1573 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d 1574 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064 1575 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066 1576 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068 1577 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c 1578 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e 1579 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070 1580 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074 1581 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076 1582 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088 1583 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c 1584 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e 1585 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090 1586 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094 1587 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096 1588 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 0x0098 1589 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 0x009c 1590 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 0x009e 1591 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0 1592 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2 1593 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4 1594 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8 1595 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8 1596 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac 1597 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac 1598 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0 1599 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0 1600 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4 1601 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0 1602 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2 1603 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4 1604 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8 1605 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1606 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1607 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108 1608 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c 1609 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1610 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154 1611 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158 1612 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1613 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160 1614 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164 1615 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1616 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c 1617 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170 1618 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174 1619 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178 1620 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188 1621 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c 1622 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190 1623 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194 1624 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1625 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4 1626 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6 1627 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1628 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c 1629 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e 1630 1631 1632 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp 1633 // base address: 0x0 1634 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000 1635 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002 1636 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004 1637 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006 1638 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008 1639 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009 1640 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a 1641 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b 1642 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c 1643 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d 1644 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e 1645 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f 1646 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010 1647 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014 1648 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018 1649 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c 1650 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020 1651 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024 1652 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c 1653 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030 1654 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034 1655 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c 1656 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d 1657 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064 1658 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066 1659 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068 1660 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c 1661 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e 1662 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070 1663 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074 1664 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076 1665 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088 1666 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c 1667 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e 1668 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090 1669 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094 1670 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096 1671 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 0x0098 1672 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 0x009c 1673 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 0x009e 1674 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0 1675 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2 1676 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4 1677 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8 1678 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8 1679 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac 1680 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac 1681 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0 1682 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0 1683 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4 1684 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0 1685 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2 1686 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4 1687 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8 1688 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1689 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1690 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108 1691 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c 1692 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1693 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154 1694 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158 1695 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1696 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160 1697 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164 1698 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1699 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c 1700 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170 1701 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174 1702 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178 1703 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188 1704 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c 1705 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190 1706 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194 1707 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1708 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4 1709 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6 1710 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1711 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c 1712 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e 1713 1714 1715 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp 1716 // base address: 0x0 1717 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000 1718 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002 1719 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004 1720 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006 1721 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008 1722 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009 1723 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a 1724 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b 1725 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c 1726 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d 1727 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e 1728 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f 1729 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010 1730 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014 1731 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018 1732 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c 1733 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020 1734 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024 1735 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c 1736 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030 1737 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034 1738 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c 1739 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d 1740 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064 1741 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066 1742 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068 1743 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c 1744 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e 1745 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070 1746 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074 1747 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076 1748 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088 1749 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c 1750 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e 1751 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090 1752 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094 1753 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096 1754 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 0x0098 1755 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 0x009c 1756 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 0x009e 1757 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0 1758 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2 1759 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4 1760 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8 1761 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8 1762 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac 1763 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac 1764 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0 1765 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0 1766 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4 1767 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0 1768 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2 1769 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4 1770 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8 1771 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1772 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1773 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108 1774 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c 1775 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1776 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154 1777 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158 1778 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1779 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160 1780 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164 1781 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1782 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c 1783 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170 1784 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174 1785 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178 1786 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188 1787 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c 1788 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190 1789 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194 1790 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1791 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4 1792 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6 1793 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1794 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c 1795 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e 1796 1797 1798 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp 1799 // base address: 0x0 1800 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000 1801 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002 1802 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004 1803 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006 1804 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008 1805 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009 1806 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a 1807 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b 1808 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c 1809 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d 1810 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e 1811 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f 1812 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010 1813 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014 1814 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018 1815 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c 1816 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020 1817 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024 1818 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c 1819 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030 1820 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034 1821 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c 1822 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d 1823 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064 1824 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066 1825 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068 1826 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c 1827 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e 1828 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070 1829 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074 1830 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076 1831 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088 1832 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c 1833 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e 1834 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090 1835 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094 1836 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096 1837 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 0x0098 1838 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 0x009c 1839 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 0x009e 1840 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0 1841 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2 1842 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4 1843 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8 1844 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8 1845 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac 1846 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac 1847 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0 1848 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0 1849 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4 1850 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0 1851 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2 1852 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4 1853 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8 1854 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1855 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1856 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108 1857 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c 1858 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1859 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154 1860 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158 1861 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1862 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160 1863 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164 1864 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1865 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c 1866 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170 1867 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174 1868 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178 1869 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188 1870 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c 1871 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190 1872 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194 1873 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1874 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4 1875 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6 1876 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1877 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c 1878 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e 1879 1880 1881 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp 1882 // base address: 0x0 1883 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000 1884 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002 1885 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004 1886 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006 1887 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008 1888 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009 1889 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a 1890 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b 1891 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c 1892 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d 1893 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e 1894 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f 1895 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010 1896 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014 1897 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018 1898 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c 1899 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020 1900 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024 1901 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c 1902 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030 1903 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034 1904 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c 1905 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d 1906 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064 1907 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066 1908 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068 1909 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c 1910 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e 1911 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070 1912 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074 1913 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076 1914 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088 1915 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c 1916 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e 1917 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090 1918 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094 1919 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096 1920 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 0x0098 1921 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 0x009c 1922 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 0x009e 1923 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0 1924 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2 1925 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4 1926 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8 1927 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8 1928 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac 1929 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac 1930 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0 1931 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0 1932 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4 1933 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0 1934 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2 1935 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4 1936 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8 1937 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1938 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1939 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108 1940 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c 1941 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1942 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154 1943 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158 1944 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1945 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160 1946 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164 1947 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1948 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c 1949 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170 1950 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174 1951 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178 1952 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188 1953 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c 1954 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190 1955 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194 1956 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1957 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4 1958 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6 1959 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1960 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c 1961 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e 1962 1963 1964 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp 1965 // base address: 0x0 1966 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000 1967 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002 1968 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004 1969 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006 1970 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008 1971 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009 1972 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a 1973 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b 1974 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c 1975 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d 1976 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e 1977 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f 1978 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010 1979 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014 1980 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018 1981 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c 1982 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020 1983 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024 1984 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c 1985 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030 1986 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034 1987 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c 1988 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d 1989 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064 1990 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066 1991 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068 1992 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c 1993 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e 1994 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070 1995 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074 1996 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076 1997 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088 1998 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c 1999 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e 2000 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090 2001 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094 2002 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096 2003 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 0x0098 2004 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 0x009c 2005 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 0x009e 2006 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0 2007 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2 2008 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4 2009 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8 2010 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8 2011 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac 2012 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac 2013 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0 2014 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0 2015 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4 2016 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0 2017 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2 2018 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4 2019 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8 2020 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2021 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2022 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108 2023 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c 2024 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2025 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154 2026 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158 2027 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2028 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160 2029 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164 2030 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2031 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c 2032 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170 2033 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174 2034 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178 2035 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188 2036 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c 2037 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190 2038 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194 2039 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2040 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4 2041 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6 2042 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2043 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c 2044 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e 2045 2046 2047 // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp 2048 // base address: 0x0 2049 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000 2050 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002 2051 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004 2052 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006 2053 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008 2054 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009 2055 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a 2056 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b 2057 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c 2058 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d 2059 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e 2060 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f 2061 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010 2062 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014 2063 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018 2064 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c 2065 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020 2066 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024 2067 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c 2068 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030 2069 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034 2070 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c 2071 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d 2072 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064 2073 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066 2074 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068 2075 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c 2076 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e 2077 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070 2078 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074 2079 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076 2080 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088 2081 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c 2082 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e 2083 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090 2084 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094 2085 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096 2086 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 0x0098 2087 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 0x009c 2088 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 0x009e 2089 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0 2090 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2 2091 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4 2092 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8 2093 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8 2094 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac 2095 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac 2096 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0 2097 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0 2098 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4 2099 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0 2100 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2 2101 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4 2102 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8 2103 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2104 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2105 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108 2106 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c 2107 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2108 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154 2109 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158 2110 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2111 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160 2112 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164 2113 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2114 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c 2115 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170 2116 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174 2117 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178 2118 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188 2119 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c 2120 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190 2121 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194 2122 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2123 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4 2124 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6 2125 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2126 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c 2127 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e 2128 2129 2130 // addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767] 2131 // base address: 0x0 2132 #define mmMM_INDEX 0x0000 2133 #define mmMM_INDEX_BASE_IDX 0 2134 #define mmMM_DATA 0x0001 2135 #define mmMM_DATA_BASE_IDX 0 2136 #define mmMM_INDEX_HI 0x0006 2137 #define mmMM_INDEX_HI_BASE_IDX 0 2138 2139 2140 // addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767] 2141 // base address: 0x0 2142 #define mmSYSHUB_INDEX_OVLP 0x0008 2143 #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 2144 #define mmSYSHUB_DATA_OVLP 0x0009 2145 #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 2146 #define mmPCIE_INDEX 0x000c 2147 #define mmPCIE_INDEX_BASE_IDX 0 2148 #define mmPCIE_DATA 0x000d 2149 #define mmPCIE_DATA_BASE_IDX 0 2150 #define mmPCIE_INDEX2 0x000e 2151 #define mmPCIE_INDEX2_BASE_IDX 0 2152 #define mmPCIE_DATA2 0x000f 2153 #define mmPCIE_DATA2_BASE_IDX 0 2154 #define mmSBIOS_SCRATCH_0 0x0034 2155 #define mmSBIOS_SCRATCH_0_BASE_IDX 1 2156 #define mmSBIOS_SCRATCH_1 0x0035 2157 #define mmSBIOS_SCRATCH_1_BASE_IDX 1 2158 #define mmSBIOS_SCRATCH_2 0x0036 2159 #define mmSBIOS_SCRATCH_2_BASE_IDX 1 2160 #define mmSBIOS_SCRATCH_3 0x0037 2161 #define mmSBIOS_SCRATCH_3_BASE_IDX 1 2162 #define mmBIOS_SCRATCH_0 0x0038 2163 #define mmBIOS_SCRATCH_0_BASE_IDX 1 2164 #define mmBIOS_SCRATCH_1 0x0039 2165 #define mmBIOS_SCRATCH_1_BASE_IDX 1 2166 #define mmBIOS_SCRATCH_2 0x003a 2167 #define mmBIOS_SCRATCH_2_BASE_IDX 1 2168 #define mmBIOS_SCRATCH_3 0x003b 2169 #define mmBIOS_SCRATCH_3_BASE_IDX 1 2170 #define mmBIOS_SCRATCH_4 0x003c 2171 #define mmBIOS_SCRATCH_4_BASE_IDX 1 2172 #define mmBIOS_SCRATCH_5 0x003d 2173 #define mmBIOS_SCRATCH_5_BASE_IDX 1 2174 #define mmBIOS_SCRATCH_6 0x003e 2175 #define mmBIOS_SCRATCH_6_BASE_IDX 1 2176 #define mmBIOS_SCRATCH_7 0x003f 2177 #define mmBIOS_SCRATCH_7_BASE_IDX 1 2178 #define mmBIOS_SCRATCH_8 0x0040 2179 #define mmBIOS_SCRATCH_8_BASE_IDX 1 2180 #define mmBIOS_SCRATCH_9 0x0041 2181 #define mmBIOS_SCRATCH_9_BASE_IDX 1 2182 #define mmBIOS_SCRATCH_10 0x0042 2183 #define mmBIOS_SCRATCH_10_BASE_IDX 1 2184 #define mmBIOS_SCRATCH_11 0x0043 2185 #define mmBIOS_SCRATCH_11_BASE_IDX 1 2186 #define mmBIOS_SCRATCH_12 0x0044 2187 #define mmBIOS_SCRATCH_12_BASE_IDX 1 2188 #define mmBIOS_SCRATCH_13 0x0045 2189 #define mmBIOS_SCRATCH_13_BASE_IDX 1 2190 #define mmBIOS_SCRATCH_14 0x0046 2191 #define mmBIOS_SCRATCH_14_BASE_IDX 1 2192 #define mmBIOS_SCRATCH_15 0x0047 2193 #define mmBIOS_SCRATCH_15_BASE_IDX 1 2194 #define mmBIF_RLC_INTR_CNTL 0x004c 2195 #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 2196 #define mmBIF_VCE_INTR_CNTL 0x004d 2197 #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 2198 #define mmBIF_UVD_INTR_CNTL 0x004e 2199 #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 2200 #define mmGFX_MMIOREG_CAM_ADDR0 0x006c 2201 #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 2202 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 2203 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 2204 #define mmGFX_MMIOREG_CAM_ADDR1 0x006e 2205 #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 2206 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 2207 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 2208 #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 2209 #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 2210 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 2211 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 2212 #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 2213 #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 2214 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 2215 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 2216 #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 2217 #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 2218 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 2219 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 2220 #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 2221 #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 2222 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 2223 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 2224 #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 2225 #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 2226 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 2227 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 2228 #define mmGFX_MMIOREG_CAM_ADDR7 0x007a 2229 #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 2230 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 2231 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 2232 #define mmGFX_MMIOREG_CAM_CNTL 0x007c 2233 #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 2234 #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d 2235 #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 2236 #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e 2237 #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 2238 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 2239 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 2240 2241 2242 // addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39] 2243 // base address: 0x20 2244 #define mmSYSHUB_INDEX 0x0008 2245 #define mmSYSHUB_INDEX_BASE_IDX 0 2246 #define mmSYSHUB_DATA 0x0009 2247 #define mmSYSHUB_DATA_BASE_IDX 0 2248 2249 2250 // addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975] 2251 // base address: 0x3480 2252 #define mmRCC_BIF_STRAP0 0x0000 2253 #define mmRCC_BIF_STRAP0_BASE_IDX 2 2254 #define mmRCC_DEV0_EPF0_STRAP0 0x000f 2255 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 2256 2257 2258 // addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975] 2259 // base address: 0x3480 2260 #define mmEP_PCIE_SCRATCH 0x0023 2261 #define mmEP_PCIE_SCRATCH_BASE_IDX 2 2262 #define mmEP_PCIE_CNTL 0x0025 2263 #define mmEP_PCIE_CNTL_BASE_IDX 2 2264 #define mmEP_PCIE_INT_CNTL 0x0026 2265 #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 2266 #define mmEP_PCIE_INT_STATUS 0x0027 2267 #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 2268 #define mmEP_PCIE_RX_CNTL2 0x0028 2269 #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 2270 #define mmEP_PCIE_BUS_CNTL 0x0029 2271 #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 2272 #define mmEP_PCIE_CFG_CNTL 0x002a 2273 #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 2274 #define mmEP_PCIE_TX_LTR_CNTL 0x002c 2275 #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 2276 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002d 2277 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2278 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002d 2279 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2280 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002d 2281 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2282 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002d 2283 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2284 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x002e 2285 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2286 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x002e 2287 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2288 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x002e 2289 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2290 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x002e 2291 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2292 #define mmEP_PCIE_F0_DPA_CAP 0x0032 2293 #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 2294 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0033 2295 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 2296 #define mmEP_PCIE_F0_DPA_CNTL 0x0033 2297 #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 2298 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0033 2299 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2300 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0034 2301 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2302 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0034 2303 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2304 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0034 2305 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2306 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0034 2307 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2308 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0035 2309 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2310 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0035 2311 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2312 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0035 2313 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2314 #define mmEP_PCIE_PME_CONTROL 0x0035 2315 #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 2316 #define mmEP_PCIEP_RESERVED 0x0036 2317 #define mmEP_PCIEP_RESERVED_BASE_IDX 2 2318 #define mmEP_PCIE_TX_CNTL 0x0038 2319 #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 2320 #define mmEP_PCIE_TX_REQUESTER_ID 0x0039 2321 #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 2322 #define mmEP_PCIE_ERR_CNTL 0x003a 2323 #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 2324 #define mmEP_PCIE_RX_CNTL 0x003b 2325 #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 2326 #define mmEP_PCIE_LC_SPEED_CNTL 0x003c 2327 #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 2328 2329 2330 // addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975] 2331 // base address: 0x3480 2332 #define mmDN_PCIE_RESERVED 0x0040 2333 #define mmDN_PCIE_RESERVED_BASE_IDX 2 2334 #define mmDN_PCIE_SCRATCH 0x0041 2335 #define mmDN_PCIE_SCRATCH_BASE_IDX 2 2336 #define mmDN_PCIE_CNTL 0x0043 2337 #define mmDN_PCIE_CNTL_BASE_IDX 2 2338 #define mmDN_PCIE_CONFIG_CNTL 0x0044 2339 #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 2340 #define mmDN_PCIE_RX_CNTL2 0x0045 2341 #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 2342 #define mmDN_PCIE_BUS_CNTL 0x0046 2343 #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 2344 #define mmDN_PCIE_CFG_CNTL 0x0047 2345 #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 2346 2347 2348 // addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975] 2349 // base address: 0x3480 2350 #define mmPCIE_ERR_CNTL 0x004f 2351 #define mmPCIE_ERR_CNTL_BASE_IDX 2 2352 #define mmPCIE_RX_CNTL 0x0050 2353 #define mmPCIE_RX_CNTL_BASE_IDX 2 2354 #define mmPCIE_LC_SPEED_CNTL 0x0051 2355 #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 2356 #define mmPCIE_LC_CNTL2 0x0052 2357 #define mmPCIE_LC_CNTL2_BASE_IDX 2 2358 #define mmPCIEP_STRAP_MISC 0x0053 2359 #define mmPCIEP_STRAP_MISC_BASE_IDX 2 2360 #define mmLTR_MSG_INFO_FROM_EP 0x0054 2361 #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 2362 2363 2364 // addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975] 2365 // base address: 0x3480 2366 #define mmRCC_PF_0_0_RCC_ERR_LOG 0x0085 2367 #define mmRCC_PF_0_0_RCC_ERR_LOG_BASE_IDX 2 2368 #define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN 0x00c0 2369 #define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN_BASE_IDX 2 2370 #define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE 0x00c3 2371 #define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 2372 #define mmRCC_PF_0_0_RCC_CONFIG_RESERVED 0x00c4 2373 #define mmRCC_PF_0_0_RCC_CONFIG_RESERVED_BASE_IDX 2 2374 #define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 2375 #define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2376 2377 2378 // addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975] 2379 // base address: 0x3480 2380 #define mmRCC_ERR_INT_CNTL 0x0086 2381 #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 2382 #define mmRCC_BACO_CNTL_MISC 0x0087 2383 #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 2384 #define mmRCC_RESET_EN 0x0088 2385 #define mmRCC_RESET_EN_BASE_IDX 2 2386 #define mmRCC_VDM_SUPPORT 0x0089 2387 #define mmRCC_VDM_SUPPORT_BASE_IDX 2 2388 #define mmRCC_PEER_REG_RANGE0 0x00be 2389 #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 2390 #define mmRCC_PEER_REG_RANGE1 0x00bf 2391 #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 2392 #define mmRCC_BUS_CNTL 0x00c1 2393 #define mmRCC_BUS_CNTL_BASE_IDX 2 2394 #define mmRCC_CONFIG_CNTL 0x00c2 2395 #define mmRCC_CONFIG_CNTL_BASE_IDX 2 2396 #define mmRCC_CONFIG_F0_BASE 0x00c6 2397 #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 2398 #define mmRCC_CONFIG_APER_SIZE 0x00c7 2399 #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 2400 #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 2401 #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 2402 #define mmRCC_XDMA_LO 0x00c9 2403 #define mmRCC_XDMA_LO_BASE_IDX 2 2404 #define mmRCC_XDMA_HI 0x00ca 2405 #define mmRCC_XDMA_HI_BASE_IDX 2 2406 #define mmRCC_FEATURES_CONTROL_MISC 0x00cb 2407 #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 2408 #define mmRCC_BUSNUM_CNTL1 0x00cc 2409 #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 2410 #define mmRCC_BUSNUM_LIST0 0x00cd 2411 #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 2412 #define mmRCC_BUSNUM_LIST1 0x00ce 2413 #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 2414 #define mmRCC_BUSNUM_CNTL2 0x00cf 2415 #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 2416 #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 2417 #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 2418 #define mmRCC_HOST_BUSNUM 0x00d1 2419 #define mmRCC_HOST_BUSNUM_BASE_IDX 2 2420 #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 2421 #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 2422 #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 2423 #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 2424 #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 2425 #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 2426 #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 2427 #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 2428 #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 2429 #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 2430 #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 2431 #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 2432 #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 2433 #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 2434 #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 2435 #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 2436 #define mmRCC_CMN_LINK_CNTL 0x00de 2437 #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 2438 #define mmRCC_EP_REQUESTERID_RESTORE 0x00df 2439 #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 2440 #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 2441 #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 2442 #define mmRCC_MH_ARB_CNTL 0x00e1 2443 #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 2444 2445 2446 // addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975] 2447 // base address: 0x3480 2448 #define mmBIF_MM_INDACCESS_CNTL 0x00e6 2449 #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 2450 #define mmBUS_CNTL 0x00e7 2451 #define mmBUS_CNTL_BASE_IDX 2 2452 #define mmBIF_SCRATCH0 0x00e8 2453 #define mmBIF_SCRATCH0_BASE_IDX 2 2454 #define mmBIF_SCRATCH1 0x00e9 2455 #define mmBIF_SCRATCH1_BASE_IDX 2 2456 #define mmBX_RESET_EN 0x00ed 2457 #define mmBX_RESET_EN_BASE_IDX 2 2458 #define mmMM_CFGREGS_CNTL 0x00ee 2459 #define mmMM_CFGREGS_CNTL_BASE_IDX 2 2460 #define mmBX_RESET_CNTL 0x00f0 2461 #define mmBX_RESET_CNTL_BASE_IDX 2 2462 #define mmINTERRUPT_CNTL 0x00f1 2463 #define mmINTERRUPT_CNTL_BASE_IDX 2 2464 #define mmINTERRUPT_CNTL2 0x00f2 2465 #define mmINTERRUPT_CNTL2_BASE_IDX 2 2466 #define mmCLKREQB_PAD_CNTL 0x00f8 2467 #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 2468 #define mmBIF_FEATURES_CONTROL_MISC 0x00fb 2469 #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 2470 #define mmBIF_DOORBELL_CNTL 0x00fc 2471 #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 2472 #define mmBIF_DOORBELL_INT_CNTL 0x00fd 2473 #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 2474 #define mmBIF_FB_EN 0x00ff 2475 #define mmBIF_FB_EN_BASE_IDX 2 2476 #define mmBIF_BUSY_DELAY_CNTR 0x0100 2477 #define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2 2478 #define mmBIF_MST_TRANS_PENDING_VF 0x0109 2479 #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 2480 #define mmBIF_SLV_TRANS_PENDING_VF 0x010a 2481 #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 2482 #define mmBACO_CNTL 0x010b 2483 #define mmBACO_CNTL_BASE_IDX 2 2484 #define mmBIF_BACO_EXIT_TIME0 0x010c 2485 #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 2486 #define mmBIF_BACO_EXIT_TIMER1 0x010d 2487 #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 2488 #define mmBIF_BACO_EXIT_TIMER2 0x010e 2489 #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 2490 #define mmBIF_BACO_EXIT_TIMER3 0x010f 2491 #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 2492 #define mmBIF_BACO_EXIT_TIMER4 0x0110 2493 #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 2494 #define mmMEM_TYPE_CNTL 0x0111 2495 #define mmMEM_TYPE_CNTL_BASE_IDX 2 2496 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113 2497 #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2 2498 #define mmBIF_VDDGFX_GFX0_LOWER 0x0114 2499 #define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 2 2500 #define mmBIF_VDDGFX_GFX0_UPPER 0x0115 2501 #define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 2 2502 #define mmBIF_VDDGFX_GFX1_LOWER 0x0116 2503 #define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 2 2504 #define mmBIF_VDDGFX_GFX1_UPPER 0x0117 2505 #define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 2 2506 #define mmBIF_VDDGFX_GFX2_LOWER 0x0118 2507 #define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 2 2508 #define mmBIF_VDDGFX_GFX2_UPPER 0x0119 2509 #define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 2 2510 #define mmBIF_VDDGFX_GFX3_LOWER 0x011a 2511 #define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 2 2512 #define mmBIF_VDDGFX_GFX3_UPPER 0x011b 2513 #define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 2 2514 #define mmBIF_VDDGFX_GFX4_LOWER 0x011c 2515 #define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 2 2516 #define mmBIF_VDDGFX_GFX4_UPPER 0x011d 2517 #define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 2 2518 #define mmBIF_VDDGFX_GFX5_LOWER 0x011e 2519 #define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 2 2520 #define mmBIF_VDDGFX_GFX5_UPPER 0x011f 2521 #define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 2 2522 #define mmBIF_VDDGFX_RSV1_LOWER 0x0120 2523 #define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 2 2524 #define mmBIF_VDDGFX_RSV1_UPPER 0x0121 2525 #define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 2 2526 #define mmBIF_VDDGFX_RSV2_LOWER 0x0122 2527 #define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 2 2528 #define mmBIF_VDDGFX_RSV2_UPPER 0x0123 2529 #define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 2 2530 #define mmBIF_VDDGFX_RSV3_LOWER 0x0124 2531 #define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 2 2532 #define mmBIF_VDDGFX_RSV3_UPPER 0x0125 2533 #define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 2 2534 #define mmBIF_VDDGFX_RSV4_LOWER 0x0126 2535 #define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 2 2536 #define mmBIF_VDDGFX_RSV4_UPPER 0x0127 2537 #define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 2 2538 #define mmBIF_VDDGFX_FB_CMP 0x0128 2539 #define mmBIF_VDDGFX_FB_CMP_BASE_IDX 2 2540 #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0129 2541 #define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 2 2542 #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x012a 2543 #define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 2 2544 #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x012b 2545 #define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 2 2546 #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x012c 2547 #define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 2 2548 #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d 2549 #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 2550 #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e 2551 #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 2552 #define mmBIF_RB_CNTL 0x012f 2553 #define mmBIF_RB_CNTL_BASE_IDX 2 2554 #define mmBIF_RB_BASE 0x0130 2555 #define mmBIF_RB_BASE_BASE_IDX 2 2556 #define mmBIF_RB_RPTR 0x0131 2557 #define mmBIF_RB_RPTR_BASE_IDX 2 2558 #define mmBIF_RB_WPTR 0x0132 2559 #define mmBIF_RB_WPTR_BASE_IDX 2 2560 #define mmBIF_RB_WPTR_ADDR_HI 0x0133 2561 #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 2562 #define mmBIF_RB_WPTR_ADDR_LO 0x0134 2563 #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 2564 #define mmMAILBOX_INDEX 0x0135 2565 #define mmMAILBOX_INDEX_BASE_IDX 2 2566 #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 2567 #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 2568 #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 2569 #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 2570 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 2571 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 2572 #define mmBIF_PERSTB_PAD_CNTL 0x0148 2573 #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 2574 #define mmBIF_PX_EN_PAD_CNTL 0x0149 2575 #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 2576 #define mmBIF_REFPADKIN_PAD_CNTL 0x014a 2577 #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 2578 #define mmBIF_CLKREQB_PAD_CNTL 0x014b 2579 #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 2580 2581 2582 // addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1 2583 // base address: 0x0 2584 #define mmBIF_BX_PF0_BIF_BME_STATUS 0x00eb 2585 #define mmBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 2586 #define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec 2587 #define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2588 #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2589 #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2590 #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2591 #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2592 #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2593 #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2594 #define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2595 #define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2596 #define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2597 #define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2598 #define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 2599 #define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2600 #define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 2601 #define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2602 #define mmBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 2603 #define mmBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 2604 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 2605 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2606 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 2607 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2608 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 2609 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2610 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 2611 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2612 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 2613 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2614 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 2615 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2616 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 2617 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2618 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 2619 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2620 #define mmBIF_BX_PF0_MAILBOX_CONTROL 0x013e 2621 #define mmBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 2622 #define mmBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f 2623 #define mmBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 2624 #define mmBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 2625 #define mmBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 2626 2627 2628 // addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487] 2629 // base address: 0x3a80 2630 #define mmNGDC_SDP_PORT_CTRL 0x01c2 2631 #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 2632 #define mmSHUB_REGS_IF_CTL 0x01c3 2633 #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 2634 #define mmNGDC_RESERVED_0 0x01cb 2635 #define mmNGDC_RESERVED_0_BASE_IDX 2 2636 #define mmNGDC_RESERVED_1 0x01cc 2637 #define mmNGDC_RESERVED_1_BASE_IDX 2 2638 #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd 2639 #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 2640 #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 2641 #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 2642 #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 2643 #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 2644 #define mmBIF_IH_DOORBELL_RANGE 0x01d2 2645 #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 2646 #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 2647 #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 2648 #define mmBIF_DOORBELL_FENCE_CNTL 0x01de 2649 #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 2650 #define mmS2A_MISC_CNTL 0x01df 2651 #define mmS2A_MISC_CNTL_BASE_IDX 2 2652 2653 2654 // addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2 2655 // base address: 0x0 2656 #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO 0x0400 2657 #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2658 #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI 0x0401 2659 #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2660 #define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA 0x0402 2661 #define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2662 #define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL 0x0403 2663 #define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 2664 #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO 0x0404 2665 #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2666 #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI 0x0405 2667 #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2668 #define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA 0x0406 2669 #define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2670 #define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL 0x0407 2671 #define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 2672 #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO 0x0408 2673 #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2674 #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI 0x0409 2675 #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2676 #define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA 0x040a 2677 #define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2678 #define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL 0x040b 2679 #define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 2680 #define mmRCC_PF_0_GFXMSIX_PBA 0x0800 2681 #define mmRCC_PF_0_GFXMSIX_PBA_BASE_IDX 3 2682 2683 2684 // addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..255] 2685 // base address: 0x0 2686 //#define mmBIF_BX_PF_MM_INDEX 0x0000 2687 //#define mmBIF_BX_PF_MM_DATA 0x0001 2688 //#define mmBIF_BX_PF_MM_INDEX_HI 0x0006 2689 2690 2691 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 2692 // base address: 0x0 2693 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 2694 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 2695 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 2696 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 2697 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 2698 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 2699 2700 2701 // addressBlock: nbio_nbif_rcc_dev0_epf0_vf0_BIFPFVFDEC1 2702 // base address: 0x0 2703 2704 2705 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 2706 // base address: 0x0 2707 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 2708 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 2709 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 2710 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2711 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2712 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2713 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2714 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2715 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2716 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2717 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2718 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2719 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2720 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2721 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 2722 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2723 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 2724 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2725 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 2726 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 2727 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 2728 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2729 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 2730 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2731 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 2732 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2733 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 2734 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2735 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 2736 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2737 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 2738 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2739 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 2740 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2741 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 2742 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2743 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 2744 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 2745 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 2746 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 2747 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 2748 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 2749 2750 2751 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 2752 // base address: 0x0 2753 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 2754 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 2755 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 2756 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 2757 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 2758 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 2759 2760 2761 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 2762 // base address: 0x0 2763 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 2764 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 2765 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 2766 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2767 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2768 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2769 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2770 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2771 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2772 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2773 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2774 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2775 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2776 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2777 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 2778 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2779 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 2780 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2781 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 2782 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 2783 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 2784 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2785 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 2786 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2787 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 2788 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2789 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 2790 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2791 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 2792 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2793 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 2794 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2795 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 2796 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2797 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 2798 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2799 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 2800 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 2801 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 2802 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 2803 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 2804 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 2805 2806 2807 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 2808 // base address: 0x0 2809 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 2810 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 2811 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 2812 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 2813 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 2814 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 2815 2816 2817 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 2818 // base address: 0x0 2819 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 2820 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 2821 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 2822 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2823 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2824 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2825 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2826 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2827 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2828 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2829 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2830 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2831 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2832 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2833 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 2834 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2835 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 2836 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2837 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 2838 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 2839 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 2840 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2841 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 2842 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2843 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 2844 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2845 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 2846 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2847 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 2848 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2849 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 2850 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2851 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 2852 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2853 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 2854 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2855 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 2856 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 2857 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 2858 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 2859 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 2860 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 2861 2862 2863 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 2864 // base address: 0x0 2865 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 2866 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 2867 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 2868 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 2869 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 2870 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 2871 2872 2873 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 2874 // base address: 0x0 2875 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 2876 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 2877 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 2878 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2879 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2880 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2881 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2882 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2883 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2884 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2885 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2886 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2887 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2888 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2889 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 2890 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2891 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 2892 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2893 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 2894 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 2895 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 2896 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2897 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 2898 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2899 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 2900 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2901 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 2902 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2903 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 2904 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2905 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 2906 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2907 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 2908 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2909 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 2910 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2911 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 2912 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 2913 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 2914 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 2915 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 2916 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 2917 2918 2919 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 2920 // base address: 0x0 2921 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 2922 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 2923 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 2924 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 2925 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 2926 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 2927 2928 2929 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 2930 // base address: 0x0 2931 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 2932 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 2933 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 2934 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2935 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2936 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2937 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2938 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2939 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2940 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2941 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2942 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2943 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2944 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2945 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 2946 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2947 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 2948 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2949 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 2950 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 2951 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 2952 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2953 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 2954 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2955 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 2956 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2957 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 2958 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2959 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 2960 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2961 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 2962 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2963 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 2964 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2965 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 2966 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2967 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 2968 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 2969 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 2970 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 2971 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 2972 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 2973 2974 2975 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 2976 // base address: 0x0 2977 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 2978 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 2979 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 2980 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 2981 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 2982 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 2983 2984 2985 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 2986 // base address: 0x0 2987 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 2988 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 2989 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 2990 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2991 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2992 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2993 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2994 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2995 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2996 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2997 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2998 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2999 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3000 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3001 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 3002 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3003 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 3004 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3005 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 3006 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 3007 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 3008 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3009 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 3010 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3011 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 3012 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3013 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 3014 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3015 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 3016 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3017 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 3018 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3019 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 3020 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3021 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 3022 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3023 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 3024 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 3025 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 3026 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 3027 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 3028 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 3029 3030 3031 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 3032 // base address: 0x0 3033 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 3034 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 3035 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 3036 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 3037 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 3038 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 3039 3040 3041 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 3042 // base address: 0x0 3043 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 3044 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 3045 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 3046 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3047 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3048 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3049 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3050 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3051 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3052 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3053 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3054 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3055 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3056 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3057 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 3058 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3059 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 3060 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3061 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 3062 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 3063 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 3064 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3065 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 3066 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3067 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 3068 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3069 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 3070 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3071 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 3072 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3073 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 3074 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3075 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 3076 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3077 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 3078 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3079 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 3080 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 3081 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 3082 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 3083 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 3084 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 3085 3086 3087 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 3088 // base address: 0x0 3089 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 3090 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 3091 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 3092 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 3093 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 3094 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 3095 3096 3097 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 3098 // base address: 0x0 3099 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 3100 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 3101 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 3102 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3103 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3104 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3105 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3106 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3107 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3108 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3109 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3110 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3111 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3112 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3113 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 3114 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3115 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 3116 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3117 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 3118 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 3119 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 3120 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3121 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 3122 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3123 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 3124 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3125 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 3126 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3127 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 3128 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3129 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 3130 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3131 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 3132 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3133 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 3134 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3135 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 3136 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 3137 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 3138 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 3139 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 3140 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 3141 3142 3143 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 3144 // base address: 0x0 3145 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 3146 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 3147 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 3148 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 3149 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 3150 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 3151 3152 3153 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 3154 // base address: 0x0 3155 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb 3156 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 3157 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec 3158 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3159 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3160 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3161 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3162 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3163 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3164 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3165 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3166 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3167 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3168 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3169 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 3170 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3171 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 3172 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3173 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 3174 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 3175 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 3176 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3177 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 3178 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3179 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 3180 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3181 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 3182 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3183 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a 3184 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3185 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b 3186 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3187 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c 3188 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3189 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d 3190 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3191 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e 3192 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 3193 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f 3194 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 3195 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 3196 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 3197 3198 3199 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 3200 // base address: 0x0 3201 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 3202 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 3203 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 3204 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 3205 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 3206 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 3207 3208 3209 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 3210 // base address: 0x0 3211 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb 3212 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 3213 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec 3214 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3215 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3216 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3217 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3218 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3219 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3220 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3221 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3222 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3223 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3224 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3225 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 3226 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3227 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 3228 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3229 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 3230 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 3231 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 3232 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3233 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 3234 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3235 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 3236 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3237 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 3238 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3239 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a 3240 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3241 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b 3242 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3243 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c 3244 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3245 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d 3246 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3247 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e 3248 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 3249 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f 3250 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 3251 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 3252 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 3253 3254 3255 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 3256 // base address: 0x0 3257 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 3258 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 3259 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 3260 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 3261 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 3262 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 3263 3264 3265 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 3266 // base address: 0x0 3267 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb 3268 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 3269 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec 3270 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3271 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3272 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3273 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3274 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3275 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3276 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3277 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3278 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3279 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3280 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3281 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 3282 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3283 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 3284 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3285 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 3286 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 3287 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 3288 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3289 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 3290 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3291 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 3292 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3293 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 3294 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3295 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a 3296 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3297 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b 3298 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3299 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c 3300 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3301 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d 3302 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3303 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e 3304 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 3305 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f 3306 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 3307 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 3308 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 3309 3310 3311 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 3312 // base address: 0x0 3313 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 3314 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 3315 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 3316 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 3317 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 3318 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 3319 3320 3321 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 3322 // base address: 0x0 3323 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb 3324 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 3325 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec 3326 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3327 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3328 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3329 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3330 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3331 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3332 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3333 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3334 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3335 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3336 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3337 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 3338 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3339 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 3340 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3341 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 3342 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 3343 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 3344 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3345 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 3346 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3347 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 3348 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3349 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 3350 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3351 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a 3352 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3353 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b 3354 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3355 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c 3356 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3357 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d 3358 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3359 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e 3360 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 3361 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f 3362 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 3363 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 3364 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 3365 3366 3367 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 3368 // base address: 0x0 3369 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 3370 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 3371 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 3372 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 3373 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 3374 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 3375 3376 3377 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 3378 // base address: 0x0 3379 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb 3380 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 3381 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec 3382 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3383 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3384 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3385 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3386 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3387 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3388 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3389 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3390 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3391 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3392 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3393 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 3394 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3395 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 3396 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3397 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 3398 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 3399 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 3400 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3401 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 3402 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3403 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 3404 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3405 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 3406 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3407 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a 3408 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3409 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b 3410 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3411 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c 3412 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3413 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d 3414 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3415 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e 3416 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 3417 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f 3418 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 3419 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 3420 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 3421 3422 3423 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 3424 // base address: 0x0 3425 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 3426 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 3427 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 3428 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 3429 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 3430 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 3431 3432 3433 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 3434 // base address: 0x0 3435 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb 3436 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 3437 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec 3438 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3439 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3440 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3441 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3442 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3443 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3444 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3445 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3446 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3447 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3448 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3449 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 3450 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3451 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 3452 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3453 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 3454 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 3455 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 3456 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3457 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 3458 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3459 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 3460 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3461 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 3462 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3463 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a 3464 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3465 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b 3466 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3467 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c 3468 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3469 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d 3470 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3471 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e 3472 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 3473 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f 3474 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 3475 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 3476 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 3477 3478 3479 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 3480 // base address: 0x0 3481 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 3482 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 3483 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 3484 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 3485 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 3486 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 3487 3488 3489 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 3490 // base address: 0x0 3491 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb 3492 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 3493 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec 3494 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3495 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3496 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3497 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3498 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3499 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3500 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3501 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3502 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3503 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3504 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3505 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 3506 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3507 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 3508 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3509 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 3510 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 3511 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 3512 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3513 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 3514 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3515 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 3516 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3517 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 3518 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3519 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a 3520 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3521 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b 3522 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3523 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c 3524 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3525 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d 3526 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3527 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e 3528 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 3529 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f 3530 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 3531 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 3532 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 3533 3534 3535 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 3536 // base address: 0x0 3537 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 3538 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 3539 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 3540 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 3541 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 3542 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 3543 3544 3545 // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 3546 // base address: 0x0 3547 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb 3548 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 3549 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec 3550 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3551 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3552 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3553 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3554 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3555 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3556 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3557 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3558 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3559 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3560 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3561 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 3562 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3563 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 3564 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3565 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 3566 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 3567 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 3568 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3569 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 3570 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3571 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 3572 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3573 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 3574 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3575 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a 3576 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3577 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b 3578 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3579 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c 3580 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3581 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d 3582 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3583 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e 3584 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 3585 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f 3586 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 3587 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 3588 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 3589 3590 3591 // addressBlock: syshub_mmreg_ind_syshubind 3592 // base address: 0x0 3593 #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK 0x10000 3594 #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 3595 #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 3596 #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c 3597 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 3598 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 3599 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL 0x10018 3600 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL 0x1001c 3601 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL 0x10020 3602 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL 0x10024 3603 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL 0x10028 3604 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL 0x1002c 3605 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL 0x10030 3606 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL 0x10034 3607 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL 0x10100 3608 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL 0x10104 3609 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL 0x10108 3610 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL 0x1010c 3611 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL 0x10110 3612 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL 0x10114 3613 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL 0x10118 3614 #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL 0x1011c 3615 #define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL 0x10300 3616 #define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE 0x10308 3617 #define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER 0x1030c 3618 #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK 0x10310 3619 #define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH 0x10f00 3620 #define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK 0x10f04 3621 #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 3622 #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 3623 #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 3624 #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c 3625 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 3626 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 3627 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL 0x11018 3628 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL 0x1101c 3629 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL 0x11020 3630 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL 0x11024 3631 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL 0x11028 3632 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL 0x1102c 3633 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL 0x11030 3634 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL 0x11034 3635 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL 0x11038 3636 #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL 0x1103c 3637 #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK 0x11040 3638 #define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD 0x20108 3639 #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS 0x30008 3640 #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS 0x31008 3641 #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS 0x32008 3642 #define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD 0x40108 3643 #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD 0x50008 3644 #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD 0x51008 3645 #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD 0x52008 3646 #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD 0x53008 3647 #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD 0x54008 3648 #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD 0x60108 3649 #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD 0x61108 3650 #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD 0x62108 3651 #define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS 0x70008 3652 3653 #endif 3654
Indexes created Fri Oct 03 02:09:57 GMT 2025