1 /* $NetBSD: bif_5_0_d.h,v 1.3 2021/12/18 23:45:09 riastradh Exp $ */ 2 3 /* 4 * BIF_5_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef BIF_5_0_D_H 27 #define BIF_5_0_D_H 28 29 #define mmMM_INDEX 0x0 30 #define mmMM_INDEX_HI 0x6 31 #define mmMM_DATA 0x1 32 #define mmCC_BIF_BX_FUSESTRAP0 0x14D7 33 #define mmCC_BIF_BX_STRAP2 0x152A 34 #define mmBIF_MM_INDACCESS_CNTL 0x1500 35 #define mmBIF_DOORBELL_APER_EN 0x1501 36 #define mmBUS_CNTL 0x1508 37 #define mmCONFIG_CNTL 0x1509 38 #define mmCONFIG_MEMSIZE 0x150a 39 #define mmCONFIG_RESERVED 0x1502 40 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 41 #define mmCONFIG_F0_BASE 0x150b 42 #define mmCONFIG_APER_SIZE 0x150c 43 #define mmCONFIG_REG_APER_SIZE 0x150d 44 #define mmBIF_SCRATCH0 0x150e 45 #define mmBIF_SCRATCH1 0x150f 46 #define mmBIF_RLC_INTR_CNTL 0x1510 47 #define mmBIF_BME_STATUS 0x1511 48 #define mmBIF_ATOMIC_ERR_LOG 0x1512 49 #define mmBX_RESET_EN 0x1514 50 #define mmMM_CFGREGS_CNTL 0x1513 51 #define mmHW_DEBUG 0x1515 52 #define mmMASTER_CREDIT_CNTL 0x1516 53 #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 54 #define mmBX_RESET_CNTL 0x1518 55 #define mmINTERRUPT_CNTL 0x151a 56 #define mmINTERRUPT_CNTL2 0x151b 57 #define mmBIF_DEBUG_CNTL 0x151c 58 #define mmBIF_DEBUG_MUX 0x151d 59 #define mmBIF_DEBUG_OUT 0x151e 60 #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 61 #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 62 #define mmCLKREQB_PAD_CNTL 0x1521 63 #define mmCLKREQB_PERF_COUNTER 0x1522 64 #define mmBIF_XDMA_LO 0x14c0 65 #define mmBIF_XDMA_HI 0x14c1 66 #define mmBIF_FEATURES_CONTROL_MISC 0x14c2 67 #define mmBIF_DOORBELL_CNTL 0x14c3 68 #define mmBIF_SLVARB_MODE 0x14c4 69 #define mmBIF_CLK_CTRL 0x14c5 70 #define mmBIF_FB_EN 0x1524 71 #define mmBIF_BUSNUM_CNTL1 0x1525 72 #define mmBIF_BUSNUM_LIST0 0x1526 73 #define mmBIF_BUSNUM_LIST1 0x1527 74 #define mmBIF_BUSNUM_CNTL2 0x152b 75 #define mmBIF_BUSY_DELAY_CNTR 0x1529 76 #define mmBIF_PERFMON_CNTL 0x152c 77 #define mmBIF_PERFCOUNTER0_RESULT 0x152d 78 #define mmBIF_PERFCOUNTER1_RESULT 0x152e 79 #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 80 #define mmGPU_HDP_FLUSH_REQ 0x1537 81 #define mmGPU_HDP_FLUSH_DONE 0x1538 82 #define mmSLAVE_HANG_ERROR 0x153b 83 #define mmCAPTURE_HOST_BUSNUM 0x153c 84 #define mmHOST_BUSNUM 0x153d 85 #define mmPEER_REG_RANGE0 0x153e 86 #define mmPEER_REG_RANGE1 0x153f 87 #define mmPEER0_FB_OFFSET_HI 0x14f3 88 #define mmPEER0_FB_OFFSET_LO 0x14f2 89 #define mmPEER1_FB_OFFSET_HI 0x14f1 90 #define mmPEER1_FB_OFFSET_LO 0x14f0 91 #define mmPEER2_FB_OFFSET_HI 0x14ef 92 #define mmPEER2_FB_OFFSET_LO 0x14ee 93 #define mmPEER3_FB_OFFSET_HI 0x14ed 94 #define mmPEER3_FB_OFFSET_LO 0x14ec 95 #define mmDBG_SMB_BYPASS_SRBM_ACCESS 0x14eb 96 #define mmBIF_MST_TRANS_PENDING 0x14ea 97 #define mmBIF_SLV_TRANS_PENDING 0x14e9 98 #define mmBIF_DEVFUNCNUM_LIST0 0x14e8 99 #define mmBIF_DEVFUNCNUM_LIST1 0x14e7 100 #define mmBACO_CNTL 0x14e5 101 #define mmBF_ANA_ISO_CNTL 0x14c7 102 #define mmMEM_TYPE_CNTL 0x14e4 103 #define mmBIF_BACO_DEBUG 0x14df 104 #define mmBIF_BACO_DEBUG_LATCH 0x14dc 105 #define mmBACO_CNTL_MISC 0x14db 106 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 107 #define mmBIF_VDDGFX_GFX0_LOWER 0x1428 108 #define mmBIF_VDDGFX_GFX0_UPPER 0x1429 109 #define mmBIF_VDDGFX_GFX1_LOWER 0x142a 110 #define mmBIF_VDDGFX_GFX1_UPPER 0x142b 111 #define mmBIF_VDDGFX_GFX2_LOWER 0x142c 112 #define mmBIF_VDDGFX_GFX2_UPPER 0x142d 113 #define mmBIF_VDDGFX_GFX3_LOWER 0x142e 114 #define mmBIF_VDDGFX_GFX3_UPPER 0x142f 115 #define mmBIF_VDDGFX_GFX4_LOWER 0x1430 116 #define mmBIF_VDDGFX_GFX4_UPPER 0x1431 117 #define mmBIF_VDDGFX_GFX5_LOWER 0x1432 118 #define mmBIF_VDDGFX_GFX5_UPPER 0x1433 119 #define mmBIF_VDDGFX_RSV1_LOWER 0x1434 120 #define mmBIF_VDDGFX_RSV1_UPPER 0x1435 121 #define mmBIF_VDDGFX_RSV2_LOWER 0x1436 122 #define mmBIF_VDDGFX_RSV2_UPPER 0x1437 123 #define mmBIF_VDDGFX_RSV3_LOWER 0x1438 124 #define mmBIF_VDDGFX_RSV3_UPPER 0x1439 125 #define mmBIF_VDDGFX_RSV4_LOWER 0x143a 126 #define mmBIF_VDDGFX_RSV4_UPPER 0x143b 127 #define mmBIF_VDDGFX_FB_CMP 0x143c 128 #define mmBIF_SMU_INDEX 0x143d 129 #define mmBIF_SMU_DATA 0x143e 130 #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc 131 #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd 132 #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe 133 #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff 134 #define mmIMPCTL_RESET 0x14f5 135 #define mmGARLIC_FLUSH_CNTL 0x1401 136 #define mmGARLIC_FLUSH_ADDR_START_0 0x1402 137 #define mmGARLIC_FLUSH_ADDR_START_1 0x1404 138 #define mmGARLIC_FLUSH_ADDR_START_2 0x1406 139 #define mmGARLIC_FLUSH_ADDR_START_3 0x1408 140 #define mmGARLIC_FLUSH_ADDR_START_4 0x140a 141 #define mmGARLIC_FLUSH_ADDR_START_5 0x140c 142 #define mmGARLIC_FLUSH_ADDR_START_6 0x140e 143 #define mmGARLIC_FLUSH_ADDR_START_7 0x1410 144 #define mmGARLIC_FLUSH_ADDR_END_0 0x1403 145 #define mmGARLIC_FLUSH_ADDR_END_1 0x1405 146 #define mmGARLIC_FLUSH_ADDR_END_2 0x1407 147 #define mmGARLIC_FLUSH_ADDR_END_3 0x1409 148 #define mmGARLIC_FLUSH_ADDR_END_4 0x140b 149 #define mmGARLIC_FLUSH_ADDR_END_5 0x140d 150 #define mmGARLIC_FLUSH_ADDR_END_6 0x140f 151 #define mmGARLIC_FLUSH_ADDR_END_7 0x1411 152 #define mmGARLIC_FLUSH_REQ 0x1412 153 #define mmGPU_GARLIC_FLUSH_REQ 0x1413 154 #define mmGPU_GARLIC_FLUSH_DONE 0x1414 155 #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 156 #define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 157 #define mmBIOS_SCRATCH_0 0x5c9 158 #define mmBIOS_SCRATCH_1 0x5ca 159 #define mmBIOS_SCRATCH_2 0x5cb 160 #define mmBIOS_SCRATCH_3 0x5cc 161 #define mmBIOS_SCRATCH_4 0x5cd 162 #define mmBIOS_SCRATCH_5 0x5ce 163 #define mmBIOS_SCRATCH_6 0x5cf 164 #define mmBIOS_SCRATCH_7 0x5d0 165 #define mmBIOS_SCRATCH_8 0x5d1 166 #define mmBIOS_SCRATCH_9 0x5d2 167 #define mmBIOS_SCRATCH_10 0x5d3 168 #define mmBIOS_SCRATCH_11 0x5d4 169 #define mmBIOS_SCRATCH_12 0x5d5 170 #define mmBIOS_SCRATCH_13 0x5d6 171 #define mmBIOS_SCRATCH_14 0x5d7 172 #define mmBIOS_SCRATCH_15 0x5d8 173 #define mmBIF_RB_CNTL 0x1530 174 #define mmBIF_RB_BASE 0x1531 175 #define mmBIF_RB_RPTR 0x1532 176 #define mmBIF_RB_WPTR 0x1533 177 #define mmBIF_RB_WPTR_ADDR_HI 0x1534 178 #define mmBIF_RB_WPTR_ADDR_LO 0x1535 179 #define mmMAILBOX_INDEX 0x14c6 180 #define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8 181 #define mmMAILBOX_MSGBUF_TRN_DW1 0x14c9 182 #define mmMAILBOX_MSGBUF_TRN_DW2 0x14ca 183 #define mmMAILBOX_MSGBUF_TRN_DW3 0x14cb 184 #define mmMAILBOX_MSGBUF_RCV_DW0 0x14cc 185 #define mmMAILBOX_MSGBUF_RCV_DW1 0x14cd 186 #define mmMAILBOX_MSGBUF_RCV_DW2 0x14ce 187 #define mmMAILBOX_MSGBUF_RCV_DW3 0x14cf 188 #define mmMAILBOX_CONTROL 0x14d0 189 #define mmMAILBOX_INT_CNTL 0x14d1 190 #define mmBIF_VIRT_RESET_REQ 0x14d2 191 #define mmVM_INIT_STATUS 0x14d3 192 #define mmBIF_GPUIOV_RESET_NOTIFICATION 0x14d5 193 #define mmBIF_GPUIOV_VM_INIT_STATUS 0x14d6 194 #define mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0x14d8 195 #define mmBIF_GPUIOV_GPU_IDLE_LATENCY 0x141c 196 #define mmBIF_GPUIOV_MMIO_MAP_RANGE0 0x141d 197 #define mmBIF_GPUIOV_MMIO_MAP_RANGE1 0x141e 198 #define mmBIF_GPUIOV_MMIO_MAP_RANGE2 0x141f 199 #define mmBIF_GPUIOV_MMIO_MAP_RANGE3 0x1420 200 #define mmBIF_GPUIOV_MMIO_MAP_RANGE4 0x1421 201 #define mmBIF_GPUIOV_MMIO_MAP_RANGE5 0x1422 202 #define mmBIF_GPU_IDLE_LATENCY 0x1415 203 #define mmBIF_MMIO_MAP_RANGE0 0x1416 204 #define mmBIF_MMIO_MAP_RANGE1 0x1417 205 #define mmBIF_MMIO_MAP_RANGE2 0x1418 206 #define mmBIF_MMIO_MAP_RANGE3 0x1419 207 #define mmBIF_MMIO_MAP_RANGE4 0x141a 208 #define mmBIF_MMIO_MAP_RANGE5 0x141b 209 #define mmVENDOR_ID 0x0 210 #define mmDEVICE_ID 0x0 211 #define mmCOMMAND 0x1 212 #define mmSTATUS 0x1 213 #define mmREVISION_ID 0x2 214 #define mmPROG_INTERFACE 0x2 215 #define mmSUB_CLASS 0x2 216 #define mmBASE_CLASS 0x2 217 #define mmCACHE_LINE 0x3 218 #define mmLATENCY 0x3 219 #define mmHEADER 0x3 220 #define mmBIST 0x3 221 #define mmBASE_ADDR_1 0x4 222 #define mmBASE_ADDR_2 0x5 223 #define mmBASE_ADDR_3 0x6 224 #define mmBASE_ADDR_4 0x7 225 #define mmBASE_ADDR_5 0x8 226 #define mmBASE_ADDR_6 0x9 227 #define mmROM_BASE_ADDR 0xc 228 #define mmCAP_PTR 0xd 229 #define mmINTERRUPT_LINE 0xf 230 #define mmINTERRUPT_PIN 0xf 231 #define mmADAPTER_ID 0xb 232 #define mmMIN_GRANT 0xf 233 #define mmMAX_LATENCY 0xf 234 #define mmVENDOR_CAP_LIST 0x12 235 #define mmADAPTER_ID_W 0x13 236 #define mmPMI_CAP_LIST 0x14 237 #define mmPMI_CAP 0x14 238 #define mmPMI_STATUS_CNTL 0x15 239 #define mmPCIE_CAP_LIST 0x16 240 #define mmPCIE_CAP 0x16 241 #define mmDEVICE_CAP 0x17 242 #define mmDEVICE_CNTL 0x18 243 #define mmDEVICE_STATUS 0x18 244 #define mmLINK_CAP 0x19 245 #define mmLINK_CNTL 0x1a 246 #define mmLINK_STATUS 0x1a 247 #define mmDEVICE_CAP2 0x1f 248 #define mmDEVICE_CNTL2 0x20 249 #define mmDEVICE_STATUS2 0x20 250 #define mmLINK_CAP2 0x21 251 #define mmLINK_CNTL2 0x22 252 #define mmLINK_STATUS2 0x22 253 #define mmMSI_CAP_LIST 0x28 254 #define mmMSI_MSG_CNTL 0x28 255 #define mmMSI_MSG_ADDR_LO 0x29 256 #define mmMSI_MSG_ADDR_HI 0x2a 257 #define mmMSI_MSG_DATA_64 0x2b 258 #define mmMSI_MSG_DATA 0x2a 259 #define mmMSI_MASK 0x2b 260 #define mmMSI_PENDING 0x2c 261 #define mmMSI_MASK_64 0x2c 262 #define mmMSI_PENDING_64 0x2d 263 #define mmMSIX_CAP_LIST 0x30 264 #define mmMSIX_MSG_CNTL 0x30 265 #define mmMSIX_TABLE 0x31 266 #define mmMSIX_PBA 0x32 267 #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 268 #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 269 #define mmPCIE_VENDOR_SPECIFIC1 0x42 270 #define mmPCIE_VENDOR_SPECIFIC2 0x43 271 #define mmPCIE_VC_ENH_CAP_LIST 0x44 272 #define mmPCIE_PORT_VC_CAP_REG1 0x45 273 #define mmPCIE_PORT_VC_CAP_REG2 0x46 274 #define mmPCIE_PORT_VC_CNTL 0x47 275 #define mmPCIE_PORT_VC_STATUS 0x47 276 #define mmPCIE_VC0_RESOURCE_CAP 0x48 277 #define mmPCIE_VC0_RESOURCE_CNTL 0x49 278 #define mmPCIE_VC0_RESOURCE_STATUS 0x4a 279 #define mmPCIE_VC1_RESOURCE_CAP 0x4b 280 #define mmPCIE_VC1_RESOURCE_CNTL 0x4c 281 #define mmPCIE_VC1_RESOURCE_STATUS 0x4d 282 #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 283 #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 284 #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 285 #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 286 #define mmPCIE_UNCORR_ERR_STATUS 0x55 287 #define mmPCIE_UNCORR_ERR_MASK 0x56 288 #define mmPCIE_UNCORR_ERR_SEVERITY 0x57 289 #define mmPCIE_CORR_ERR_STATUS 0x58 290 #define mmPCIE_CORR_ERR_MASK 0x59 291 #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a 292 #define mmPCIE_HDR_LOG0 0x5b 293 #define mmPCIE_HDR_LOG1 0x5c 294 #define mmPCIE_HDR_LOG2 0x5d 295 #define mmPCIE_HDR_LOG3 0x5e 296 #define mmPCIE_TLP_PREFIX_LOG0 0x62 297 #define mmPCIE_TLP_PREFIX_LOG1 0x63 298 #define mmPCIE_TLP_PREFIX_LOG2 0x64 299 #define mmPCIE_TLP_PREFIX_LOG3 0x65 300 #define mmPCIE_BAR_ENH_CAP_LIST 0x80 301 #define mmPCIE_BAR1_CAP 0x81 302 #define mmPCIE_BAR1_CNTL 0x82 303 #define mmPCIE_BAR2_CAP 0x83 304 #define mmPCIE_BAR2_CNTL 0x84 305 #define mmPCIE_BAR3_CAP 0x85 306 #define mmPCIE_BAR3_CNTL 0x86 307 #define mmPCIE_BAR4_CAP 0x87 308 #define mmPCIE_BAR4_CNTL 0x88 309 #define mmPCIE_BAR5_CAP 0x89 310 #define mmPCIE_BAR5_CNTL 0x8a 311 #define mmPCIE_BAR6_CAP 0x8b 312 #define mmPCIE_BAR6_CNTL 0x8c 313 #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 314 #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 315 #define mmPCIE_PWR_BUDGET_DATA 0x92 316 #define mmPCIE_PWR_BUDGET_CAP 0x93 317 #define mmPCIE_DPA_ENH_CAP_LIST 0x94 318 #define mmPCIE_DPA_CAP 0x95 319 #define mmPCIE_DPA_LATENCY_INDICATOR 0x96 320 #define mmPCIE_DPA_STATUS 0x97 321 #define mmPCIE_DPA_CNTL 0x97 322 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 323 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 324 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 325 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 326 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 327 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 328 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 329 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 330 #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c 331 #define mmPCIE_LINK_CNTL3 0x9d 332 #define mmPCIE_LANE_ERROR_STATUS 0x9e 333 #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f 334 #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f 335 #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 336 #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 337 #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 338 #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 339 #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 340 #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 341 #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 342 #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 343 #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 344 #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 345 #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 346 #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 347 #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 348 #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 349 #define mmPCIE_ACS_ENH_CAP_LIST 0xa8 350 #define mmPCIE_ACS_CAP 0xa9 351 #define mmPCIE_ACS_CNTL 0xa9 352 #define mmPCIE_ATS_ENH_CAP_LIST 0xac 353 #define mmPCIE_ATS_CAP 0xad 354 #define mmPCIE_ATS_CNTL 0xad 355 #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 356 #define mmPCIE_PAGE_REQ_CNTL 0xb1 357 #define mmPCIE_PAGE_REQ_STATUS 0xb1 358 #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 359 #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 360 #define mmPCIE_PASID_ENH_CAP_LIST 0xb4 361 #define mmPCIE_PASID_CAP 0xb5 362 #define mmPCIE_PASID_CNTL 0xb5 363 #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 364 #define mmPCIE_TPH_REQR_CAP 0xb9 365 #define mmPCIE_TPH_REQR_CNTL 0xba 366 #define mmPCIE_MC_ENH_CAP_LIST 0xbc 367 #define mmPCIE_MC_CAP 0xbd 368 #define mmPCIE_MC_CNTL 0xbd 369 #define mmPCIE_MC_ADDR0 0xbe 370 #define mmPCIE_MC_ADDR1 0xbf 371 #define mmPCIE_MC_RCV0 0xc0 372 #define mmPCIE_MC_RCV1 0xc1 373 #define mmPCIE_MC_BLOCK_ALL0 0xc2 374 #define mmPCIE_MC_BLOCK_ALL1 0xc3 375 #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 376 #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 377 #define mmPCIE_LTR_ENH_CAP_LIST 0xc8 378 #define mmPCIE_LTR_CAP 0xc9 379 #define mmPCIE_ARI_ENH_CAP_LIST 0xca 380 #define mmPCIE_ARI_CAP 0xcb 381 #define mmPCIE_ARI_CNTL 0xcb 382 #define mmPCIE_SRIOV_ENH_CAP_LIST 0xcc 383 #define mmPCIE_SRIOV_CAP 0xcd 384 #define mmPCIE_SRIOV_CONTROL 0xce 385 #define mmPCIE_SRIOV_STATUS 0xce 386 #define mmPCIE_SRIOV_INITIAL_VFS 0xcf 387 #define mmPCIE_SRIOV_TOTAL_VFS 0xcf 388 #define mmPCIE_SRIOV_NUM_VFS 0xd0 389 #define mmPCIE_SRIOV_FUNC_DEP_LINK 0xd0 390 #define mmPCIE_SRIOV_FIRST_VF_OFFSET 0xd1 391 #define mmPCIE_SRIOV_VF_STRIDE 0xd1 392 #define mmPCIE_SRIOV_VF_DEVICE_ID 0xd2 393 #define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xd3 394 #define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0xd4 395 #define mmPCIE_SRIOV_VF_BASE_ADDR_0 0xd5 396 #define mmPCIE_SRIOV_VF_BASE_ADDR_1 0xd6 397 #define mmPCIE_SRIOV_VF_BASE_ADDR_2 0xd7 398 #define mmPCIE_SRIOV_VF_BASE_ADDR_3 0xd8 399 #define mmPCIE_SRIOV_VF_BASE_ADDR_4 0xd9 400 #define mmPCIE_SRIOV_VF_BASE_ADDR_5 0xda 401 #define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xdb 402 #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x100 403 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101 404 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x102 405 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0x103 406 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0x104 407 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105 408 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0x106 409 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0x107 410 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x108 411 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x109 412 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0x10a 413 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x10b 414 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x10c 415 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x10d 416 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10e 417 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10f 418 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x110 419 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111 420 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112 421 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x113 422 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x114 423 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115 424 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x116 425 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117 426 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x118 427 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x119 428 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x11a 429 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x11b 430 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0x11c 431 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0x11d 432 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0x11e 433 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0x11f 434 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0x120 435 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0x121 436 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122 437 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0x124 438 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125 439 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126 440 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0x127 441 #define mmPCIE_INDEX 0xe 442 #define mmPCIE_DATA 0xf 443 #define mmPCIE_INDEX_2 0xc 444 #define mmPCIE_DATA_2 0xd 445 #define ixPCIE_HOLD_TRAINING_A 0x1500820 446 #define ixLNCNT_CONTROL 0x1508030 447 #define ixCFG_LNC_WINDOW 0x1508031 448 #define ixLNCNT_QUAN_THRD 0x1508032 449 #define ixLNCNT_WEIGHT 0x1508033 450 #define ixLNC_TOTAL_WACC 0x1508034 451 #define ixLNC_BW_WACC 0x1508035 452 #define ixLNC_CMN_WACC 0x1508036 453 #define mmPCIE_EFUSE 0xfc0 454 #define mmPCIE_EFUSE2 0xfc1 455 #define mmPCIE_EFUSE3 0xfc2 456 #define mmPCIE_EFUSE4 0xfc3 457 #define mmPCIE_EFUSE5 0xfc4 458 #define mmPCIE_EFUSE6 0xfc5 459 #define mmPCIE_EFUSE7 0xfc6 460 #define ixPCIE_WRAP_SCRATCH1 0x1308001 461 #define ixPCIE_WRAP_SCRATCH2 0x1308002 462 #define ixPCIE_WRAP_REG_TARG_MISC 0x1308005 463 #define ixPCIE_WRAP_DTM_MISC 0x1308006 464 #define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 465 #define ixPCIE_WRAP_MISC 0x1308008 466 #define ixPCIE_WRAP_PIF_MISC 0x1308009 467 #define ixPCIE_RXDET_OVERRIDE 0x130800a 468 #define ixREG_ADAPT_pciecore0_CONTROL 0x1308090 469 #define ixREG_ADAPT_pwregt_CONTROL 0x1308096 470 #define ixREG_ADAPT_pwregr_CONTROL 0x1308097 471 #define ixREG_ADAPT_pif0_CONTROL 0x1308098 472 #define ixPCIE_RESERVED 0x1400000 473 #define ixPCIE_SCRATCH 0x1400001 474 #define ixPCIE_HW_DEBUG 0x1400002 475 #define ixPCIE_RX_NUM_NAK 0x140000e 476 #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f 477 #define ixPCIE_CNTL 0x1400010 478 #define ixPCIE_CONFIG_CNTL 0x1400011 479 #define ixPCIE_DEBUG_CNTL 0x1400012 480 #define ixPCIE_INT_CNTL 0x140001a 481 #define ixPCIE_INT_STATUS 0x140001b 482 #define ixPCIE_CNTL2 0x140001c 483 #define ixPCIE_RX_CNTL2 0x140001d 484 #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e 485 #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f 486 #define ixPCIE_CI_CNTL 0x1400020 487 #define ixPCIE_BUS_CNTL 0x1400021 488 #define ixPCIE_LC_STATE6 0x1400022 489 #define ixPCIE_LC_STATE7 0x1400023 490 #define ixPCIE_LC_STATE8 0x1400024 491 #define ixPCIE_LC_STATE9 0x1400025 492 #define ixPCIE_LC_STATE10 0x1400026 493 #define ixPCIE_LC_STATE11 0x1400027 494 #define ixPCIE_LC_STATUS1 0x1400028 495 #define ixPCIE_LC_STATUS2 0x1400029 496 #define ixPCIE_WPR_CNTL 0x1400030 497 #define ixPCIE_RX_LAST_TLP0 0x1400031 498 #define ixPCIE_RX_LAST_TLP1 0x1400032 499 #define ixPCIE_RX_LAST_TLP2 0x1400033 500 #define ixPCIE_RX_LAST_TLP3 0x1400034 501 #define ixPCIE_TX_LAST_TLP0 0x1400035 502 #define ixPCIE_TX_LAST_TLP1 0x1400036 503 #define ixPCIE_TX_LAST_TLP2 0x1400037 504 #define ixPCIE_TX_LAST_TLP3 0x1400038 505 #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a 506 #define ixPCIE_I2C_REG_DATA 0x140003b 507 #define ixPCIE_CFG_CNTL 0x140003c 508 #define ixPCIE_LC_PM_CNTL 0x140003d 509 #define ixPCIE_P_CNTL 0x1400040 510 #define ixPCIE_P_BUF_STATUS 0x1400041 511 #define ixPCIE_P_DECODER_STATUS 0x1400042 512 #define ixPCIE_P_MISC_STATUS 0x1400043 513 #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 514 #define ixPCIE_OBFF_CNTL 0x1400061 515 #define ixPCIE_TX_LTR_CNTL 0x1400060 516 #define ixPCIE_IDLE_STATUS 0x1400062 517 #define ixPCIE_PERF_COUNT_CNTL 0x1400080 518 #define ixPCIE_PERF_CNTL_TXCLK 0x1400081 519 #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 520 #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 521 #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 522 #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 523 #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 524 #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 525 #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 526 #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 527 #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a 528 #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b 529 #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c 530 #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d 531 #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e 532 #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f 533 #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 534 #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 535 #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 536 #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 537 #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 538 #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 539 #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 540 #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 541 #define ixPCIE_STRAP_F0 0x14000b0 542 #define ixPCIE_STRAP_F1 0x14000b1 543 #define ixPCIE_STRAP_F2 0x14000b2 544 #define ixPCIE_STRAP_F3 0x14000b3 545 #define ixPCIE_STRAP_F4 0x14000b4 546 #define ixPCIE_STRAP_F5 0x14000b5 547 #define ixPCIE_STRAP_F6 0x14000b6 548 #define ixPCIE_STRAP_MSIX 0x14000b7 549 #define ixPCIE_STRAP_MISC 0x14000c0 550 #define ixPCIE_STRAP_MISC2 0x14000c1 551 #define ixPCIE_STRAP_PI 0x14000c2 552 #define ixPCIE_STRAP_I2C_BD 0x14000c4 553 #define ixPCIE_PRBS_CLR 0x14000c8 554 #define ixPCIE_PRBS_STATUS1 0x14000c9 555 #define ixPCIE_PRBS_STATUS2 0x14000ca 556 #define ixPCIE_PRBS_FREERUN 0x14000cb 557 #define ixPCIE_PRBS_MISC 0x14000cc 558 #define ixPCIE_PRBS_USER_PATTERN 0x14000cd 559 #define ixPCIE_PRBS_LO_BITCNT 0x14000ce 560 #define ixPCIE_PRBS_HI_BITCNT 0x14000cf 561 #define ixPCIE_PRBS_ERRCNT_0 0x14000d0 562 #define ixPCIE_PRBS_ERRCNT_1 0x14000d1 563 #define ixPCIE_PRBS_ERRCNT_2 0x14000d2 564 #define ixPCIE_PRBS_ERRCNT_3 0x14000d3 565 #define ixPCIE_PRBS_ERRCNT_4 0x14000d4 566 #define ixPCIE_PRBS_ERRCNT_5 0x14000d5 567 #define ixPCIE_PRBS_ERRCNT_6 0x14000d6 568 #define ixPCIE_PRBS_ERRCNT_7 0x14000d7 569 #define ixPCIE_PRBS_ERRCNT_8 0x14000d8 570 #define ixPCIE_PRBS_ERRCNT_9 0x14000d9 571 #define ixPCIE_PRBS_ERRCNT_10 0x14000da 572 #define ixPCIE_PRBS_ERRCNT_11 0x14000db 573 #define ixPCIE_PRBS_ERRCNT_12 0x14000dc 574 #define ixPCIE_PRBS_ERRCNT_13 0x14000dd 575 #define ixPCIE_PRBS_ERRCNT_14 0x14000de 576 #define ixPCIE_PRBS_ERRCNT_15 0x14000df 577 #define ixPCIE_F0_DPA_CAP 0x14000e0 578 #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 579 #define ixPCIE_F0_DPA_CNTL 0x14000e5 580 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 581 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 582 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 583 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea 584 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb 585 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec 586 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed 587 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee 588 #define mmSWRST_COMMAND_STATUS 0x14a0 589 #define mmSWRST_GENERAL_CONTROL 0x14a1 590 #define mmSWRST_COMMAND_0 0x14a2 591 #define mmSWRST_COMMAND_1 0x14a3 592 #define mmSWRST_CONTROL_0 0x14a4 593 #define mmSWRST_CONTROL_1 0x14a5 594 #define mmSWRST_CONTROL_2 0x14a6 595 #define mmSWRST_CONTROL_3 0x14a7 596 #define mmSWRST_CONTROL_4 0x14a8 597 #define mmSWRST_CONTROL_5 0x14a9 598 #define mmSWRST_CONTROL_6 0x14aa 599 #define mmSWRST_EP_COMMAND_0 0x14ab 600 #define mmSWRST_EP_CONTROL_0 0x14ac 601 #define mmCPM_CONTROL 0x14b8 602 #define mmGSKT_CONTROL 0x14bf 603 #define ixSWRST_COMMAND_1 0x1400103 604 #define ixLM_CONTROL 0x1400120 605 #define ixLM_PCIETXMUX0 0x1400121 606 #define ixLM_PCIETXMUX1 0x1400122 607 #define ixLM_PCIETXMUX2 0x1400123 608 #define ixLM_PCIETXMUX3 0x1400124 609 #define ixLM_PCIERXMUX0 0x1400125 610 #define ixLM_PCIERXMUX1 0x1400126 611 #define ixLM_PCIERXMUX2 0x1400127 612 #define ixLM_PCIERXMUX3 0x1400128 613 #define ixLM_LANEENABLE 0x1400129 614 #define ixLM_PRBSCONTROL 0x140012a 615 #define ixLM_POWERCONTROL 0x140012b 616 #define ixLM_POWERCONTROL1 0x140012c 617 #define ixLM_POWERCONTROL2 0x140012d 618 #define ixLM_POWERCONTROL3 0x140012e 619 #define ixLM_POWERCONTROL4 0x140012f 620 #define ixPB0_GLB_CTRL_REG0 0x1200004 621 #define ixPB0_GLB_CTRL_REG1 0x1200008 622 #define ixPB0_GLB_CTRL_REG2 0x120000c 623 #define ixPB0_GLB_CTRL_REG3 0x1200010 624 #define ixPB0_GLB_CTRL_REG4 0x1200014 625 #define ixPB0_GLB_CTRL_REG5 0x1200018 626 #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c 627 #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020 628 #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024 629 #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028 630 #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c 631 #define ixPB0_GLB_OVRD_REG0 0x1200030 632 #define ixPB0_GLB_OVRD_REG1 0x1200034 633 #define ixPB0_GLB_OVRD_REG2 0x1200038 634 #define ixPB0_HW_DEBUG 0x1202004 635 #define ixPB0_STRAP_GLB_REG0 0x1202020 636 #define ixPB0_STRAP_TX_REG0 0x1202024 637 #define ixPB0_STRAP_RX_REG0 0x1202028 638 #define ixPB0_STRAP_RX_REG1 0x120202c 639 #define ixPB0_STRAP_PLL_REG0 0x1202030 640 #define ixPB0_STRAP_PIN_REG0 0x1202034 641 #define ixPB0_STRAP_GLB_REG1 0x1202038 642 #define ixPB0_STRAP_GLB_REG2 0x120203c 643 #define ixPB0_DFT_JIT_INJ_REG0 0x1203000 644 #define ixPB0_DFT_JIT_INJ_REG1 0x1203004 645 #define ixPB0_DFT_JIT_INJ_REG2 0x1203008 646 #define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c 647 #define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010 648 #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000 649 #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010 650 #define ixPB0_PLL_RO0_CTRL_REG0 0x1204440 651 #define ixPB0_PLL_RO0_OVRD_REG0 0x1204450 652 #define ixPB0_PLL_RO0_OVRD_REG1 0x1204454 653 #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460 654 #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464 655 #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468 656 #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c 657 #define ixPB0_PLL_LC0_CTRL_REG0 0x1204480 658 #define ixPB0_PLL_LC0_OVRD_REG0 0x1204490 659 #define ixPB0_PLL_LC0_OVRD_REG1 0x1204494 660 #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500 661 #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504 662 #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508 663 #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c 664 #define ixPB0_RX_GLB_CTRL_REG0 0x1206000 665 #define ixPB0_RX_GLB_CTRL_REG1 0x1206004 666 #define ixPB0_RX_GLB_CTRL_REG2 0x1206008 667 #define ixPB0_RX_GLB_CTRL_REG3 0x120600c 668 #define ixPB0_RX_GLB_CTRL_REG4 0x1206010 669 #define ixPB0_RX_GLB_CTRL_REG5 0x1206014 670 #define ixPB0_RX_GLB_CTRL_REG6 0x1206018 671 #define ixPB0_RX_GLB_CTRL_REG7 0x120601c 672 #define ixPB0_RX_GLB_CTRL_REG8 0x1206020 673 #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028 674 #define ixPB0_RX_GLB_OVRD_REG0 0x1206030 675 #define ixPB0_RX_GLB_OVRD_REG1 0x1206034 676 #define ixPB0_RX_LANE0_CTRL_REG0 0x1206440 677 #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448 678 #define ixPB0_RX_LANE1_CTRL_REG0 0x1206480 679 #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488 680 #define ixPB0_RX_LANE2_CTRL_REG0 0x1206500 681 #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508 682 #define ixPB0_RX_LANE3_CTRL_REG0 0x1206600 683 #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608 684 #define ixPB0_RX_LANE4_CTRL_REG0 0x1206800 685 #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848 686 #define ixPB0_RX_LANE5_CTRL_REG0 0x1206880 687 #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888 688 #define ixPB0_RX_LANE6_CTRL_REG0 0x1206900 689 #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908 690 #define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00 691 #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08 692 #define ixPB0_RX_LANE8_CTRL_REG0 0x1207440 693 #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448 694 #define ixPB0_RX_LANE9_CTRL_REG0 0x1207480 695 #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488 696 #define ixPB0_RX_LANE10_CTRL_REG0 0x1207500 697 #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508 698 #define ixPB0_RX_LANE11_CTRL_REG0 0x1207600 699 #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608 700 #define ixPB0_RX_LANE12_CTRL_REG0 0x1207840 701 #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848 702 #define ixPB0_RX_LANE13_CTRL_REG0 0x1207880 703 #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888 704 #define ixPB0_RX_LANE14_CTRL_REG0 0x1207900 705 #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908 706 #define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00 707 #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08 708 #define ixPB0_TX_GLB_CTRL_REG0 0x1208000 709 #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004 710 #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010 711 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014 712 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018 713 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c 714 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020 715 #define ixPB0_TX_GLB_OVRD_REG0 0x1208030 716 #define ixPB0_TX_GLB_OVRD_REG1 0x1208034 717 #define ixPB0_TX_GLB_OVRD_REG2 0x1208038 718 #define ixPB0_TX_GLB_OVRD_REG3 0x120803c 719 #define ixPB0_TX_GLB_OVRD_REG4 0x1208040 720 #define ixPB0_TX_LANE0_CTRL_REG0 0x1208440 721 #define ixPB0_TX_LANE0_OVRD_REG0 0x1208444 722 #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448 723 #define ixPB0_TX_LANE1_CTRL_REG0 0x1208480 724 #define ixPB0_TX_LANE1_OVRD_REG0 0x1208484 725 #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488 726 #define ixPB0_TX_LANE2_CTRL_REG0 0x1208500 727 #define ixPB0_TX_LANE2_OVRD_REG0 0x1208504 728 #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508 729 #define ixPB0_TX_LANE3_CTRL_REG0 0x1208600 730 #define ixPB0_TX_LANE3_OVRD_REG0 0x1208604 731 #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608 732 #define ixPB0_TX_LANE4_CTRL_REG0 0x1208840 733 #define ixPB0_TX_LANE4_OVRD_REG0 0x1208844 734 #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848 735 #define ixPB0_TX_LANE5_CTRL_REG0 0x1208880 736 #define ixPB0_TX_LANE5_OVRD_REG0 0x1208884 737 #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888 738 #define ixPB0_TX_LANE6_CTRL_REG0 0x1208900 739 #define ixPB0_TX_LANE6_OVRD_REG0 0x1208904 740 #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908 741 #define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00 742 #define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04 743 #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08 744 #define ixPB0_TX_LANE8_CTRL_REG0 0x1209440 745 #define ixPB0_TX_LANE8_OVRD_REG0 0x1209444 746 #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448 747 #define ixPB0_TX_LANE9_CTRL_REG0 0x1209480 748 #define ixPB0_TX_LANE9_OVRD_REG0 0x1209484 749 #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488 750 #define ixPB0_TX_LANE10_CTRL_REG0 0x1209500 751 #define ixPB0_TX_LANE10_OVRD_REG0 0x1209504 752 #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508 753 #define ixPB0_TX_LANE11_CTRL_REG0 0x1209600 754 #define ixPB0_TX_LANE11_OVRD_REG0 0x1209604 755 #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608 756 #define ixPB0_TX_LANE12_CTRL_REG0 0x1209840 757 #define ixPB0_TX_LANE12_OVRD_REG0 0x1209844 758 #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848 759 #define ixPB0_TX_LANE13_CTRL_REG0 0x1209880 760 #define ixPB0_TX_LANE13_OVRD_REG0 0x1209884 761 #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888 762 #define ixPB0_TX_LANE14_CTRL_REG0 0x1209900 763 #define ixPB0_TX_LANE14_OVRD_REG0 0x1209904 764 #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908 765 #define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00 766 #define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04 767 #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08 768 #define ixPB1_GLB_CTRL_REG0 0x2200004 769 #define ixPB1_GLB_CTRL_REG1 0x2200008 770 #define ixPB1_GLB_CTRL_REG2 0x220000c 771 #define ixPB1_GLB_CTRL_REG3 0x2200010 772 #define ixPB1_GLB_CTRL_REG4 0x2200014 773 #define ixPB1_GLB_CTRL_REG5 0x2200018 774 #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c 775 #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020 776 #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024 777 #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028 778 #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c 779 #define ixPB1_GLB_OVRD_REG0 0x2200030 780 #define ixPB1_GLB_OVRD_REG1 0x2200034 781 #define ixPB1_GLB_OVRD_REG2 0x2200038 782 #define ixPB1_HW_DEBUG 0x2202004 783 #define ixPB1_STRAP_GLB_REG0 0x2202020 784 #define ixPB1_STRAP_TX_REG0 0x2202024 785 #define ixPB1_STRAP_RX_REG0 0x2202028 786 #define ixPB1_STRAP_RX_REG1 0x220202c 787 #define ixPB1_STRAP_PLL_REG0 0x2202030 788 #define ixPB1_STRAP_PIN_REG0 0x2202034 789 #define ixPB1_STRAP_GLB_REG1 0x2202038 790 #define ixPB1_STRAP_GLB_REG2 0x220203c 791 #define ixPB1_DFT_JIT_INJ_REG0 0x2203000 792 #define ixPB1_DFT_JIT_INJ_REG1 0x2203004 793 #define ixPB1_DFT_JIT_INJ_REG2 0x2203008 794 #define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c 795 #define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010 796 #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000 797 #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010 798 #define ixPB1_PLL_RO0_CTRL_REG0 0x2204440 799 #define ixPB1_PLL_RO0_OVRD_REG0 0x2204450 800 #define ixPB1_PLL_RO0_OVRD_REG1 0x2204454 801 #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460 802 #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464 803 #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468 804 #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c 805 #define ixPB1_PLL_LC0_CTRL_REG0 0x2204480 806 #define ixPB1_PLL_LC0_OVRD_REG0 0x2204490 807 #define ixPB1_PLL_LC0_OVRD_REG1 0x2204494 808 #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500 809 #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504 810 #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508 811 #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c 812 #define ixPB1_RX_GLB_CTRL_REG0 0x2206000 813 #define ixPB1_RX_GLB_CTRL_REG1 0x2206004 814 #define ixPB1_RX_GLB_CTRL_REG2 0x2206008 815 #define ixPB1_RX_GLB_CTRL_REG3 0x220600c 816 #define ixPB1_RX_GLB_CTRL_REG4 0x2206010 817 #define ixPB1_RX_GLB_CTRL_REG5 0x2206014 818 #define ixPB1_RX_GLB_CTRL_REG6 0x2206018 819 #define ixPB1_RX_GLB_CTRL_REG7 0x220601c 820 #define ixPB1_RX_GLB_CTRL_REG8 0x2206020 821 #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028 822 #define ixPB1_RX_GLB_OVRD_REG0 0x2206030 823 #define ixPB1_RX_GLB_OVRD_REG1 0x2206034 824 #define ixPB1_RX_LANE0_CTRL_REG0 0x2206440 825 #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448 826 #define ixPB1_RX_LANE1_CTRL_REG0 0x2206480 827 #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488 828 #define ixPB1_RX_LANE2_CTRL_REG0 0x2206500 829 #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508 830 #define ixPB1_RX_LANE3_CTRL_REG0 0x2206600 831 #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608 832 #define ixPB1_RX_LANE4_CTRL_REG0 0x2206800 833 #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848 834 #define ixPB1_RX_LANE5_CTRL_REG0 0x2206880 835 #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888 836 #define ixPB1_RX_LANE6_CTRL_REG0 0x2206900 837 #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908 838 #define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00 839 #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08 840 #define ixPB1_RX_LANE8_CTRL_REG0 0x2207440 841 #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448 842 #define ixPB1_RX_LANE9_CTRL_REG0 0x2207480 843 #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488 844 #define ixPB1_RX_LANE10_CTRL_REG0 0x2207500 845 #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508 846 #define ixPB1_RX_LANE11_CTRL_REG0 0x2207600 847 #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608 848 #define ixPB1_RX_LANE12_CTRL_REG0 0x2207840 849 #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848 850 #define ixPB1_RX_LANE13_CTRL_REG0 0x2207880 851 #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888 852 #define ixPB1_RX_LANE14_CTRL_REG0 0x2207900 853 #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908 854 #define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00 855 #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08 856 #define ixPB1_TX_GLB_CTRL_REG0 0x2208000 857 #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004 858 #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010 859 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014 860 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018 861 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c 862 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020 863 #define ixPB1_TX_GLB_OVRD_REG0 0x2208030 864 #define ixPB1_TX_GLB_OVRD_REG1 0x2208034 865 #define ixPB1_TX_GLB_OVRD_REG2 0x2208038 866 #define ixPB1_TX_GLB_OVRD_REG3 0x220803c 867 #define ixPB1_TX_GLB_OVRD_REG4 0x2208040 868 #define ixPB1_TX_LANE0_CTRL_REG0 0x2208440 869 #define ixPB1_TX_LANE0_OVRD_REG0 0x2208444 870 #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448 871 #define ixPB1_TX_LANE1_CTRL_REG0 0x2208480 872 #define ixPB1_TX_LANE1_OVRD_REG0 0x2208484 873 #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488 874 #define ixPB1_TX_LANE2_CTRL_REG0 0x2208500 875 #define ixPB1_TX_LANE2_OVRD_REG0 0x2208504 876 #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508 877 #define ixPB1_TX_LANE3_CTRL_REG0 0x2208600 878 #define ixPB1_TX_LANE3_OVRD_REG0 0x2208604 879 #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608 880 #define ixPB1_TX_LANE4_CTRL_REG0 0x2208840 881 #define ixPB1_TX_LANE4_OVRD_REG0 0x2208844 882 #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848 883 #define ixPB1_TX_LANE5_CTRL_REG0 0x2208880 884 #define ixPB1_TX_LANE5_OVRD_REG0 0x2208884 885 #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888 886 #define ixPB1_TX_LANE6_CTRL_REG0 0x2208900 887 #define ixPB1_TX_LANE6_OVRD_REG0 0x2208904 888 #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908 889 #define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00 890 #define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04 891 #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08 892 #define ixPB1_TX_LANE8_CTRL_REG0 0x2209440 893 #define ixPB1_TX_LANE8_OVRD_REG0 0x2209444 894 #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448 895 #define ixPB1_TX_LANE9_CTRL_REG0 0x2209480 896 #define ixPB1_TX_LANE9_OVRD_REG0 0x2209484 897 #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488 898 #define ixPB1_TX_LANE10_CTRL_REG0 0x2209500 899 #define ixPB1_TX_LANE10_OVRD_REG0 0x2209504 900 #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508 901 #define ixPB1_TX_LANE11_CTRL_REG0 0x2209600 902 #define ixPB1_TX_LANE11_OVRD_REG0 0x2209604 903 #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608 904 #define ixPB1_TX_LANE12_CTRL_REG0 0x2209840 905 #define ixPB1_TX_LANE12_OVRD_REG0 0x2209844 906 #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848 907 #define ixPB1_TX_LANE13_CTRL_REG0 0x2209880 908 #define ixPB1_TX_LANE13_OVRD_REG0 0x2209884 909 #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888 910 #define ixPB1_TX_LANE14_CTRL_REG0 0x2209900 911 #define ixPB1_TX_LANE14_OVRD_REG0 0x2209904 912 #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908 913 #define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00 914 #define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04 915 #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08 916 #define ixPB0_PIF_SCRATCH 0x1100001 917 #define ixPB0_PIF_HW_DEBUG 0x1100002 918 #define ixPB0_PIF_STRAP_0 0x1100003 919 #define ixPB0_PIF_CTRL 0x1100004 920 #define ixPB0_PIF_TX_CTRL 0x1100008 921 #define ixPB0_PIF_TX_CTRL2 0x1100009 922 #define ixPB0_PIF_RX_CTRL 0x110000a 923 #define ixPB0_PIF_RX_CTRL2 0x110000b 924 #define ixPB0_PIF_GLB_OVRD 0x110000c 925 #define ixPB0_PIF_GLB_OVRD2 0x110000d 926 #define ixPB0_PIF_BIF_CMD_STATUS 0x1100010 927 #define ixPB0_PIF_CMD_BUS_CTRL 0x1100011 928 #define ixPB0_PIF_CMD_BUS_GLB_OVRD 0x1100013 929 #define ixPB0_PIF_LANE0_OVRD 0x1100014 930 #define ixPB0_PIF_LANE0_OVRD2 0x1100015 931 #define ixPB0_PIF_LANE1_OVRD 0x1100016 932 #define ixPB0_PIF_LANE1_OVRD2 0x1100017 933 #define ixPB0_PIF_LANE2_OVRD 0x1100018 934 #define ixPB0_PIF_LANE2_OVRD2 0x1100019 935 #define ixPB0_PIF_LANE3_OVRD 0x110001a 936 #define ixPB0_PIF_LANE3_OVRD2 0x110001b 937 #define ixPB0_PIF_LANE4_OVRD 0x110001c 938 #define ixPB0_PIF_LANE4_OVRD2 0x110001d 939 #define ixPB0_PIF_LANE5_OVRD 0x110001e 940 #define ixPB0_PIF_LANE5_OVRD2 0x110001f 941 #define ixPB0_PIF_LANE6_OVRD 0x1100020 942 #define ixPB0_PIF_LANE6_OVRD2 0x1100021 943 #define ixPB0_PIF_LANE7_OVRD 0x1100022 944 #define ixPB0_PIF_LANE7_OVRD2 0x1100023 945 #define ixPB1_PIF_SCRATCH 0x2100001 946 #define ixPB1_PIF_HW_DEBUG 0x2100002 947 #define ixPB1_PIF_STRAP_0 0x2100003 948 #define ixPB1_PIF_CTRL 0x2100004 949 #define ixPB1_PIF_TX_CTRL 0x2100008 950 #define ixPB1_PIF_TX_CTRL2 0x2100009 951 #define ixPB1_PIF_RX_CTRL 0x210000a 952 #define ixPB1_PIF_RX_CTRL2 0x210000b 953 #define ixPB1_PIF_GLB_OVRD 0x210000c 954 #define ixPB1_PIF_GLB_OVRD2 0x210000d 955 #define ixPB1_PIF_BIF_CMD_STATUS 0x2100010 956 #define ixPB1_PIF_CMD_BUS_CTRL 0x2100011 957 #define ixPB1_PIF_CMD_BUS_GLB_OVRD 0x2100013 958 #define ixPB1_PIF_LANE0_OVRD 0x2100014 959 #define ixPB1_PIF_LANE0_OVRD2 0x2100015 960 #define ixPB1_PIF_LANE1_OVRD 0x2100016 961 #define ixPB1_PIF_LANE1_OVRD2 0x2100017 962 #define ixPB1_PIF_LANE2_OVRD 0x2100018 963 #define ixPB1_PIF_LANE2_OVRD2 0x2100019 964 #define ixPB1_PIF_LANE3_OVRD 0x210001a 965 #define ixPB1_PIF_LANE3_OVRD2 0x210001b 966 #define ixPB1_PIF_LANE4_OVRD 0x210001c 967 #define ixPB1_PIF_LANE4_OVRD2 0x210001d 968 #define ixPB1_PIF_LANE5_OVRD 0x210001e 969 #define ixPB1_PIF_LANE5_OVRD2 0x210001f 970 #define ixPB1_PIF_LANE6_OVRD 0x2100020 971 #define ixPB1_PIF_LANE6_OVRD2 0x2100021 972 #define ixPB1_PIF_LANE7_OVRD 0x2100022 973 #define ixPB1_PIF_LANE7_OVRD2 0x2100023 974 #define ixPCIEP_RESERVED 0x10010000 975 #define ixPCIEP_SCRATCH 0x10010001 976 #define ixPCIEP_HW_DEBUG 0x10010002 977 #define ixPCIEP_PORT_CNTL 0x10010010 978 #define ixPCIE_TX_CNTL 0x10010020 979 #define ixPCIE_TX_REQUESTER_ID 0x10010021 980 #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 981 #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 982 #define ixPCIE_TX_SEQ 0x10010024 983 #define ixPCIE_TX_REPLAY 0x10010025 984 #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 985 #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 986 #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 987 #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 988 #define ixPCIE_TX_CREDITS_INIT_P 0x10010033 989 #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 990 #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 991 #define ixPCIE_TX_CREDITS_STATUS 0x10010036 992 #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 993 #define ixPCIE_P_PORT_LANE_STATUS 0x10010050 994 #define ixPCIE_FC_P 0x10010060 995 #define ixPCIE_FC_NP 0x10010061 996 #define ixPCIE_FC_CPL 0x10010062 997 #define ixPCIE_ERR_CNTL 0x1001006a 998 #define ixPCIE_RX_CNTL 0x10010070 999 #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 1000 #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 1001 #define ixPCIE_RX_CNTL3 0x10010074 1002 #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 1003 #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 1004 #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 1005 #define ixPCIEP_ERROR_INJECT_PHYSICAL 0x10010083 1006 #define ixPCIEP_ERROR_INJECT_TRANSACTION 0x10010084 1007 #define ixPCIEP_SRIOV_PRIV_CTRL 0x10010085 1008 #define ixPCIE_LC_CNTL 0x100100a0 1009 #define ixPCIE_LC_CNTL2 0x100100b1 1010 #define ixPCIE_LC_CNTL3 0x100100b5 1011 #define ixPCIE_LC_CNTL4 0x100100b6 1012 #define ixPCIE_LC_CNTL5 0x100100b7 1013 #define ixPCIE_LC_CNTL6 0x100100bb 1014 #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 1015 #define ixPCIE_LC_TRAINING_CNTL 0x100100a1 1016 #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 1017 #define ixPCIE_LC_N_FTS_CNTL 0x100100a3 1018 #define ixPCIE_LC_SPEED_CNTL 0x100100a4 1019 #define ixPCIE_LC_CDR_CNTL 0x100100b3 1020 #define ixPCIE_LC_LANE_CNTL 0x100100b4 1021 #define ixPCIE_LC_FORCE_COEFF 0x100100b8 1022 #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 1023 #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba 1024 #define ixPCIE_LC_STATE0 0x100100a5 1025 #define ixPCIE_LC_STATE1 0x100100a6 1026 #define ixPCIE_LC_STATE2 0x100100a7 1027 #define ixPCIE_LC_STATE3 0x100100a8 1028 #define ixPCIE_LC_STATE4 0x100100a9 1029 #define ixPCIE_LC_STATE5 0x100100aa 1030 #define ixPCIEP_STRAP_LC 0x100100c0 1031 #define ixPCIEP_STRAP_MISC 0x100100c1 1032 #define ixPCIEP_BCH_ECC_CNTL 0x100100d0 1033 #define ixPCIEP_HPGI_PRIVATE 0x100100d2 1034 #define ixPCIEP_HPGI 0x100100da 1035 #define mmPCIEMSIX_VECT0_ADDR_LO 0x6000 1036 #define mmPCIEMSIX_VECT0_ADDR_HI 0x6001 1037 #define mmPCIEMSIX_VECT0_MSG_DATA 0x6002 1038 #define mmPCIEMSIX_VECT0_CONTROL 0x6003 1039 #define mmPCIEMSIX_VECT1_ADDR_LO 0x6004 1040 #define mmPCIEMSIX_VECT1_ADDR_HI 0x6005 1041 #define mmPCIEMSIX_VECT1_MSG_DATA 0x6006 1042 #define mmPCIEMSIX_VECT1_CONTROL 0x6007 1043 #define mmPCIEMSIX_VECT2_ADDR_LO 0x6008 1044 #define mmPCIEMSIX_VECT2_ADDR_HI 0x6009 1045 #define mmPCIEMSIX_VECT2_MSG_DATA 0x600a 1046 #define mmPCIEMSIX_VECT2_CONTROL 0x600b 1047 #define mmPCIEMSIX_VECT3_ADDR_LO 0x600c 1048 #define mmPCIEMSIX_VECT3_ADDR_HI 0x600d 1049 #define mmPCIEMSIX_VECT3_MSG_DATA 0x600e 1050 #define mmPCIEMSIX_VECT3_CONTROL 0x600f 1051 #define mmPCIEMSIX_PBA 0x6200 1052 #define mmBIF_RFE_SNOOP_REG 0x27 1053 #define mmBIF_RFE_WARMRST_CNTL 0x1459 1054 #define mmBIF_RFE_SOFTRST_CNTL 0x1441 1055 #define mmBIF_RFE_IMPRST_CNTL 0x1458 1056 #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 1057 #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 1058 #define mmBIF_PWDN_COMMAND 0x1444 1059 #define mmBIF_PWDN_STATUS 0x1445 1060 #define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446 1061 #define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447 1062 #define mmBIF_RFE_MST_SMBUS_CMDSTATUS 0x1448 1063 #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1449 1064 #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b 1065 #define mmBIF_RFE_MMCFG_CNTL 0x144c 1066 #define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455 1067 #define mmBIF_IMPCTL_SMPLCNTL 0x1450 1068 #define mmBIF_IMPCTL_RXCNTL 0x1451 1069 #define mmBIF_IMPCTL_TXCNTL_pd 0x1452 1070 #define mmBIF_IMPCTL_TXCNTL_pu 0x1453 1071 #define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454 1072 1073 #endif /* BIF_5_0_D_H */ 1074
Indexes created Mon Sep 29 03:10:08 GMT 2025