1 /* $NetBSD: smuio_11_0_0_offset.h,v 1.2 2021/12/18 23:45:23 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _smuio_11_0_0_OFFSET_HEADER 24 #define _smuio_11_0_0_OFFSET_HEADER 25 26 27 28 // addressBlock: smuio_smuio_SmuSmuioDec 29 // base address: 0x5a000 30 #define mmSMUSVI0_TEL_PLANE0 0x0004 31 #define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0 32 #define mmSMUIO_MCM_CONFIG 0x0024 33 #define mmSMUIO_MCM_CONFIG_BASE_IDX 0 34 #define mmCKSVII2C_IC_CON 0x0040 35 #define mmCKSVII2C_IC_CON_BASE_IDX 0 36 #define mmCKSVII2C_IC_TAR 0x0041 37 #define mmCKSVII2C_IC_TAR_BASE_IDX 0 38 #define mmCKSVII2C_IC_SAR 0x0042 39 #define mmCKSVII2C_IC_SAR_BASE_IDX 0 40 #define mmCKSVII2C_IC_HS_MADDR 0x0043 41 #define mmCKSVII2C_IC_HS_MADDR_BASE_IDX 0 42 #define mmCKSVII2C_IC_DATA_CMD 0x0044 43 #define mmCKSVII2C_IC_DATA_CMD_BASE_IDX 0 44 #define mmCKSVII2C_IC_SS_SCL_HCNT 0x0045 45 #define mmCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0 46 #define mmCKSVII2C_IC_SS_SCL_LCNT 0x0046 47 #define mmCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0 48 #define mmCKSVII2C_IC_FS_SCL_HCNT 0x0047 49 #define mmCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0 50 #define mmCKSVII2C_IC_FS_SCL_LCNT 0x0048 51 #define mmCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0 52 #define mmCKSVII2C_IC_HS_SCL_HCNT 0x0049 53 #define mmCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0 54 #define mmCKSVII2C_IC_HS_SCL_LCNT 0x004a 55 #define mmCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0 56 #define mmCKSVII2C_IC_INTR_STAT 0x004b 57 #define mmCKSVII2C_IC_INTR_STAT_BASE_IDX 0 58 #define mmCKSVII2C_IC_INTR_MASK 0x004c 59 #define mmCKSVII2C_IC_INTR_MASK_BASE_IDX 0 60 #define mmCKSVII2C_IC_RAW_INTR_STAT 0x004d 61 #define mmCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0 62 #define mmCKSVII2C_IC_RX_TL 0x004e 63 #define mmCKSVII2C_IC_RX_TL_BASE_IDX 0 64 #define mmCKSVII2C_IC_TX_TL 0x004f 65 #define mmCKSVII2C_IC_TX_TL_BASE_IDX 0 66 #define mmCKSVII2C_IC_CLR_INTR 0x0050 67 #define mmCKSVII2C_IC_CLR_INTR_BASE_IDX 0 68 #define mmCKSVII2C_IC_CLR_RX_UNDER 0x0051 69 #define mmCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0 70 #define mmCKSVII2C_IC_CLR_RX_OVER 0x0052 71 #define mmCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0 72 #define mmCKSVII2C_IC_CLR_TX_OVER 0x0053 73 #define mmCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0 74 #define mmCKSVII2C_IC_CLR_RD_REQ 0x0054 75 #define mmCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0 76 #define mmCKSVII2C_IC_CLR_TX_ABRT 0x0055 77 #define mmCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0 78 #define mmCKSVII2C_IC_CLR_RX_DONE 0x0056 79 #define mmCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0 80 #define mmCKSVII2C_IC_CLR_ACTIVITY 0x0057 81 #define mmCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0 82 #define mmCKSVII2C_IC_CLR_STOP_DET 0x0058 83 #define mmCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0 84 #define mmCKSVII2C_IC_CLR_START_DET 0x0059 85 #define mmCKSVII2C_IC_CLR_START_DET_BASE_IDX 0 86 #define mmCKSVII2C_IC_CLR_GEN_CALL 0x005a 87 #define mmCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0 88 #define mmCKSVII2C_IC_ENABLE 0x005b 89 #define mmCKSVII2C_IC_ENABLE_BASE_IDX 0 90 #define mmCKSVII2C_IC_STATUS 0x005c 91 #define mmCKSVII2C_IC_STATUS_BASE_IDX 0 92 #define mmCKSVII2C_IC_TXFLR 0x005d 93 #define mmCKSVII2C_IC_TXFLR_BASE_IDX 0 94 #define mmCKSVII2C_IC_RXFLR 0x005e 95 #define mmCKSVII2C_IC_RXFLR_BASE_IDX 0 96 #define mmCKSVII2C_IC_SDA_HOLD 0x005f 97 #define mmCKSVII2C_IC_SDA_HOLD_BASE_IDX 0 98 #define mmCKSVII2C_IC_TX_ABRT_SOURCE 0x0060 99 #define mmCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0 100 #define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061 101 #define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 102 #define mmCKSVII2C_IC_DMA_CR 0x0062 103 #define mmCKSVII2C_IC_DMA_CR_BASE_IDX 0 104 #define mmCKSVII2C_IC_DMA_TDLR 0x0063 105 #define mmCKSVII2C_IC_DMA_TDLR_BASE_IDX 0 106 #define mmCKSVII2C_IC_DMA_RDLR 0x0064 107 #define mmCKSVII2C_IC_DMA_RDLR_BASE_IDX 0 108 #define mmCKSVII2C_IC_SDA_SETUP 0x0065 109 #define mmCKSVII2C_IC_SDA_SETUP_BASE_IDX 0 110 #define mmCKSVII2C_IC_ACK_GENERAL_CALL 0x0066 111 #define mmCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0 112 #define mmCKSVII2C_IC_ENABLE_STATUS 0x0067 113 #define mmCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0 114 #define mmCKSVII2C_IC_FS_SPKLEN 0x0068 115 #define mmCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0 116 #define mmCKSVII2C_IC_HS_SPKLEN 0x0069 117 #define mmCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0 118 #define mmCKSVII2C_IC_CLR_RESTART_DET 0x006a 119 #define mmCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0 120 #define mmCKSVII2C_IC_COMP_PARAM_1 0x006b 121 #define mmCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0 122 #define mmCKSVII2C_IC_COMP_VERSION 0x006c 123 #define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX 0 124 #define mmCKSVII2C_IC_COMP_TYPE 0x006d 125 #define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX 0 126 #define mmCKSVII2C1_IC_CON 0x0080 127 #define mmCKSVII2C1_IC_CON_BASE_IDX 0 128 #define mmCKSVII2C1_IC_TAR 0x0081 129 #define mmCKSVII2C1_IC_TAR_BASE_IDX 0 130 #define mmCKSVII2C1_IC_SAR 0x0082 131 #define mmCKSVII2C1_IC_SAR_BASE_IDX 0 132 #define mmCKSVII2C1_IC_HS_MADDR 0x0083 133 #define mmCKSVII2C1_IC_HS_MADDR_BASE_IDX 0 134 #define mmCKSVII2C1_IC_DATA_CMD 0x0084 135 #define mmCKSVII2C1_IC_DATA_CMD_BASE_IDX 0 136 #define mmCKSVII2C1_IC_SS_SCL_HCNT 0x0085 137 #define mmCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0 138 #define mmCKSVII2C1_IC_SS_SCL_LCNT 0x0086 139 #define mmCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0 140 #define mmCKSVII2C1_IC_FS_SCL_HCNT 0x0087 141 #define mmCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0 142 #define mmCKSVII2C1_IC_FS_SCL_LCNT 0x0088 143 #define mmCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0 144 #define mmCKSVII2C1_IC_HS_SCL_HCNT 0x0089 145 #define mmCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0 146 #define mmCKSVII2C1_IC_HS_SCL_LCNT 0x008a 147 #define mmCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0 148 #define mmCKSVII2C1_IC_INTR_STAT 0x008b 149 #define mmCKSVII2C1_IC_INTR_STAT_BASE_IDX 0 150 #define mmCKSVII2C1_IC_INTR_MASK 0x008c 151 #define mmCKSVII2C1_IC_INTR_MASK_BASE_IDX 0 152 #define mmCKSVII2C1_IC_RAW_INTR_STAT 0x008d 153 #define mmCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0 154 #define mmCKSVII2C1_IC_RX_TL 0x008e 155 #define mmCKSVII2C1_IC_RX_TL_BASE_IDX 0 156 #define mmCKSVII2C1_IC_TX_TL 0x008f 157 #define mmCKSVII2C1_IC_TX_TL_BASE_IDX 0 158 #define mmCKSVII2C1_IC_CLR_INTR 0x0090 159 #define mmCKSVII2C1_IC_CLR_INTR_BASE_IDX 0 160 #define mmCKSVII2C1_IC_CLR_RX_UNDER 0x0091 161 #define mmCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0 162 #define mmCKSVII2C1_IC_CLR_RX_OVER 0x0092 163 #define mmCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0 164 #define mmCKSVII2C1_IC_CLR_TX_OVER 0x0093 165 #define mmCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0 166 #define mmCKSVII2C1_IC_CLR_RD_REQ 0x0094 167 #define mmCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0 168 #define mmCKSVII2C1_IC_CLR_TX_ABRT 0x0095 169 #define mmCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0 170 #define mmCKSVII2C1_IC_CLR_RX_DONE 0x0096 171 #define mmCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0 172 #define mmCKSVII2C1_IC_CLR_ACTIVITY 0x0097 173 #define mmCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0 174 #define mmCKSVII2C1_IC_CLR_STOP_DET 0x0098 175 #define mmCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0 176 #define mmCKSVII2C1_IC_CLR_START_DET 0x0099 177 #define mmCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0 178 #define mmCKSVII2C1_IC_CLR_GEN_CALL 0x009a 179 #define mmCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0 180 #define mmCKSVII2C1_IC_ENABLE 0x009b 181 #define mmCKSVII2C1_IC_ENABLE_BASE_IDX 0 182 #define mmCKSVII2C1_IC_STATUS 0x009c 183 #define mmCKSVII2C1_IC_STATUS_BASE_IDX 0 184 #define mmCKSVII2C1_IC_TXFLR 0x009d 185 #define mmCKSVII2C1_IC_TXFLR_BASE_IDX 0 186 #define mmCKSVII2C1_IC_RXFLR 0x009e 187 #define mmCKSVII2C1_IC_RXFLR_BASE_IDX 0 188 #define mmCKSVII2C1_IC_SDA_HOLD 0x009f 189 #define mmCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0 190 #define mmCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0 191 #define mmCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0 192 #define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1 193 #define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 194 #define mmCKSVII2C1_IC_DMA_CR 0x00a2 195 #define mmCKSVII2C1_IC_DMA_CR_BASE_IDX 0 196 #define mmCKSVII2C1_IC_DMA_TDLR 0x00a3 197 #define mmCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0 198 #define mmCKSVII2C1_IC_DMA_RDLR 0x00a4 199 #define mmCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0 200 #define mmCKSVII2C1_IC_SDA_SETUP 0x00a5 201 #define mmCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0 202 #define mmCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6 203 #define mmCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0 204 #define mmCKSVII2C1_IC_ENABLE_STATUS 0x00a7 205 #define mmCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0 206 #define mmCKSVII2C1_IC_FS_SPKLEN 0x00a8 207 #define mmCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0 208 #define mmCKSVII2C1_IC_HS_SPKLEN 0x00a9 209 #define mmCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0 210 #define mmCKSVII2C1_IC_CLR_RESTART_DET 0x00aa 211 #define mmCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0 212 #define mmCKSVII2C1_IC_COMP_PARAM_1 0x00ab 213 #define mmCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0 214 #define mmCKSVII2C1_IC_COMP_VERSION 0x00ac 215 #define mmCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0 216 #define mmCKSVII2C1_IC_COMP_TYPE 0x00ad 217 #define mmCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0 218 #define mmSMUIO_MP_RESET_INTR 0x00c1 219 #define mmSMUIO_MP_RESET_INTR_BASE_IDX 0 220 #define mmSMUIO_SOC_HALT 0x00c2 221 #define mmSMUIO_SOC_HALT_BASE_IDX 0 222 #define mmSMUIO_PWRMGT 0x00c8 223 #define mmSMUIO_PWRMGT_BASE_IDX 0 224 #define mmROM_CNTL 0x00e0 225 #define mmROM_CNTL_BASE_IDX 0 226 #define mmPAGE_MIRROR_CNTL 0x00e1 227 #define mmPAGE_MIRROR_CNTL_BASE_IDX 0 228 #define mmROM_STATUS 0x00e2 229 #define mmROM_STATUS_BASE_IDX 0 230 #define mmCGTT_ROM_CLK_CTRL0 0x00e3 231 #define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0 232 #define mmROM_INDEX 0x00e4 233 #define mmROM_INDEX_BASE_IDX 0 234 #define mmROM_DATA 0x00e5 235 #define mmROM_DATA_BASE_IDX 0 236 #define mmROM_START 0x00e6 237 #define mmROM_START_BASE_IDX 0 238 #define mmROM_SW_CNTL 0x00e7 239 #define mmROM_SW_CNTL_BASE_IDX 0 240 #define mmROM_SW_STATUS 0x00e8 241 #define mmROM_SW_STATUS_BASE_IDX 0 242 #define mmROM_SW_COMMAND 0x00e9 243 #define mmROM_SW_COMMAND_BASE_IDX 0 244 #define mmROM_SW_DATA_1 0x00ea 245 #define mmROM_SW_DATA_1_BASE_IDX 0 246 #define mmROM_SW_DATA_2 0x00eb 247 #define mmROM_SW_DATA_2_BASE_IDX 0 248 #define mmROM_SW_DATA_3 0x00ec 249 #define mmROM_SW_DATA_3_BASE_IDX 0 250 #define mmROM_SW_DATA_4 0x00ed 251 #define mmROM_SW_DATA_4_BASE_IDX 0 252 #define mmROM_SW_DATA_5 0x00ee 253 #define mmROM_SW_DATA_5_BASE_IDX 0 254 #define mmROM_SW_DATA_6 0x00ef 255 #define mmROM_SW_DATA_6_BASE_IDX 0 256 #define mmROM_SW_DATA_7 0x00f0 257 #define mmROM_SW_DATA_7_BASE_IDX 0 258 #define mmROM_SW_DATA_8 0x00f1 259 #define mmROM_SW_DATA_8_BASE_IDX 0 260 #define mmROM_SW_DATA_9 0x00f2 261 #define mmROM_SW_DATA_9_BASE_IDX 0 262 #define mmROM_SW_DATA_10 0x00f3 263 #define mmROM_SW_DATA_10_BASE_IDX 0 264 #define mmROM_SW_DATA_11 0x00f4 265 #define mmROM_SW_DATA_11_BASE_IDX 0 266 #define mmROM_SW_DATA_12 0x00f5 267 #define mmROM_SW_DATA_12_BASE_IDX 0 268 #define mmROM_SW_DATA_13 0x00f6 269 #define mmROM_SW_DATA_13_BASE_IDX 0 270 #define mmROM_SW_DATA_14 0x00f7 271 #define mmROM_SW_DATA_14_BASE_IDX 0 272 #define mmROM_SW_DATA_15 0x00f8 273 #define mmROM_SW_DATA_15_BASE_IDX 0 274 #define mmROM_SW_DATA_16 0x00f9 275 #define mmROM_SW_DATA_16_BASE_IDX 0 276 #define mmROM_SW_DATA_17 0x00fa 277 #define mmROM_SW_DATA_17_BASE_IDX 0 278 #define mmROM_SW_DATA_18 0x00fb 279 #define mmROM_SW_DATA_18_BASE_IDX 0 280 #define mmROM_SW_DATA_19 0x00fc 281 #define mmROM_SW_DATA_19_BASE_IDX 0 282 #define mmROM_SW_DATA_20 0x00fd 283 #define mmROM_SW_DATA_20_BASE_IDX 0 284 #define mmROM_SW_DATA_21 0x00fe 285 #define mmROM_SW_DATA_21_BASE_IDX 0 286 #define mmROM_SW_DATA_22 0x00ff 287 #define mmROM_SW_DATA_22_BASE_IDX 0 288 #define mmROM_SW_DATA_23 0x0100 289 #define mmROM_SW_DATA_23_BASE_IDX 0 290 #define mmROM_SW_DATA_24 0x0101 291 #define mmROM_SW_DATA_24_BASE_IDX 0 292 #define mmROM_SW_DATA_25 0x0102 293 #define mmROM_SW_DATA_25_BASE_IDX 0 294 #define mmROM_SW_DATA_26 0x0103 295 #define mmROM_SW_DATA_26_BASE_IDX 0 296 #define mmROM_SW_DATA_27 0x0104 297 #define mmROM_SW_DATA_27_BASE_IDX 0 298 #define mmROM_SW_DATA_28 0x0105 299 #define mmROM_SW_DATA_28_BASE_IDX 0 300 #define mmROM_SW_DATA_29 0x0106 301 #define mmROM_SW_DATA_29_BASE_IDX 0 302 #define mmROM_SW_DATA_30 0x0107 303 #define mmROM_SW_DATA_30_BASE_IDX 0 304 #define mmROM_SW_DATA_31 0x0108 305 #define mmROM_SW_DATA_31_BASE_IDX 0 306 #define mmROM_SW_DATA_32 0x0109 307 #define mmROM_SW_DATA_32_BASE_IDX 0 308 #define mmROM_SW_DATA_33 0x010a 309 #define mmROM_SW_DATA_33_BASE_IDX 0 310 #define mmROM_SW_DATA_34 0x010b 311 #define mmROM_SW_DATA_34_BASE_IDX 0 312 #define mmROM_SW_DATA_35 0x010c 313 #define mmROM_SW_DATA_35_BASE_IDX 0 314 #define mmROM_SW_DATA_36 0x010d 315 #define mmROM_SW_DATA_36_BASE_IDX 0 316 #define mmROM_SW_DATA_37 0x010e 317 #define mmROM_SW_DATA_37_BASE_IDX 0 318 #define mmROM_SW_DATA_38 0x010f 319 #define mmROM_SW_DATA_38_BASE_IDX 0 320 #define mmROM_SW_DATA_39 0x0110 321 #define mmROM_SW_DATA_39_BASE_IDX 0 322 #define mmROM_SW_DATA_40 0x0111 323 #define mmROM_SW_DATA_40_BASE_IDX 0 324 #define mmROM_SW_DATA_41 0x0112 325 #define mmROM_SW_DATA_41_BASE_IDX 0 326 #define mmROM_SW_DATA_42 0x0113 327 #define mmROM_SW_DATA_42_BASE_IDX 0 328 #define mmROM_SW_DATA_43 0x0114 329 #define mmROM_SW_DATA_43_BASE_IDX 0 330 #define mmROM_SW_DATA_44 0x0115 331 #define mmROM_SW_DATA_44_BASE_IDX 0 332 #define mmROM_SW_DATA_45 0x0116 333 #define mmROM_SW_DATA_45_BASE_IDX 0 334 #define mmROM_SW_DATA_46 0x0117 335 #define mmROM_SW_DATA_46_BASE_IDX 0 336 #define mmROM_SW_DATA_47 0x0118 337 #define mmROM_SW_DATA_47_BASE_IDX 0 338 #define mmROM_SW_DATA_48 0x0119 339 #define mmROM_SW_DATA_48_BASE_IDX 0 340 #define mmROM_SW_DATA_49 0x011a 341 #define mmROM_SW_DATA_49_BASE_IDX 0 342 #define mmROM_SW_DATA_50 0x011b 343 #define mmROM_SW_DATA_50_BASE_IDX 0 344 #define mmROM_SW_DATA_51 0x011c 345 #define mmROM_SW_DATA_51_BASE_IDX 0 346 #define mmROM_SW_DATA_52 0x011d 347 #define mmROM_SW_DATA_52_BASE_IDX 0 348 #define mmROM_SW_DATA_53 0x011e 349 #define mmROM_SW_DATA_53_BASE_IDX 0 350 #define mmROM_SW_DATA_54 0x011f 351 #define mmROM_SW_DATA_54_BASE_IDX 0 352 #define mmROM_SW_DATA_55 0x0120 353 #define mmROM_SW_DATA_55_BASE_IDX 0 354 #define mmROM_SW_DATA_56 0x0121 355 #define mmROM_SW_DATA_56_BASE_IDX 0 356 #define mmROM_SW_DATA_57 0x0122 357 #define mmROM_SW_DATA_57_BASE_IDX 0 358 #define mmROM_SW_DATA_58 0x0123 359 #define mmROM_SW_DATA_58_BASE_IDX 0 360 #define mmROM_SW_DATA_59 0x0124 361 #define mmROM_SW_DATA_59_BASE_IDX 0 362 #define mmROM_SW_DATA_60 0x0125 363 #define mmROM_SW_DATA_60_BASE_IDX 0 364 #define mmROM_SW_DATA_61 0x0126 365 #define mmROM_SW_DATA_61_BASE_IDX 0 366 #define mmROM_SW_DATA_62 0x0127 367 #define mmROM_SW_DATA_62_BASE_IDX 0 368 #define mmROM_SW_DATA_63 0x0128 369 #define mmROM_SW_DATA_63_BASE_IDX 0 370 #define mmROM_SW_DATA_64 0x0129 371 #define mmROM_SW_DATA_64_BASE_IDX 0 372 #define mmSMU_GPIOPAD_SW_INT_STAT 0x0140 373 #define mmSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0 374 #define mmSMU_GPIOPAD_MASK 0x0141 375 #define mmSMU_GPIOPAD_MASK_BASE_IDX 0 376 #define mmSMU_GPIOPAD_A 0x0142 377 #define mmSMU_GPIOPAD_A_BASE_IDX 0 378 #define mmSMU_GPIOPAD_TXIMPSEL 0x0143 379 #define mmSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0 380 #define mmSMU_GPIOPAD_EN 0x0144 381 #define mmSMU_GPIOPAD_EN_BASE_IDX 0 382 #define mmSMU_GPIOPAD_Y 0x0145 383 #define mmSMU_GPIOPAD_Y_BASE_IDX 0 384 #define mmSMU_GPIOPAD_RXEN 0x0146 385 #define mmSMU_GPIOPAD_RXEN_BASE_IDX 0 386 #define mmSMU_GPIOPAD_RCVR_SEL0 0x0147 387 #define mmSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0 388 #define mmSMU_GPIOPAD_RCVR_SEL1 0x0148 389 #define mmSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0 390 #define mmSMU_GPIOPAD_PU_EN 0x0149 391 #define mmSMU_GPIOPAD_PU_EN_BASE_IDX 0 392 #define mmSMU_GPIOPAD_PD_EN 0x014a 393 #define mmSMU_GPIOPAD_PD_EN_BASE_IDX 0 394 #define mmSMU_GPIOPAD_PINSTRAPS 0x014b 395 #define mmSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0 396 #define mmDFT_PINSTRAPS 0x014c 397 #define mmDFT_PINSTRAPS_BASE_IDX 0 398 #define mmSMU_GPIOPAD_INT_STAT_EN 0x014d 399 #define mmSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0 400 #define mmSMU_GPIOPAD_INT_STAT 0x014e 401 #define mmSMU_GPIOPAD_INT_STAT_BASE_IDX 0 402 #define mmSMU_GPIOPAD_INT_STAT_AK 0x014f 403 #define mmSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0 404 #define mmSMU_GPIOPAD_INT_EN 0x0150 405 #define mmSMU_GPIOPAD_INT_EN_BASE_IDX 0 406 #define mmSMU_GPIOPAD_INT_TYPE 0x0151 407 #define mmSMU_GPIOPAD_INT_TYPE_BASE_IDX 0 408 #define mmSMU_GPIOPAD_INT_POLARITY 0x0152 409 #define mmSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0 410 #define mmROM_CC_BIF_PINSTRAP 0x0153 411 #define mmROM_CC_BIF_PINSTRAP_BASE_IDX 0 412 #define mmIO_SMUIO_PINSTRAP 0x0154 413 #define mmIO_SMUIO_PINSTRAP_BASE_IDX 0 414 #define mmSMUIO_PCC_CONTROL 0x0155 415 #define mmSMUIO_PCC_CONTROL_BASE_IDX 0 416 #define mmSMUIO_PCC_GPIO_SELECT 0x0156 417 #define mmSMUIO_PCC_GPIO_SELECT_BASE_IDX 0 418 #define mmSMUIO_GPIO_INT0_SELECT 0x0157 419 #define mmSMUIO_GPIO_INT0_SELECT_BASE_IDX 0 420 #define mmSMUIO_GPIO_INT1_SELECT 0x0158 421 #define mmSMUIO_GPIO_INT1_SELECT_BASE_IDX 0 422 #define mmSMUIO_GPIO_INT2_SELECT 0x0159 423 #define mmSMUIO_GPIO_INT2_SELECT_BASE_IDX 0 424 #define mmSMUIO_GPIO_INT3_SELECT 0x015a 425 #define mmSMUIO_GPIO_INT3_SELECT_BASE_IDX 0 426 #define mmSMU_GPIOPAD_MP_INT0_STAT 0x015b 427 #define mmSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0 428 #define mmSMU_GPIOPAD_MP_INT1_STAT 0x015c 429 #define mmSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0 430 #define mmSMU_GPIOPAD_MP_INT2_STAT 0x015d 431 #define mmSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0 432 #define mmSMU_GPIOPAD_MP_INT3_STAT 0x015e 433 #define mmSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0 434 #define mmSMIO_INDEX 0x015f 435 #define mmSMIO_INDEX_BASE_IDX 0 436 #define mmS0_VID_SMIO_CNTL 0x0160 437 #define mmS0_VID_SMIO_CNTL_BASE_IDX 0 438 #define mmS1_VID_SMIO_CNTL 0x0161 439 #define mmS1_VID_SMIO_CNTL_BASE_IDX 0 440 #define mmOPEN_DRAIN_SELECT 0x0162 441 #define mmOPEN_DRAIN_SELECT_BASE_IDX 0 442 #define mmSMIO_ENABLE 0x0163 443 #define mmSMIO_ENABLE_BASE_IDX 0 444 #define mmSMU_GPIOPAD_S0 0x0166 445 #define mmSMU_GPIOPAD_S0_BASE_IDX 0 446 #define mmSMU_GPIOPAD_S1 0x0167 447 #define mmSMU_GPIOPAD_S1_BASE_IDX 0 448 #define mmSMU_GPIOPAD_SCL_EN 0x0168 449 #define mmSMU_GPIOPAD_SCL_EN_BASE_IDX 0 450 #define mmSMU_GPIOPAD_SDA_EN 0x0169 451 #define mmSMU_GPIOPAD_SDA_EN_BASE_IDX 0 452 #define mmSMU_GPIOPAD_SCHMEN 0x016a 453 #define mmSMU_GPIOPAD_SCHMEN_BASE_IDX 0 454 455 456 // addressBlock: smuio_smuio_pwr_SmuSmuioDec 457 // base address: 0x5a800 458 #define mmIP_DISCOVERY_VERSION 0x0000 459 #define mmIP_DISCOVERY_VERSION_BASE_IDX 1 460 #define mmSOC_GAP_PWROK 0x00f8 461 #define mmSOC_GAP_PWROK_BASE_IDX 1 462 #define mmGFX_GAP_PWROK 0x00f9 463 #define mmGFX_GAP_PWROK_BASE_IDX 1 464 #define mmPWROK_REFCLK_GAP_CYCLES 0x00fa 465 #define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 466 #define mmGOLDEN_TSC_INCREMENT_UPPER 0x0100 467 #define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 468 #define mmGOLDEN_TSC_INCREMENT_LOWER 0x0101 469 #define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 470 #define mmGOLDEN_TSC_COUNT_UPPER 0x0102 471 #define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 472 #define mmGOLDEN_TSC_COUNT_LOWER 0x0103 473 #define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 474 #define mmSOC_GOLDEN_TSC_SHADOW_UPPER 0x0104 475 #define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 476 #define mmSOC_GOLDEN_TSC_SHADOW_LOWER 0x0105 477 #define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 478 #define mmGFX_GOLDEN_TSC_SHADOW_UPPER 0x0106 479 #define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 480 #define mmGFX_GOLDEN_TSC_SHADOW_LOWER 0x0107 481 #define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 482 #define mmPWR_VIRT_RESET_REQ 0x0108 483 #define mmPWR_VIRT_RESET_REQ_BASE_IDX 1 484 #define mmSCRATCH_REGISTER0 0x0110 485 #define mmSCRATCH_REGISTER0_BASE_IDX 1 486 #define mmSCRATCH_REGISTER1 0x0111 487 #define mmSCRATCH_REGISTER1_BASE_IDX 1 488 #define mmSCRATCH_REGISTER2 0x0112 489 #define mmSCRATCH_REGISTER2_BASE_IDX 1 490 #define mmSCRATCH_REGISTER3 0x0113 491 #define mmSCRATCH_REGISTER3_BASE_IDX 1 492 #define mmSCRATCH_REGISTER4 0x0114 493 #define mmSCRATCH_REGISTER4_BASE_IDX 1 494 #define mmSCRATCH_REGISTER5 0x0115 495 #define mmSCRATCH_REGISTER5_BASE_IDX 1 496 #define mmSCRATCH_REGISTER6 0x0116 497 #define mmSCRATCH_REGISTER6_BASE_IDX 1 498 #define mmSCRATCH_REGISTER7 0x0117 499 #define mmSCRATCH_REGISTER7_BASE_IDX 1 500 #define mmPWR_DISP_TIMER_CONTROL 0x012c 501 #define mmPWR_DISP_TIMER_CONTROL_BASE_IDX 1 502 #define mmPWR_DISP_TIMER2_CONTROL 0x012e 503 #define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 504 #define mmPWR_DISP_TIMER_GLOBAL_CONTROL 0x0130 505 #define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 506 #define mmPWR_IH_CONTROL 0x0131 507 #define mmPWR_IH_CONTROL_BASE_IDX 1 508 509 #endif 510
Indexes created Mon Sep 29 03:10:08 GMT 2025