1 /* $NetBSD: dce_11_0_d.h,v 1.3 2021/12/18 23:45:09 riastradh Exp $ */ 2 3 /* 4 * DCE_11_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef DCE_11_0_D_H 27 #define DCE_11_0_D_H 28 29 #define mmPIPE0_PG_CONFIG 0x2c0 30 #define mmPIPE0_PG_ENABLE 0x2c1 31 #define mmPIPE0_PG_STATUS 0x2c2 32 #define mmPIPE1_PG_CONFIG 0x2c3 33 #define mmPIPE1_PG_ENABLE 0x2c4 34 #define mmPIPE1_PG_STATUS 0x2c5 35 #define mmPIPE2_PG_CONFIG 0x2c6 36 #define mmPIPE2_PG_ENABLE 0x2c7 37 #define mmPIPE2_PG_STATUS 0x2c8 38 #define mmDCFEV0_PG_CONFIG 0x2db 39 #define mmDCFEV0_PG_ENABLE 0x2dc 40 #define mmDCFEV0_PG_STATUS 0x2dd 41 #define mmDCPG_INTERRUPT_STATUS 0x2de 42 #define mmDCPG_INTERRUPT_CONTROL 0x2df 43 #define mmDC_IP_REQUEST_CNTL 0x2d2 44 #define mmDC_PGFSM_CONFIG_REG 0x2d3 45 #define mmDC_PGFSM_WRITE_REG 0x2d4 46 #define mmDC_PGCNTL_STATUS_REG 0x2d5 47 #define mmDCPG_TEST_DEBUG_INDEX 0x2d6 48 #define mmDCPG_TEST_DEBUG_DATA 0x2d7 49 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 50 #define mmBL1_PWM_USER_LEVEL 0x1629 51 #define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a 52 #define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b 53 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c 54 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d 55 #define mmBL1_PWM_ABM_CNTL 0x162e 56 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f 57 #define mmBL1_PWM_GRP2_REG_LOCK 0x1630 58 #define mmDC_ABM1_CNTL 0x1638 59 #define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 60 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a 61 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b 62 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c 63 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d 64 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e 65 #define mmDC_ABM1_ACE_THRES_12 0x163f 66 #define mmDC_ABM1_ACE_THRES_34 0x1640 67 #define mmDC_ABM1_ACE_CNTL_MISC 0x1641 68 #define mmDC_ABM1_DEBUG_MISC 0x1649 69 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a 70 #define mmDC_ABM1_HG_MISC_CTRL 0x164b 71 #define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c 72 #define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d 73 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e 74 #define mmDC_ABM1_LS_PIXEL_COUNT 0x164f 75 #define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 76 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 77 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 78 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 79 #define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 80 #define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 81 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 82 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 83 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 84 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 85 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a 86 #define mmDC_ABM1_HG_RESULT_1 0x165b 87 #define mmDC_ABM1_HG_RESULT_2 0x165c 88 #define mmDC_ABM1_HG_RESULT_3 0x165d 89 #define mmDC_ABM1_HG_RESULT_4 0x165e 90 #define mmDC_ABM1_HG_RESULT_5 0x165f 91 #define mmDC_ABM1_HG_RESULT_6 0x1660 92 #define mmDC_ABM1_HG_RESULT_7 0x1661 93 #define mmDC_ABM1_HG_RESULT_8 0x1662 94 #define mmDC_ABM1_HG_RESULT_9 0x1663 95 #define mmDC_ABM1_HG_RESULT_10 0x1664 96 #define mmDC_ABM1_HG_RESULT_11 0x1665 97 #define mmDC_ABM1_HG_RESULT_12 0x1666 98 #define mmDC_ABM1_HG_RESULT_13 0x1667 99 #define mmDC_ABM1_HG_RESULT_14 0x1668 100 #define mmDC_ABM1_HG_RESULT_15 0x1669 101 #define mmDC_ABM1_HG_RESULT_16 0x166a 102 #define mmDC_ABM1_HG_RESULT_17 0x166b 103 #define mmDC_ABM1_HG_RESULT_18 0x166c 104 #define mmDC_ABM1_HG_RESULT_19 0x166d 105 #define mmDC_ABM1_HG_RESULT_20 0x166e 106 #define mmDC_ABM1_HG_RESULT_21 0x166f 107 #define mmDC_ABM1_HG_RESULT_22 0x1670 108 #define mmDC_ABM1_HG_RESULT_23 0x1671 109 #define mmDC_ABM1_HG_RESULT_24 0x1672 110 #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b 111 #define mmDC_ABM1_BL_MASTER_LOCK 0x169c 112 #define mmABM_TEST_DEBUG_INDEX 0x169e 113 #define mmABM_TEST_DEBUG_DATA 0x169f 114 #define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d 115 #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d 116 #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d 117 #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d 118 #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d 119 #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d 120 #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d 121 #define mmCRTC_H_TOTAL 0x1b80 122 #define mmCRTC0_CRTC_H_TOTAL 0x1b80 123 #define mmCRTC1_CRTC_H_TOTAL 0x1d80 124 #define mmCRTC2_CRTC_H_TOTAL 0x1f80 125 #define mmCRTC3_CRTC_H_TOTAL 0x4180 126 #define mmCRTC4_CRTC_H_TOTAL 0x4380 127 #define mmCRTC5_CRTC_H_TOTAL 0x4580 128 #define mmCRTC_H_BLANK_START_END 0x1b81 129 #define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 130 #define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 131 #define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 132 #define mmCRTC3_CRTC_H_BLANK_START_END 0x4181 133 #define mmCRTC4_CRTC_H_BLANK_START_END 0x4381 134 #define mmCRTC5_CRTC_H_BLANK_START_END 0x4581 135 #define mmCRTC_H_SYNC_A 0x1b82 136 #define mmCRTC0_CRTC_H_SYNC_A 0x1b82 137 #define mmCRTC1_CRTC_H_SYNC_A 0x1d82 138 #define mmCRTC2_CRTC_H_SYNC_A 0x1f82 139 #define mmCRTC3_CRTC_H_SYNC_A 0x4182 140 #define mmCRTC4_CRTC_H_SYNC_A 0x4382 141 #define mmCRTC5_CRTC_H_SYNC_A 0x4582 142 #define mmCRTC_H_SYNC_A_CNTL 0x1b83 143 #define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 144 #define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 145 #define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 146 #define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 147 #define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 148 #define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 149 #define mmCRTC_H_SYNC_B 0x1b84 150 #define mmCRTC0_CRTC_H_SYNC_B 0x1b84 151 #define mmCRTC1_CRTC_H_SYNC_B 0x1d84 152 #define mmCRTC2_CRTC_H_SYNC_B 0x1f84 153 #define mmCRTC3_CRTC_H_SYNC_B 0x4184 154 #define mmCRTC4_CRTC_H_SYNC_B 0x4384 155 #define mmCRTC5_CRTC_H_SYNC_B 0x4584 156 #define mmCRTC_H_SYNC_B_CNTL 0x1b85 157 #define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 158 #define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 159 #define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 160 #define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 161 #define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 162 #define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 163 #define mmCRTC_VBI_END 0x1b86 164 #define mmCRTC0_CRTC_VBI_END 0x1b86 165 #define mmCRTC1_CRTC_VBI_END 0x1d86 166 #define mmCRTC2_CRTC_VBI_END 0x1f86 167 #define mmCRTC3_CRTC_VBI_END 0x4186 168 #define mmCRTC4_CRTC_VBI_END 0x4386 169 #define mmCRTC5_CRTC_VBI_END 0x4586 170 #define mmCRTC_V_TOTAL 0x1b87 171 #define mmCRTC0_CRTC_V_TOTAL 0x1b87 172 #define mmCRTC1_CRTC_V_TOTAL 0x1d87 173 #define mmCRTC2_CRTC_V_TOTAL 0x1f87 174 #define mmCRTC3_CRTC_V_TOTAL 0x4187 175 #define mmCRTC4_CRTC_V_TOTAL 0x4387 176 #define mmCRTC5_CRTC_V_TOTAL 0x4587 177 #define mmCRTC_V_TOTAL_MIN 0x1b88 178 #define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 179 #define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 180 #define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 181 #define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 182 #define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 183 #define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 184 #define mmCRTC_V_TOTAL_MAX 0x1b89 185 #define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 186 #define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 187 #define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 188 #define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 189 #define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 190 #define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 191 #define mmCRTC_V_TOTAL_CONTROL 0x1b8a 192 #define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a 193 #define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a 194 #define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a 195 #define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a 196 #define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a 197 #define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a 198 #define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b 199 #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b 200 #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b 201 #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b 202 #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b 203 #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b 204 #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b 205 #define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c 206 #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c 207 #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c 208 #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c 209 #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c 210 #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c 211 #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c 212 #define mmCRTC_V_BLANK_START_END 0x1b8d 213 #define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d 214 #define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d 215 #define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d 216 #define mmCRTC3_CRTC_V_BLANK_START_END 0x418d 217 #define mmCRTC4_CRTC_V_BLANK_START_END 0x438d 218 #define mmCRTC5_CRTC_V_BLANK_START_END 0x458d 219 #define mmCRTC_V_SYNC_A 0x1b8e 220 #define mmCRTC0_CRTC_V_SYNC_A 0x1b8e 221 #define mmCRTC1_CRTC_V_SYNC_A 0x1d8e 222 #define mmCRTC2_CRTC_V_SYNC_A 0x1f8e 223 #define mmCRTC3_CRTC_V_SYNC_A 0x418e 224 #define mmCRTC4_CRTC_V_SYNC_A 0x438e 225 #define mmCRTC5_CRTC_V_SYNC_A 0x458e 226 #define mmCRTC_V_SYNC_A_CNTL 0x1b8f 227 #define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f 228 #define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f 229 #define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f 230 #define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f 231 #define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f 232 #define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f 233 #define mmCRTC_V_SYNC_B 0x1b90 234 #define mmCRTC0_CRTC_V_SYNC_B 0x1b90 235 #define mmCRTC1_CRTC_V_SYNC_B 0x1d90 236 #define mmCRTC2_CRTC_V_SYNC_B 0x1f90 237 #define mmCRTC3_CRTC_V_SYNC_B 0x4190 238 #define mmCRTC4_CRTC_V_SYNC_B 0x4390 239 #define mmCRTC5_CRTC_V_SYNC_B 0x4590 240 #define mmCRTC_V_SYNC_B_CNTL 0x1b91 241 #define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 242 #define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 243 #define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 244 #define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 245 #define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 246 #define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 247 #define mmCRTC_DTMTEST_CNTL 0x1b92 248 #define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 249 #define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 250 #define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 251 #define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 252 #define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 253 #define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 254 #define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 255 #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 256 #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 257 #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 258 #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 259 #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 260 #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 261 #define mmCRTC_TRIGA_CNTL 0x1b94 262 #define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 263 #define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 264 #define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 265 #define mmCRTC3_CRTC_TRIGA_CNTL 0x4194 266 #define mmCRTC4_CRTC_TRIGA_CNTL 0x4394 267 #define mmCRTC5_CRTC_TRIGA_CNTL 0x4594 268 #define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 269 #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 270 #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 271 #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 272 #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 273 #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 274 #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 275 #define mmCRTC_TRIGB_CNTL 0x1b96 276 #define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 277 #define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 278 #define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 279 #define mmCRTC3_CRTC_TRIGB_CNTL 0x4196 280 #define mmCRTC4_CRTC_TRIGB_CNTL 0x4396 281 #define mmCRTC5_CRTC_TRIGB_CNTL 0x4596 282 #define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 283 #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 284 #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 285 #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 286 #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 287 #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 288 #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 289 #define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 290 #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 291 #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 292 #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 293 #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 294 #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 295 #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 296 #define mmCRTC_FLOW_CONTROL 0x1b99 297 #define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 298 #define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 299 #define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 300 #define mmCRTC3_CRTC_FLOW_CONTROL 0x4199 301 #define mmCRTC4_CRTC_FLOW_CONTROL 0x4399 302 #define mmCRTC5_CRTC_FLOW_CONTROL 0x4599 303 #define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a 304 #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a 305 #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a 306 #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a 307 #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a 308 #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a 309 #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a 310 #define mmCRTC_AVSYNC_COUNTER 0x1b9b 311 #define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b 312 #define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b 313 #define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b 314 #define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b 315 #define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b 316 #define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b 317 #define mmCRTC_CONTROL 0x1b9c 318 #define mmCRTC0_CRTC_CONTROL 0x1b9c 319 #define mmCRTC1_CRTC_CONTROL 0x1d9c 320 #define mmCRTC2_CRTC_CONTROL 0x1f9c 321 #define mmCRTC3_CRTC_CONTROL 0x419c 322 #define mmCRTC4_CRTC_CONTROL 0x439c 323 #define mmCRTC5_CRTC_CONTROL 0x459c 324 #define mmCRTC_BLANK_CONTROL 0x1b9d 325 #define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d 326 #define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d 327 #define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d 328 #define mmCRTC3_CRTC_BLANK_CONTROL 0x419d 329 #define mmCRTC4_CRTC_BLANK_CONTROL 0x439d 330 #define mmCRTC5_CRTC_BLANK_CONTROL 0x459d 331 #define mmCRTC_INTERLACE_CONTROL 0x1b9e 332 #define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e 333 #define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e 334 #define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e 335 #define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e 336 #define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e 337 #define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e 338 #define mmCRTC_INTERLACE_STATUS 0x1b9f 339 #define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f 340 #define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f 341 #define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f 342 #define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f 343 #define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f 344 #define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f 345 #define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 346 #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 347 #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 348 #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 349 #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 350 #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 351 #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 352 #define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 353 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 354 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 355 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 356 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 357 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 358 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 359 #define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 360 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 361 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 362 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 363 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 364 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 365 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 366 #define mmCRTC_STATUS 0x1ba3 367 #define mmCRTC0_CRTC_STATUS 0x1ba3 368 #define mmCRTC1_CRTC_STATUS 0x1da3 369 #define mmCRTC2_CRTC_STATUS 0x1fa3 370 #define mmCRTC3_CRTC_STATUS 0x41a3 371 #define mmCRTC4_CRTC_STATUS 0x43a3 372 #define mmCRTC5_CRTC_STATUS 0x45a3 373 #define mmCRTC_STATUS_POSITION 0x1ba4 374 #define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 375 #define mmCRTC1_CRTC_STATUS_POSITION 0x1da4 376 #define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 377 #define mmCRTC3_CRTC_STATUS_POSITION 0x41a4 378 #define mmCRTC4_CRTC_STATUS_POSITION 0x43a4 379 #define mmCRTC5_CRTC_STATUS_POSITION 0x45a4 380 #define mmCRTC_NOM_VERT_POSITION 0x1ba5 381 #define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 382 #define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 383 #define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 384 #define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 385 #define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 386 #define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 387 #define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 388 #define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 389 #define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 390 #define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 391 #define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 392 #define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 393 #define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 394 #define mmCRTC_STATUS_VF_COUNT 0x1ba7 395 #define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 396 #define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 397 #define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 398 #define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 399 #define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 400 #define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 401 #define mmCRTC_STATUS_HV_COUNT 0x1ba8 402 #define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 403 #define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 404 #define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 405 #define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 406 #define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 407 #define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 408 #define mmCRTC_COUNT_CONTROL 0x1ba9 409 #define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 410 #define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 411 #define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 412 #define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 413 #define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 414 #define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 415 #define mmCRTC_COUNT_RESET 0x1baa 416 #define mmCRTC0_CRTC_COUNT_RESET 0x1baa 417 #define mmCRTC1_CRTC_COUNT_RESET 0x1daa 418 #define mmCRTC2_CRTC_COUNT_RESET 0x1faa 419 #define mmCRTC3_CRTC_COUNT_RESET 0x41aa 420 #define mmCRTC4_CRTC_COUNT_RESET 0x43aa 421 #define mmCRTC5_CRTC_COUNT_RESET 0x45aa 422 #define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab 423 #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab 424 #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab 425 #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab 426 #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab 427 #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab 428 #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab 429 #define mmCRTC_VERT_SYNC_CONTROL 0x1bac 430 #define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac 431 #define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac 432 #define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac 433 #define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac 434 #define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac 435 #define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac 436 #define mmCRTC_STEREO_STATUS 0x1bad 437 #define mmCRTC0_CRTC_STEREO_STATUS 0x1bad 438 #define mmCRTC1_CRTC_STEREO_STATUS 0x1dad 439 #define mmCRTC2_CRTC_STEREO_STATUS 0x1fad 440 #define mmCRTC3_CRTC_STEREO_STATUS 0x41ad 441 #define mmCRTC4_CRTC_STEREO_STATUS 0x43ad 442 #define mmCRTC5_CRTC_STEREO_STATUS 0x45ad 443 #define mmCRTC_STEREO_CONTROL 0x1bae 444 #define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae 445 #define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae 446 #define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae 447 #define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae 448 #define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae 449 #define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae 450 #define mmCRTC_SNAPSHOT_STATUS 0x1baf 451 #define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf 452 #define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf 453 #define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf 454 #define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af 455 #define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af 456 #define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af 457 #define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 458 #define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 459 #define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 460 #define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 461 #define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 462 #define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 463 #define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 464 #define mmCRTC_SNAPSHOT_POSITION 0x1bb1 465 #define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 466 #define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 467 #define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 468 #define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 469 #define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 470 #define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 471 #define mmCRTC_SNAPSHOT_FRAME 0x1bb2 472 #define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 473 #define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 474 #define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 475 #define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 476 #define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 477 #define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 478 #define mmCRTC_START_LINE_CONTROL 0x1bb3 479 #define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 480 #define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 481 #define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 482 #define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 483 #define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 484 #define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 485 #define mmCRTC_INTERRUPT_CONTROL 0x1bb4 486 #define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 487 #define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 488 #define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 489 #define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 490 #define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 491 #define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 492 #define mmCRTC_UPDATE_LOCK 0x1bb5 493 #define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 494 #define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 495 #define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 496 #define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 497 #define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 498 #define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 499 #define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 500 #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 501 #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 502 #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 503 #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 504 #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 505 #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 506 #define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 507 #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 508 #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 509 #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 510 #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 511 #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 512 #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 513 #define mmCRTC_TEST_PATTERN_CONTROL 0x1bba 514 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba 515 #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba 516 #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba 517 #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba 518 #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba 519 #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba 520 #define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb 521 #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb 522 #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb 523 #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb 524 #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb 525 #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb 526 #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb 527 #define mmCRTC_TEST_PATTERN_COLOR 0x1bbc 528 #define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc 529 #define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc 530 #define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc 531 #define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc 532 #define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc 533 #define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc 534 #define mmCRTC_MASTER_UPDATE_LOCK 0x1bbd 535 #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd 536 #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd 537 #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd 538 #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd 539 #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd 540 #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd 541 #define mmCRTC_MASTER_UPDATE_MODE 0x1bbe 542 #define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe 543 #define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe 544 #define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe 545 #define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be 546 #define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be 547 #define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be 548 #define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf 549 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf 550 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf 551 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf 552 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf 553 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf 554 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf 555 #define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 556 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 557 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 558 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 559 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 560 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 561 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 562 #define mmCRTC_MVP_STATUS 0x1bc1 563 #define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 564 #define mmCRTC1_CRTC_MVP_STATUS 0x1dc1 565 #define mmCRTC2_CRTC_MVP_STATUS 0x1fc1 566 #define mmCRTC3_CRTC_MVP_STATUS 0x41c1 567 #define mmCRTC4_CRTC_MVP_STATUS 0x43c1 568 #define mmCRTC5_CRTC_MVP_STATUS 0x45c1 569 #define mmCRTC_MASTER_EN 0x1bc2 570 #define mmCRTC0_CRTC_MASTER_EN 0x1bc2 571 #define mmCRTC1_CRTC_MASTER_EN 0x1dc2 572 #define mmCRTC2_CRTC_MASTER_EN 0x1fc2 573 #define mmCRTC3_CRTC_MASTER_EN 0x41c2 574 #define mmCRTC4_CRTC_MASTER_EN 0x43c2 575 #define mmCRTC5_CRTC_MASTER_EN 0x45c2 576 #define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 577 #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 578 #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 579 #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 580 #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 581 #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 582 #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 583 #define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 584 #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 585 #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 586 #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 587 #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 588 #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 589 #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 590 #define mmCRTC_OVERSCAN_COLOR 0x1bc8 591 #define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 592 #define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 593 #define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 594 #define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 595 #define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 596 #define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 597 #define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 598 #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 599 #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 600 #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 601 #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 602 #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 603 #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 604 #define mmCRTC_BLANK_DATA_COLOR 0x1bca 605 #define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca 606 #define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca 607 #define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca 608 #define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca 609 #define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca 610 #define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca 611 #define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb 612 #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb 613 #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb 614 #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb 615 #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb 616 #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb 617 #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb 618 #define mmCRTC_BLACK_COLOR 0x1bcc 619 #define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc 620 #define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc 621 #define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc 622 #define mmCRTC3_CRTC_BLACK_COLOR 0x41cc 623 #define mmCRTC4_CRTC_BLACK_COLOR 0x43cc 624 #define mmCRTC5_CRTC_BLACK_COLOR 0x45cc 625 #define mmCRTC_BLACK_COLOR_EXT 0x1bcd 626 #define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd 627 #define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd 628 #define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd 629 #define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd 630 #define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd 631 #define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd 632 #define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce 633 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce 634 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce 635 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce 636 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce 637 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce 638 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce 639 #define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf 640 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf 641 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf 642 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf 643 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf 644 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf 645 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf 646 #define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 647 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 648 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 649 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 650 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 651 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 652 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 653 #define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 654 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 655 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 656 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 657 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 658 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 659 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 660 #define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 661 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 662 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 663 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 664 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 665 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 666 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 667 #define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 668 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 669 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 670 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 671 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 672 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 673 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 674 #define mmCRTC_CRC_CNTL 0x1bd4 675 #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 676 #define mmCRTC1_CRTC_CRC_CNTL 0x1dd4 677 #define mmCRTC2_CRTC_CRC_CNTL 0x1fd4 678 #define mmCRTC3_CRTC_CRC_CNTL 0x41d4 679 #define mmCRTC4_CRTC_CRC_CNTL 0x43d4 680 #define mmCRTC5_CRTC_CRC_CNTL 0x45d4 681 #define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 682 #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 683 #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 684 #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 685 #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 686 #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 687 #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 688 #define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 689 #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 690 #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 691 #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 692 #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 693 #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 694 #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 695 #define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 696 #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 697 #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 698 #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 699 #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 700 #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 701 #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 702 #define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 703 #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 704 #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 705 #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 706 #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 707 #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 708 #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 709 #define mmCRTC_CRC0_DATA_RG 0x1bd9 710 #define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 711 #define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 712 #define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 713 #define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 714 #define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 715 #define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 716 #define mmCRTC_CRC0_DATA_B 0x1bda 717 #define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda 718 #define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda 719 #define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda 720 #define mmCRTC3_CRTC_CRC0_DATA_B 0x41da 721 #define mmCRTC4_CRTC_CRC0_DATA_B 0x43da 722 #define mmCRTC5_CRTC_CRC0_DATA_B 0x45da 723 #define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb 724 #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb 725 #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb 726 #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb 727 #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db 728 #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db 729 #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db 730 #define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc 731 #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc 732 #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc 733 #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc 734 #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc 735 #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc 736 #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc 737 #define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd 738 #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd 739 #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd 740 #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd 741 #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd 742 #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd 743 #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd 744 #define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde 745 #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde 746 #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde 747 #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde 748 #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de 749 #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de 750 #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de 751 #define mmCRTC_CRC1_DATA_RG 0x1bdf 752 #define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf 753 #define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf 754 #define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf 755 #define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df 756 #define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df 757 #define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df 758 #define mmCRTC_CRC1_DATA_B 0x1be0 759 #define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 760 #define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 761 #define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 762 #define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 763 #define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 764 #define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 765 #define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 766 #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 767 #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 768 #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 769 #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 770 #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 771 #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 772 #define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 773 #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 774 #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 775 #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 776 #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 777 #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 778 #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 779 #define mmCRTC_GSL_VSYNC_GAP 0x1b79 780 #define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 781 #define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 782 #define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 783 #define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 784 #define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 785 #define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 786 #define mmCRTC_GSL_WINDOW 0x1b7a 787 #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a 788 #define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a 789 #define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a 790 #define mmCRTC3_CRTC_GSL_WINDOW 0x417a 791 #define mmCRTC4_CRTC_GSL_WINDOW 0x437a 792 #define mmCRTC5_CRTC_GSL_WINDOW 0x457a 793 #define mmCRTC_GSL_CONTROL 0x1b7b 794 #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b 795 #define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b 796 #define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b 797 #define mmCRTC3_CRTC_GSL_CONTROL 0x417b 798 #define mmCRTC4_CRTC_GSL_CONTROL 0x437b 799 #define mmCRTC5_CRTC_GSL_CONTROL 0x457b 800 #define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 801 #define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 802 #define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 803 #define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 804 #define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 805 #define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 806 #define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 807 #define mmCRTC_TEST_DEBUG_DATA 0x1bc7 808 #define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 809 #define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 810 #define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 811 #define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 812 #define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 813 #define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 814 #define mmDAC_ENABLE 0x16aa 815 #define mmDAC_SOURCE_SELECT 0x16ab 816 #define mmDAC_CRC_EN 0x16ac 817 #define mmDAC_CRC_CONTROL 0x16ad 818 #define mmDAC_CRC_SIG_RGB_MASK 0x16ae 819 #define mmDAC_CRC_SIG_CONTROL_MASK 0x16af 820 #define mmDAC_CRC_SIG_RGB 0x16b0 821 #define mmDAC_CRC_SIG_CONTROL 0x16b1 822 #define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 823 #define mmDAC_STEREOSYNC_SELECT 0x16b3 824 #define mmDAC_AUTODETECT_CONTROL 0x16b4 825 #define mmDAC_AUTODETECT_CONTROL2 0x16b5 826 #define mmDAC_AUTODETECT_CONTROL3 0x16b6 827 #define mmDAC_AUTODETECT_STATUS 0x16b7 828 #define mmDAC_AUTODETECT_INT_CONTROL 0x16b8 829 #define mmDAC_FORCE_OUTPUT_CNTL 0x16b9 830 #define mmDAC_FORCE_DATA 0x16ba 831 #define mmDAC_POWERDOWN 0x16bb 832 #define mmDAC_CONTROL 0x16bc 833 #define mmDAC_COMPARATOR_ENABLE 0x16bd 834 #define mmDAC_COMPARATOR_OUTPUT 0x16be 835 #define mmDAC_PWR_CNTL 0x16bf 836 #define mmDAC_DFT_CONFIG 0x16c0 837 #define mmDAC_FIFO_STATUS 0x16c1 838 #define mmDAC_TEST_DEBUG_INDEX 0x16c2 839 #define mmDAC_TEST_DEBUG_DATA 0x16c3 840 #define mmPERFCOUNTER_CNTL 0x170 841 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 842 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 843 #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 844 #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 845 #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 846 #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 847 #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 848 #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 849 #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 850 #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 851 #define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 852 #define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 853 #define mmPERFCOUNTER_STATE 0x171 854 #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 855 #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 856 #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 857 #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 858 #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 859 #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 860 #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 861 #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 862 #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 863 #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 864 #define mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 865 #define mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 866 #define mmPERFMON_CNTL 0x173 867 #define mmDC_PERFMON0_PERFMON_CNTL 0x173 868 #define mmDC_PERFMON1_PERFMON_CNTL 0x367 869 #define mmDC_PERFMON2_PERFMON_CNTL 0x18cb 870 #define mmDC_PERFMON3_PERFMON_CNTL 0x1b27 871 #define mmDC_PERFMON4_PERFMON_CNTL 0x1d27 872 #define mmDC_PERFMON5_PERFMON_CNTL 0x1f27 873 #define mmDC_PERFMON6_PERFMON_CNTL 0x4127 874 #define mmDC_PERFMON7_PERFMON_CNTL 0x4327 875 #define mmDC_PERFMON8_PERFMON_CNTL 0x4527 876 #define mmDC_PERFMON9_PERFMON_CNTL 0x4727 877 #define mmDC_PERFMON10_PERFMON_CNTL 0x59a3 878 #define mmDC_PERFMON11_PERFMON_CNTL 0x5f6b 879 #define mmPERFMON_CNTL2 0x17a 880 #define mmDC_PERFMON0_PERFMON_CNTL2 0x17a 881 #define mmDC_PERFMON1_PERFMON_CNTL2 0x36e 882 #define mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 883 #define mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e 884 #define mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e 885 #define mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e 886 #define mmDC_PERFMON6_PERFMON_CNTL2 0x412e 887 #define mmDC_PERFMON7_PERFMON_CNTL2 0x432e 888 #define mmDC_PERFMON8_PERFMON_CNTL2 0x452e 889 #define mmDC_PERFMON9_PERFMON_CNTL2 0x472e 890 #define mmDC_PERFMON10_PERFMON_CNTL2 0x59aa 891 #define mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 892 #define mmPERFMON_CVALUE_INT_MISC 0x172 893 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 894 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 895 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca 896 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 897 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 898 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 899 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 900 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 901 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 902 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 903 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 904 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a 905 #define mmPERFMON_CVALUE_LOW 0x174 906 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 907 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 908 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc 909 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 910 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 911 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 912 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 913 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 914 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 915 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 916 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 917 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c 918 #define mmPERFMON_HI 0x175 919 #define mmDC_PERFMON0_PERFMON_HI 0x175 920 #define mmDC_PERFMON1_PERFMON_HI 0x369 921 #define mmDC_PERFMON2_PERFMON_HI 0x18cd 922 #define mmDC_PERFMON3_PERFMON_HI 0x1b29 923 #define mmDC_PERFMON4_PERFMON_HI 0x1d29 924 #define mmDC_PERFMON5_PERFMON_HI 0x1f29 925 #define mmDC_PERFMON6_PERFMON_HI 0x4129 926 #define mmDC_PERFMON7_PERFMON_HI 0x4329 927 #define mmDC_PERFMON8_PERFMON_HI 0x4529 928 #define mmDC_PERFMON9_PERFMON_HI 0x4729 929 #define mmDC_PERFMON10_PERFMON_HI 0x59a5 930 #define mmDC_PERFMON11_PERFMON_HI 0x5f6d 931 #define mmPERFMON_LOW 0x176 932 #define mmDC_PERFMON0_PERFMON_LOW 0x176 933 #define mmDC_PERFMON1_PERFMON_LOW 0x36a 934 #define mmDC_PERFMON2_PERFMON_LOW 0x18ce 935 #define mmDC_PERFMON3_PERFMON_LOW 0x1b2a 936 #define mmDC_PERFMON4_PERFMON_LOW 0x1d2a 937 #define mmDC_PERFMON5_PERFMON_LOW 0x1f2a 938 #define mmDC_PERFMON6_PERFMON_LOW 0x412a 939 #define mmDC_PERFMON7_PERFMON_LOW 0x432a 940 #define mmDC_PERFMON8_PERFMON_LOW 0x452a 941 #define mmDC_PERFMON9_PERFMON_LOW 0x472a 942 #define mmDC_PERFMON10_PERFMON_LOW 0x59a6 943 #define mmDC_PERFMON11_PERFMON_LOW 0x5f6e 944 #define mmPERFMON_TEST_DEBUG_INDEX 0x177 945 #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 946 #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b 947 #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf 948 #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b 949 #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b 950 #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b 951 #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b 952 #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b 953 #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b 954 #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b 955 #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 956 #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f 957 #define mmPERFMON_TEST_DEBUG_DATA 0x178 958 #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 959 #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c 960 #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 961 #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c 962 #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c 963 #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c 964 #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c 965 #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c 966 #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c 967 #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c 968 #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 969 #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 970 #define mmREFCLK_CNTL 0x109 971 #define mmDCCG_CBUS_WRCMD_DELAY 0x110 972 #define mmDPREFCLK_CNTL 0x118 973 #define mmDCE_VERSION 0x11e 974 #define mmAVSYNC_COUNTER_WRITE 0x12a 975 #define mmAVSYNC_COUNTER_CONTROL 0x12b 976 #define mmAVSYNC_COUNTER_READ 0x12f 977 #define mmDCCG_GTC_CNTL 0x120 978 #define mmDCCG_GTC_DTO_INCR 0x121 979 #define mmDCCG_GTC_DTO_MODULO 0x122 980 #define mmDCCG_GTC_CURRENT 0x123 981 #define mmDCCG_DS_DTO_INCR 0x113 982 #define mmDCCG_DS_DTO_MODULO 0x114 983 #define mmDCCG_DS_CNTL 0x115 984 #define mmDCCG_DS_HW_CAL_INTERVAL 0x116 985 #define mmDCCG_DS_DEBUG_CNTL 0x112 986 #define mmDMCU_SMU_INTERRUPT_CNTL 0x12c 987 #define mmSMU_CONTROL 0x12d 988 #define mmSMU_INTERRUPT_CONTROL 0x12e 989 #define mmDAC_CLK_ENABLE 0x128 990 #define mmDVO_CLK_ENABLE 0x129 991 #define mmDCCG_GATE_DISABLE_CNTL 0x134 992 #define mmDCCG_GATE_DISABLE_CNTL2 0x13c 993 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 994 #define mmSCLK_CGTT_BLK_CTRL_REG 0x136 995 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 996 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b 997 #define mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d 998 #define mmDCCG_CAC_STATUS 0x137 999 #define mmPIXCLK1_RESYNC_CNTL 0x138 1000 #define mmPIXCLK2_RESYNC_CNTL 0x139 1001 #define mmPIXCLK0_RESYNC_CNTL 0x13a 1002 #define mmPHYPLL_PIXCLK_CNTL 0x13e 1003 #define mmMICROSECOND_TIME_BASE_DIV 0x13b 1004 #define mmDCCG_DISP_CNTL_REG 0x13f 1005 #define mmMILLISECOND_TIME_BASE_DIV 0x130 1006 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 1007 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 1008 #define mmDCCG_PERFMON_CNTL 0x133 1009 #define mmDCCG_PERFMON_CNTL2 0x10e 1010 #define mmCRTC0_PIXEL_RATE_CNTL 0x140 1011 #define mmDP_DTO0_PHASE 0x141 1012 #define mmDP_DTO0_MODULO 0x142 1013 #define mmCRTC1_PIXEL_RATE_CNTL 0x144 1014 #define mmDP_DTO1_PHASE 0x145 1015 #define mmDP_DTO1_MODULO 0x146 1016 #define mmCRTC2_PIXEL_RATE_CNTL 0x148 1017 #define mmDP_DTO2_PHASE 0x149 1018 #define mmDP_DTO2_MODULO 0x14a 1019 #define mmCRTC3_PIXEL_RATE_CNTL 0x14c 1020 #define mmDP_DTO3_PHASE 0x14d 1021 #define mmDP_DTO3_MODULO 0x14e 1022 #define mmCRTC4_PIXEL_RATE_CNTL 0x150 1023 #define mmDP_DTO4_PHASE 0x151 1024 #define mmDP_DTO4_MODULO 0x152 1025 #define mmCRTC5_PIXEL_RATE_CNTL 0x154 1026 #define mmDP_DTO5_PHASE 0x155 1027 #define mmDP_DTO5_MODULO 0x156 1028 #define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x104 1029 #define mmDCCG_SOFT_RESET 0x15f 1030 #define mmSYMCLKA_CLOCK_ENABLE 0x160 1031 #define mmSYMCLKB_CLOCK_ENABLE 0x161 1032 #define mmSYMCLKC_CLOCK_ENABLE 0x162 1033 #define mmSYMCLKD_CLOCK_ENABLE 0x163 1034 #define mmSYMCLKE_CLOCK_ENABLE 0x164 1035 #define mmSYMCLKF_CLOCK_ENABLE 0x165 1036 #define mmSYMCLKG_CLOCK_ENABLE 0x117 1037 #define mmDPDBG_CLK_FORCE_CONTROL 0x10d 1038 #define mmDCCG_AUDIO_DTO_SOURCE 0x16b 1039 #define mmDCCG_AUDIO_DTO0_PHASE 0x16c 1040 #define mmDCCG_AUDIO_DTO0_MODULE 0x16d 1041 #define mmDCCG_AUDIO_DTO1_PHASE 0x16e 1042 #define mmDCCG_AUDIO_DTO1_MODULE 0x16f 1043 #define mmDCCG_TEST_DEBUG_INDEX 0x17c 1044 #define mmDCCG_TEST_DEBUG_DATA 0x17d 1045 #define mmDCCG_TEST_CLK_SEL 0x17e 1046 #define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 1047 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 1048 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc 1049 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 1050 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 1051 #define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 1052 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 1053 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd 1054 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 1055 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 1056 #define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 1057 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 1058 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde 1059 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea 1060 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 1061 #define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 1062 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 1063 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf 1064 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb 1065 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 1066 #define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 1067 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 1068 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 1069 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec 1070 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 1071 #define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 1072 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 1073 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 1074 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed 1075 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 1076 #define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 1077 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 1078 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 1079 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee 1080 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa 1081 #define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 1082 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 1083 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 1084 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef 1085 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb 1086 #define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 1087 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 1088 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 1089 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 1090 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc 1091 #define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 1092 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 1093 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 1094 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 1095 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd 1096 #define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda 1097 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda 1098 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 1099 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 1100 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe 1101 #define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb 1102 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb 1103 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 1104 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 1105 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff 1106 #define mmPLL_MACRO_CNTL_RESERVED0 0x1700 1107 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 1108 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a 1109 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 1110 #define mmPLL_MACRO_CNTL_RESERVED1 0x1701 1111 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 1112 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b 1113 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 1114 #define mmPLL_MACRO_CNTL_RESERVED2 0x1702 1115 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 1116 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c 1117 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 1118 #define mmPLL_MACRO_CNTL_RESERVED3 0x1703 1119 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 1120 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d 1121 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 1122 #define mmPLL_MACRO_CNTL_RESERVED4 0x1704 1123 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 1124 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e 1125 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 1126 #define mmPLL_MACRO_CNTL_RESERVED5 0x1705 1127 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 1128 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f 1129 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 1130 #define mmPLL_MACRO_CNTL_RESERVED6 0x1706 1131 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 1132 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 1133 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a 1134 #define mmPLL_MACRO_CNTL_RESERVED7 0x1707 1135 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 1136 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 1137 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b 1138 #define mmPLL_MACRO_CNTL_RESERVED8 0x1708 1139 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 1140 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 1141 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c 1142 #define mmPLL_MACRO_CNTL_RESERVED9 0x1709 1143 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 1144 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 1145 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d 1146 #define mmPLL_MACRO_CNTL_RESERVED10 0x170a 1147 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a 1148 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 1149 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e 1150 #define mmPLL_MACRO_CNTL_RESERVED11 0x170b 1151 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b 1152 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 1153 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f 1154 #define mmPLL_MACRO_CNTL_RESERVED12 0x170c 1155 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c 1156 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 1157 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 1158 #define mmPLL_MACRO_CNTL_RESERVED13 0x170d 1159 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d 1160 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 1161 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 1162 #define mmPLL_MACRO_CNTL_RESERVED14 0x170e 1163 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e 1164 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 1165 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 1166 #define mmPLL_MACRO_CNTL_RESERVED15 0x170f 1167 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f 1168 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 1169 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 1170 #define mmPLL_MACRO_CNTL_RESERVED16 0x1710 1171 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 1172 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a 1173 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 1174 #define mmPLL_MACRO_CNTL_RESERVED17 0x1711 1175 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 1176 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b 1177 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 1178 #define mmPLL_MACRO_CNTL_RESERVED18 0x1712 1179 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 1180 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c 1181 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 1182 #define mmPLL_MACRO_CNTL_RESERVED19 0x1713 1183 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 1184 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d 1185 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 1186 #define mmPLL_MACRO_CNTL_RESERVED20 0x1714 1187 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 1188 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e 1189 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 1190 #define mmPLL_MACRO_CNTL_RESERVED21 0x1715 1191 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 1192 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f 1193 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 1194 #define mmPLL_MACRO_CNTL_RESERVED22 0x1716 1195 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 1196 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 1197 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a 1198 #define mmPLL_MACRO_CNTL_RESERVED23 0x1717 1199 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 1200 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 1201 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b 1202 #define mmPLL_MACRO_CNTL_RESERVED24 0x1718 1203 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 1204 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 1205 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c 1206 #define mmPLL_MACRO_CNTL_RESERVED25 0x1719 1207 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 1208 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 1209 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d 1210 #define mmPLL_MACRO_CNTL_RESERVED26 0x171a 1211 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a 1212 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 1213 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e 1214 #define mmPLL_MACRO_CNTL_RESERVED27 0x171b 1215 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b 1216 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 1217 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f 1218 #define mmPLL_MACRO_CNTL_RESERVED28 0x171c 1219 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c 1220 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 1221 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 1222 #define mmPLL_MACRO_CNTL_RESERVED29 0x171d 1223 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d 1224 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 1225 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 1226 #define mmPLL_MACRO_CNTL_RESERVED30 0x171e 1227 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e 1228 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 1229 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 1230 #define mmPLL_MACRO_CNTL_RESERVED31 0x171f 1231 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f 1232 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 1233 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 1234 #define mmPLL_MACRO_CNTL_RESERVED32 0x1720 1235 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 1236 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a 1237 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 1238 #define mmPLL_MACRO_CNTL_RESERVED33 0x1721 1239 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 1240 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b 1241 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 1242 #define mmPLL_MACRO_CNTL_RESERVED34 0x1722 1243 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 1244 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c 1245 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 1246 #define mmPLL_MACRO_CNTL_RESERVED35 0x1723 1247 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 1248 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d 1249 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 1250 #define mmPLL_MACRO_CNTL_RESERVED36 0x1724 1251 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 1252 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e 1253 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 1254 #define mmPLL_MACRO_CNTL_RESERVED37 0x1725 1255 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 1256 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f 1257 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 1258 #define mmPLL_MACRO_CNTL_RESERVED38 0x1726 1259 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 1260 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 1261 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a 1262 #define mmPLL_MACRO_CNTL_RESERVED39 0x1727 1263 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 1264 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 1265 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b 1266 #define mmPLL_MACRO_CNTL_RESERVED40 0x1728 1267 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 1268 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 1269 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c 1270 #define mmPLL_MACRO_CNTL_RESERVED41 0x1729 1271 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 1272 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 1273 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d 1274 #define mmDENTIST_DISPCLK_CNTL 0x124 1275 #define mmDCDEBUG_BUS_CLK1_SEL 0x16c4 1276 #define mmDCDEBUG_BUS_CLK2_SEL 0x16c5 1277 #define mmDCDEBUG_BUS_CLK3_SEL 0x16c6 1278 #define mmDCDEBUG_BUS_CLK4_SEL 0x16c7 1279 #define mmDCDEBUG_BUS_CLK5_SEL 0x16c8 1280 #define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 1281 #define mmDCDEBUG_OUT_CNTL 0x16ca 1282 #define mmDCDEBUG_OUT_DATA 0x16cb 1283 #define mmDMIF_ADDR_CONFIG 0x2f5 1284 #define mmDMIF_CONTROL 0x2f6 1285 #define mmDMIF_STATUS 0x2f7 1286 #define mmDMIF_HW_DEBUG 0x2f8 1287 #define mmDMIF_ARBITRATION_CONTROL 0x2f9 1288 #define mmPIPE0_ARBITRATION_CONTROL3 0x2fa 1289 #define mmPIPE1_ARBITRATION_CONTROL3 0x2fb 1290 #define mmPIPE2_ARBITRATION_CONTROL3 0x2fc 1291 #define mmPIPE3_ARBITRATION_CONTROL3 0x2fd 1292 #define mmPIPE4_ARBITRATION_CONTROL3 0x2fe 1293 #define mmPIPE5_ARBITRATION_CONTROL3 0x2ff 1294 #define mmPIPE6_ARBITRATION_CONTROL3 0x32a 1295 #define mmPIPE7_ARBITRATION_CONTROL3 0x32b 1296 #define mmDMIF_P_VMID 0x300 1297 #define mmDMIF_URG_OVERRIDE 0x329 1298 #define mmDMIF_TEST_DEBUG_INDEX 0x301 1299 #define mmDMIF_TEST_DEBUG_DATA 0x302 1300 #define ixDMIF_DEBUG02_CORE0 0x2 1301 #define ixDMIF_DEBUG02_CORE1 0xa 1302 #define mmDMIF_ADDR_CALC 0x303 1303 #define mmDMIF_STATUS2 0x304 1304 #define mmPIPE0_MAX_REQUESTS 0x305 1305 #define mmPIPE1_MAX_REQUESTS 0x306 1306 #define mmPIPE2_MAX_REQUESTS 0x307 1307 #define mmPIPE3_MAX_REQUESTS 0x308 1308 #define mmPIPE4_MAX_REQUESTS 0x309 1309 #define mmPIPE5_MAX_REQUESTS 0x30a 1310 #define mmPIPE6_MAX_REQUESTS 0x32c 1311 #define mmPIPE7_MAX_REQUESTS 0x32d 1312 #define mmDVMM_REG_RD_STATUS 0x32e 1313 #define mmDVMM_REG_RD_DATA 0x32f 1314 #define mmDVMM_PTE_REQ 0x330 1315 #define mmDVMM_CNTL 0x331 1316 #define mmDVMM_FAULT_STATUS 0x332 1317 #define mmDVMM_FAULT_ADDR 0x333 1318 #define mmLOW_POWER_TILING_CONTROL 0x30b 1319 #define mmMCIF_CONTROL 0x30c 1320 #define mmMCIF_WRITE_COMBINE_CONTROL 0x30d 1321 #define mmMCIF_TEST_DEBUG_INDEX 0x30e 1322 #define mmMCIF_TEST_DEBUG_DATA 0x30f 1323 #define ixIDDCCIF02_DBG_DCCIF_C 0x9 1324 #define ixIDDCCIF04_DBG_DCCIF_E 0xb 1325 #define ixIDDCCIF05_DBG_DCCIF_F 0xc 1326 #define mmMCIF_VMID 0x310 1327 #define mmMCIF_MEM_CONTROL 0x311 1328 #define mmCC_DC_PIPE_DIS 0x312 1329 #define mmMC_DC_INTERFACE_NACK_STATUS 0x313 1330 #define mmRBBMIF_TIMEOUT 0x314 1331 #define mmRBBMIF_STATUS 0x315 1332 #define mmRBBMIF_TIMEOUT_DIS 0x316 1333 #define mmRBBMIF_STATUS_FLAG 0x327 1334 #define mmDCI_MEM_PWR_STATUS 0x317 1335 #define mmDCI_MEM_PWR_STATUS2 0x318 1336 #define mmDCI_CLK_CNTL 0x319 1337 #define mmDCI_CLK_RAMP_CNTL 0x31a 1338 #define mmDCI_MEM_PWR_CNTL 0x31b 1339 #define mmDCI_MEM_PWR_CNTL2 0x31c 1340 #define mmDCI_MEM_PWR_CNTL3 0x31d 1341 #define mmDVMM_PTE_PGMEM_CONTROL 0x335 1342 #define mmDVMM_PTE_PGMEM_STATE 0x336 1343 #define mmDCI_SOFT_RESET 0x328 1344 #define mmDCI_MISC 0x334 1345 #define mmDCI_TEST_DEBUG_INDEX 0x31e 1346 #define mmDCI_TEST_DEBUG_DATA 0x31f 1347 #define mmDCI_DEBUG_CONFIG 0x320 1348 #define mmPIPE0_DMIF_BUFFER_CONTROL 0x321 1349 #define mmPIPE1_DMIF_BUFFER_CONTROL 0x322 1350 #define mmPIPE2_DMIF_BUFFER_CONTROL 0x323 1351 #define mmPIPE3_DMIF_BUFFER_CONTROL 0x324 1352 #define mmPIPE4_DMIF_BUFFER_CONTROL 0x325 1353 #define mmPIPE5_DMIF_BUFFER_CONTROL 0x326 1354 #define mmDC_GENERICA 0x4800 1355 #define mmDC_GENERICB 0x4801 1356 #define mmDC_PAD_EXTERN_SIG 0x4802 1357 #define mmDC_REF_CLK_CNTL 0x4803 1358 #define mmDC_GPIO_DEBUG 0x4804 1359 #define mmUNIPHYA_LINK_CNTL 0x4805 1360 #define mmUNIPHYB_LINK_CNTL 0x4807 1361 #define mmUNIPHYC_LINK_CNTL 0x4809 1362 #define mmUNIPHYD_LINK_CNTL 0x480b 1363 #define mmUNIPHYE_LINK_CNTL 0x480d 1364 #define mmUNIPHYF_LINK_CNTL 0x480f 1365 #define mmUNIPHYG_LINK_CNTL 0x4811 1366 #define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 1367 #define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 1368 #define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a 1369 #define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c 1370 #define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e 1371 #define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 1372 #define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 1373 #define mmUNIPHYLPA_LINK_CNTL 0x4847 1374 #define mmUNIPHYLPB_LINK_CNTL 0x4848 1375 #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849 1376 #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a 1377 #define mmUNIPHY_IMPCAL_LINKA 0x4838 1378 #define mmUNIPHY_IMPCAL_LINKB 0x4839 1379 #define mmUNIPHY_IMPCAL_LINKC 0x483f 1380 #define mmUNIPHY_IMPCAL_LINKD 0x4840 1381 #define mmUNIPHY_IMPCAL_LINKE 0x4843 1382 #define mmUNIPHY_IMPCAL_LINKF 0x4844 1383 #define mmUNIPHY_IMPCAL_PERIOD 0x483a 1384 #define mmAUXP_IMPCAL 0x483b 1385 #define mmAUXN_IMPCAL 0x483c 1386 #define mmDCIO_IMPCAL_CNTL 0x483d 1387 #define mmUNIPHY_IMPCAL_PSW_AB 0x483e 1388 #define mmDCIO_IMPCAL_CNTL_CD 0x4841 1389 #define mmUNIPHY_IMPCAL_PSW_CD 0x4842 1390 #define mmDCIO_IMPCAL_CNTL_EF 0x4845 1391 #define mmUNIPHY_IMPCAL_PSW_EF 0x4846 1392 #define mmDCIO_WRCMD_DELAY 0x4816 1393 #define mmDC_PINSTRAPS 0x4818 1394 #define mmDC_DVODATA_CONFIG 0x481a 1395 #define mmLVTMA_PWRSEQ_CNTL 0x481b 1396 #define mmLVTMA_PWRSEQ_STATE 0x481c 1397 #define mmLVTMA_PWRSEQ_REF_DIV 0x481d 1398 #define mmLVTMA_PWRSEQ_DELAY1 0x481e 1399 #define mmLVTMA_PWRSEQ_DELAY2 0x481f 1400 #define mmBL_PWM_CNTL 0x4820 1401 #define mmBL_PWM_CNTL2 0x4821 1402 #define mmBL_PWM_PERIOD_CNTL 0x4822 1403 #define mmBL_PWM_GRP1_REG_LOCK 0x4823 1404 #define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 1405 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 1406 #define mmDCIO_GSL0_CNTL 0x4826 1407 #define mmDCIO_GSL1_CNTL 0x4827 1408 #define mmDCIO_GSL2_CNTL 0x4828 1409 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 1410 #define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a 1411 #define mmDC_GPU_TIMER_READ 0x482b 1412 #define mmDC_GPU_TIMER_READ_CNTL 0x482c 1413 #define mmDCIO_CLOCK_CNTL 0x482d 1414 #define mmDCIO_DEBUG 0x482f 1415 #define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 1416 #define mmDBG_OUT_CNTL 0x4834 1417 #define mmDCIO_DEBUG_CONFIG 0x4835 1418 #define mmDCIO_SOFT_RESET 0x4836 1419 #define mmDCIO_DPHY_SEL 0x4837 1420 #define mmDCIO_TEST_DEBUG_INDEX 0x4831 1421 #define mmDCIO_TEST_DEBUG_DATA 0x4832 1422 #define ixDCIO_DEBUG1 0x1 1423 #define ixDCIO_DEBUG2 0x2 1424 #define ixDCIO_DEBUG3 0x3 1425 #define ixDCIO_DEBUG4 0x4 1426 #define ixDCIO_DEBUG5 0x5 1427 #define ixDCIO_DEBUG6 0x6 1428 #define ixDCIO_DEBUG7 0x7 1429 #define ixDCIO_DEBUG8 0x8 1430 #define ixDCIO_DEBUG9 0x9 1431 #define ixDCIO_DEBUGA 0xa 1432 #define ixDCIO_DEBUGB 0xb 1433 #define ixDCIO_DEBUGC 0xc 1434 #define ixDCIO_DEBUGD 0xd 1435 #define ixDCIO_DEBUGE 0xe 1436 #define ixDCIO_DEBUGF 0xf 1437 #define ixDCIO_DEBUG10 0x10 1438 #define ixDCIO_DEBUG11 0x11 1439 #define ixDCIO_DEBUG12 0x12 1440 #define ixDCIO_DEBUG13 0x13 1441 #define ixDCIO_DEBUG14 0x14 1442 #define ixDCIO_DEBUG15 0x15 1443 #define ixDCIO_DEBUG16 0x16 1444 #define ixDCIO_DEBUG17 0x17 1445 #define ixDCIO_DEBUG18 0x18 1446 #define ixDCIO_DEBUG19 0x19 1447 #define ixDCIO_DEBUG1A 0x1a 1448 #define ixDCIO_DEBUG1B 0x1b 1449 #define ixDCIO_DEBUG_ID 0x0 1450 #define mmDC_GPIO_GENERIC_MASK 0x4860 1451 #define mmDC_GPIO_GENERIC_A 0x4861 1452 #define mmDC_GPIO_GENERIC_EN 0x4862 1453 #define mmDC_GPIO_GENERIC_Y 0x4863 1454 #define mmDC_GPIO_DVODATA_MASK 0x4864 1455 #define mmDC_GPIO_DVODATA_A 0x4865 1456 #define mmDC_GPIO_DVODATA_EN 0x4866 1457 #define mmDC_GPIO_DVODATA_Y 0x4867 1458 #define mmDC_GPIO_DDC1_MASK 0x4868 1459 #define mmDC_GPIO_DDC1_A 0x4869 1460 #define mmDC_GPIO_DDC1_EN 0x486a 1461 #define mmDC_GPIO_DDC1_Y 0x486b 1462 #define mmDC_GPIO_DDC2_MASK 0x486c 1463 #define mmDC_GPIO_DDC2_A 0x486d 1464 #define mmDC_GPIO_DDC2_EN 0x486e 1465 #define mmDC_GPIO_DDC2_Y 0x486f 1466 #define mmDC_GPIO_DDC3_MASK 0x4870 1467 #define mmDC_GPIO_DDC3_A 0x4871 1468 #define mmDC_GPIO_DDC3_EN 0x4872 1469 #define mmDC_GPIO_DDC3_Y 0x4873 1470 #define mmDC_GPIO_DDC4_MASK 0x4874 1471 #define mmDC_GPIO_DDC4_A 0x4875 1472 #define mmDC_GPIO_DDC4_EN 0x4876 1473 #define mmDC_GPIO_DDC4_Y 0x4877 1474 #define mmDC_GPIO_DDC5_MASK 0x4878 1475 #define mmDC_GPIO_DDC5_A 0x4879 1476 #define mmDC_GPIO_DDC5_EN 0x487a 1477 #define mmDC_GPIO_DDC5_Y 0x487b 1478 #define mmDC_GPIO_DDC6_MASK 0x487c 1479 #define mmDC_GPIO_DDC6_A 0x487d 1480 #define mmDC_GPIO_DDC6_EN 0x487e 1481 #define mmDC_GPIO_DDC6_Y 0x487f 1482 #define mmDC_GPIO_DDCVGA_MASK 0x4880 1483 #define mmDC_GPIO_DDCVGA_A 0x4881 1484 #define mmDC_GPIO_DDCVGA_EN 0x4882 1485 #define mmDC_GPIO_DDCVGA_Y 0x4883 1486 #define mmDC_GPIO_SYNCA_MASK 0x4884 1487 #define mmDC_GPIO_SYNCA_A 0x4885 1488 #define mmDC_GPIO_SYNCA_EN 0x4886 1489 #define mmDC_GPIO_SYNCA_Y 0x4887 1490 #define mmDC_GPIO_GENLK_MASK 0x4888 1491 #define mmDC_GPIO_GENLK_A 0x4889 1492 #define mmDC_GPIO_GENLK_EN 0x488a 1493 #define mmDC_GPIO_GENLK_Y 0x488b 1494 #define mmDC_GPIO_HPD_MASK 0x488c 1495 #define mmDC_GPIO_HPD_A 0x488d 1496 #define mmDC_GPIO_HPD_EN 0x488e 1497 #define mmDC_GPIO_HPD_Y 0x488f 1498 #define mmDC_GPIO_PWRSEQ_MASK 0x4890 1499 #define mmDC_GPIO_PWRSEQ_A 0x4891 1500 #define mmDC_GPIO_PWRSEQ_EN 0x4892 1501 #define mmDC_GPIO_PWRSEQ_Y 0x4893 1502 #define mmDC_GPIO_PAD_STRENGTH_1 0x4894 1503 #define mmDC_GPIO_PAD_STRENGTH_2 0x4895 1504 #define mmPHY_AUX_CNTL 0x4897 1505 #define mmDC_GPIO_I2CPAD_MASK 0x4898 1506 #define mmDC_GPIO_I2CPAD_A 0x4899 1507 #define mmDC_GPIO_I2CPAD_EN 0x489a 1508 #define mmDC_GPIO_I2CPAD_Y 0x489b 1509 #define mmDC_GPIO_I2CPAD_STRENGTH 0x489c 1510 #define mmDVO_VREF_CONTROL 0x489e 1511 #define mmDVO_SKEW_ADJUST 0x489f 1512 #define mmDAC_MACRO_CNTL_RESERVED0 0x48b8 1513 #define mmDAC_MACRO_CNTL_RESERVED1 0x48b9 1514 #define mmDAC_MACRO_CNTL_RESERVED2 0x48ba 1515 #define mmDAC_MACRO_CNTL_RESERVED3 0x48bb 1516 #define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 1517 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 1518 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 1519 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 1520 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 1521 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 1522 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 1523 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 1524 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x49c0 1525 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x49e0 1526 #define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 1527 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 1528 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 1529 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 1530 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 1531 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 1532 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 1533 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 1534 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x49c1 1535 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x49e1 1536 #define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 1537 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 1538 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 1539 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 1540 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 1541 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 1542 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 1543 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 1544 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x49c2 1545 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x49e2 1546 #define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 1547 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 1548 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 1549 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 1550 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 1551 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 1552 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 1553 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 1554 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x49c3 1555 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x49e3 1556 #define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 1557 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 1558 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 1559 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 1560 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 1561 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 1562 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 1563 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 1564 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x49c4 1565 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x49e4 1566 #define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 1567 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 1568 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 1569 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 1570 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 1571 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 1572 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 1573 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 1574 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x49c5 1575 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x49e5 1576 #define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 1577 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 1578 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 1579 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 1580 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 1581 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 1582 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 1583 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 1584 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x49c6 1585 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x49e6 1586 #define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 1587 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 1588 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 1589 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 1590 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 1591 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 1592 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 1593 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 1594 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x49c7 1595 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x49e7 1596 #define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 1597 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 1598 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 1599 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 1600 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 1601 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 1602 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 1603 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 1604 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x49c8 1605 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x49e8 1606 #define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 1607 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 1608 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 1609 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 1610 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 1611 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 1612 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 1613 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 1614 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x49c9 1615 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x49e9 1616 #define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca 1617 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca 1618 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea 1619 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a 1620 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a 1621 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a 1622 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a 1623 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a 1624 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x49ca 1625 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x49ea 1626 #define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb 1627 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb 1628 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb 1629 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b 1630 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b 1631 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b 1632 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b 1633 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b 1634 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x49cb 1635 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x49eb 1636 #define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc 1637 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc 1638 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec 1639 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c 1640 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c 1641 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c 1642 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c 1643 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c 1644 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x49cc 1645 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x49ec 1646 #define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd 1647 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd 1648 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed 1649 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d 1650 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d 1651 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d 1652 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d 1653 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d 1654 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x49cd 1655 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x49ed 1656 #define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce 1657 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce 1658 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee 1659 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e 1660 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e 1661 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e 1662 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e 1663 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e 1664 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x49ce 1665 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x49ee 1666 #define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf 1667 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf 1668 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef 1669 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f 1670 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f 1671 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f 1672 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f 1673 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f 1674 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x49cf 1675 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x49ef 1676 #define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 1677 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 1678 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 1679 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 1680 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 1681 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 1682 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 1683 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 1684 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x49d0 1685 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x49f0 1686 #define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 1687 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 1688 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 1689 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 1690 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 1691 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 1692 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 1693 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 1694 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x49d1 1695 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x49f1 1696 #define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 1697 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 1698 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 1699 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 1700 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 1701 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 1702 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 1703 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 1704 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x49d2 1705 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x49f2 1706 #define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 1707 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 1708 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 1709 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 1710 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 1711 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 1712 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 1713 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 1714 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x49d3 1715 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x49f3 1716 #define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 1717 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 1718 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 1719 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 1720 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 1721 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 1722 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 1723 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 1724 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x49d4 1725 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x49f4 1726 #define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 1727 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 1728 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 1729 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 1730 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 1731 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 1732 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 1733 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 1734 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x49d5 1735 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x49f5 1736 #define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 1737 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 1738 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 1739 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 1740 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 1741 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 1742 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 1743 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 1744 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x49d6 1745 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x49f6 1746 #define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 1747 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 1748 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 1749 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 1750 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 1751 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 1752 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 1753 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 1754 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x49d7 1755 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x49f7 1756 #define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 1757 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 1758 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 1759 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 1760 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 1761 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 1762 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 1763 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 1764 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x49d8 1765 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x49f8 1766 #define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 1767 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 1768 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 1769 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 1770 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 1771 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 1772 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 1773 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 1774 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x49d9 1775 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x49f9 1776 #define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da 1777 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da 1778 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa 1779 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a 1780 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a 1781 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a 1782 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a 1783 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a 1784 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x49da 1785 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x49fa 1786 #define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db 1787 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db 1788 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb 1789 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b 1790 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b 1791 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b 1792 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b 1793 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b 1794 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x49db 1795 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x49fb 1796 #define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc 1797 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc 1798 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc 1799 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c 1800 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c 1801 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c 1802 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c 1803 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c 1804 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x49dc 1805 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x49fc 1806 #define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd 1807 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd 1808 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd 1809 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d 1810 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d 1811 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d 1812 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d 1813 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d 1814 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x49dd 1815 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x49fd 1816 #define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de 1817 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de 1818 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe 1819 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e 1820 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e 1821 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e 1822 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e 1823 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e 1824 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x49de 1825 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x49fe 1826 #define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df 1827 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df 1828 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff 1829 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f 1830 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f 1831 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f 1832 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f 1833 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f 1834 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x49df 1835 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x49ff 1836 #define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 1837 #define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 1838 #define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 1839 #define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 1840 #define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 1841 #define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 1842 #define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a 1843 #define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b 1844 #define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c 1845 #define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d 1846 #define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e 1847 #define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f 1848 #define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 1849 #define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 1850 #define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 1851 #define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 1852 #define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 1853 #define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 1854 #define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 1855 #define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 1856 #define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 1857 #define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 1858 #define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a 1859 #define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b 1860 #define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c 1861 #define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d 1862 #define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e 1863 #define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f 1864 #define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 1865 #define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 1866 #define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 1867 #define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 1868 #define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 1869 #define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 1870 #define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 1871 #define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 1872 #define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 1873 #define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 1874 #define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa 1875 #define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab 1876 #define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac 1877 #define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad 1878 #define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae 1879 #define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf 1880 #define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 1881 #define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 1882 #define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 1883 #define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 1884 #define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 1885 #define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 1886 #define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 1887 #define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 1888 #define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 1889 #define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 1890 #define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba 1891 #define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb 1892 #define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc 1893 #define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd 1894 #define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe 1895 #define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf 1896 #define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 1897 #define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 1898 #define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 1899 #define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 1900 #define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 1901 #define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 1902 #define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 1903 #define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 1904 #define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 1905 #define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 1906 #define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca 1907 #define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb 1908 #define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc 1909 #define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd 1910 #define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace 1911 #define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf 1912 #define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 1913 #define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 1914 #define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 1915 #define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 1916 #define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 1917 #define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 1918 #define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 1919 #define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 1920 #define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 1921 #define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 1922 #define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada 1923 #define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb 1924 #define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc 1925 #define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add 1926 #define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade 1927 #define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf 1928 #define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 1929 #define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 1930 #define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 1931 #define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 1932 #define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 1933 #define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 1934 #define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 1935 #define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 1936 #define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 1937 #define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 1938 #define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea 1939 #define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb 1940 #define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec 1941 #define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed 1942 #define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee 1943 #define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef 1944 #define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 1945 #define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 1946 #define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 1947 #define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 1948 #define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 1949 #define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 1950 #define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 1951 #define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 1952 #define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 1953 #define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 1954 #define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa 1955 #define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb 1956 #define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc 1957 #define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd 1958 #define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe 1959 #define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff 1960 #define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 1961 #define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 1962 #define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 1963 #define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 1964 #define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 1965 #define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 1966 #define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 1967 #define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 1968 #define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 1969 #define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 1970 #define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a 1971 #define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b 1972 #define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c 1973 #define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d 1974 #define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e 1975 #define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f 1976 #define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 1977 #define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 1978 #define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 1979 #define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 1980 #define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 1981 #define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 1982 #define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 1983 #define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 1984 #define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 1985 #define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 1986 #define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a 1987 #define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b 1988 #define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c 1989 #define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d 1990 #define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e 1991 #define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f 1992 #define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 1993 #define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 1994 #define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 1995 #define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 1996 #define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 1997 #define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 1998 #define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 1999 #define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 2000 #define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 2001 #define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 2002 #define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a 2003 #define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b 2004 #define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c 2005 #define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d 2006 #define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e 2007 #define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f 2008 #define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 2009 #define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 2010 #define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 2011 #define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 2012 #define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 2013 #define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 2014 #define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 2015 #define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 2016 #define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 2017 #define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 2018 #define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a 2019 #define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b 2020 #define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c 2021 #define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d 2022 #define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e 2023 #define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f 2024 #define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 2025 #define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 2026 #define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 2027 #define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 2028 #define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 2029 #define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 2030 #define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 2031 #define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 2032 #define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 2033 #define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 2034 #define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a 2035 #define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b 2036 #define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c 2037 #define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d 2038 #define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e 2039 #define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f 2040 #define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 2041 #define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 2042 #define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 2043 #define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 2044 #define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 2045 #define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 2046 #define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 2047 #define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 2048 #define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 2049 #define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 2050 #define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a 2051 #define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b 2052 #define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c 2053 #define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d 2054 #define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e 2055 #define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f 2056 #define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 2057 #define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 2058 #define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 2059 #define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 2060 #define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 2061 #define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 2062 #define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 2063 #define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 2064 #define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 2065 #define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 2066 #define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a 2067 #define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b 2068 #define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c 2069 #define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d 2070 #define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e 2071 #define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f 2072 #define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 2073 #define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 2074 #define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 2075 #define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 2076 #define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 2077 #define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 2078 #define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 2079 #define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 2080 #define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 2081 #define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 2082 #define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a 2083 #define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b 2084 #define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c 2085 #define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d 2086 #define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e 2087 #define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f 2088 #define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 2089 #define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 2090 #define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 2091 #define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 2092 #define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 2093 #define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 2094 #define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 2095 #define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 2096 #define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 2097 #define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 2098 #define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a 2099 #define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b 2100 #define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c 2101 #define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d 2102 #define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e 2103 #define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f 2104 #define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 2105 #define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 2106 #define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 2107 #define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 2108 #define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 2109 #define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 2110 #define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 2111 #define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 2112 #define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 2113 #define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 2114 #define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a 2115 #define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b 2116 #define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c 2117 #define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d 2118 #define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e 2119 #define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f 2120 #define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 2121 #define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 2122 #define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 2123 #define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 2124 #define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 2125 #define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 2126 #define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 2127 #define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 2128 #define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 2129 #define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 2130 #define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa 2131 #define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab 2132 #define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac 2133 #define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad 2134 #define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae 2135 #define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf 2136 #define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 2137 #define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 2138 #define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 2139 #define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 2140 #define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 2141 #define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 2142 #define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 2143 #define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 2144 #define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 2145 #define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 2146 #define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba 2147 #define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb 2148 #define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc 2149 #define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd 2150 #define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe 2151 #define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf 2152 #define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 2153 #define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 2154 #define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 2155 #define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 2156 #define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 2157 #define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 2158 #define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 2159 #define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 2160 #define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 2161 #define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 2162 #define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca 2163 #define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb 2164 #define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc 2165 #define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd 2166 #define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce 2167 #define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf 2168 #define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 2169 #define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 2170 #define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 2171 #define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 2172 #define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 2173 #define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 2174 #define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 2175 #define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 2176 #define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 2177 #define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 2178 #define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda 2179 #define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb 2180 #define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc 2181 #define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd 2182 #define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde 2183 #define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf 2184 #define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 2185 #define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 2186 #define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 2187 #define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 2188 #define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 2189 #define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 2190 #define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 2191 #define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 2192 #define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 2193 #define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 2194 #define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea 2195 #define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb 2196 #define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec 2197 #define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed 2198 #define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee 2199 #define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef 2200 #define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 2201 #define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 2202 #define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 2203 #define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 2204 #define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 2205 #define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 2206 #define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 2207 #define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 2208 #define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 2209 #define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 2210 #define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa 2211 #define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb 2212 #define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc 2213 #define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd 2214 #define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe 2215 #define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff 2216 #define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 2217 #define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 2218 #define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a 2219 #define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b 2220 #define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c 2221 #define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d 2222 #define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e 2223 #define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f 2224 #define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 2225 #define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 2226 #define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 2227 #define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 2228 #define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 2229 #define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 2230 #define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 2231 #define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 2232 #define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 2233 #define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 2234 #define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa 2235 #define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab 2236 #define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac 2237 #define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad 2238 #define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae 2239 #define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf 2240 #define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 2241 #define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 2242 #define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 2243 #define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 2244 #define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 2245 #define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 2246 #define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 2247 #define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 2248 #define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 2249 #define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 2250 #define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba 2251 #define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb 2252 #define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc 2253 #define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd 2254 #define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe 2255 #define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf 2256 #define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 2257 #define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 2258 #define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 2259 #define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 2260 #define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 2261 #define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 2262 #define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 2263 #define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 2264 #define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 2265 #define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 2266 #define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca 2267 #define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb 2268 #define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc 2269 #define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd 2270 #define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce 2271 #define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf 2272 #define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 2273 #define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 2274 #define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 2275 #define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 2276 #define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 2277 #define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 2278 #define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 2279 #define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 2280 #define mmGRPH_ENABLE 0x1a00 2281 #define mmDCP0_GRPH_ENABLE 0x1a00 2282 #define mmDCP1_GRPH_ENABLE 0x1c00 2283 #define mmDCP2_GRPH_ENABLE 0x1e00 2284 #define mmDCP3_GRPH_ENABLE 0x4000 2285 #define mmDCP4_GRPH_ENABLE 0x4200 2286 #define mmDCP5_GRPH_ENABLE 0x4400 2287 #define mmGRPH_CONTROL 0x1a01 2288 #define mmDCP0_GRPH_CONTROL 0x1a01 2289 #define mmDCP1_GRPH_CONTROL 0x1c01 2290 #define mmDCP2_GRPH_CONTROL 0x1e01 2291 #define mmDCP3_GRPH_CONTROL 0x4001 2292 #define mmDCP4_GRPH_CONTROL 0x4201 2293 #define mmDCP5_GRPH_CONTROL 0x4401 2294 #define mmGRPH_LUT_10BIT_BYPASS 0x1a02 2295 #define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 2296 #define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 2297 #define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 2298 #define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 2299 #define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 2300 #define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 2301 #define mmGRPH_SWAP_CNTL 0x1a03 2302 #define mmDCP0_GRPH_SWAP_CNTL 0x1a03 2303 #define mmDCP1_GRPH_SWAP_CNTL 0x1c03 2304 #define mmDCP2_GRPH_SWAP_CNTL 0x1e03 2305 #define mmDCP3_GRPH_SWAP_CNTL 0x4003 2306 #define mmDCP4_GRPH_SWAP_CNTL 0x4203 2307 #define mmDCP5_GRPH_SWAP_CNTL 0x4403 2308 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 2309 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 2310 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 2311 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 2312 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 2313 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 2314 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 2315 #define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 2316 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 2317 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 2318 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 2319 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 2320 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 2321 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 2322 #define mmGRPH_PITCH 0x1a06 2323 #define mmDCP0_GRPH_PITCH 0x1a06 2324 #define mmDCP1_GRPH_PITCH 0x1c06 2325 #define mmDCP2_GRPH_PITCH 0x1e06 2326 #define mmDCP3_GRPH_PITCH 0x4006 2327 #define mmDCP4_GRPH_PITCH 0x4206 2328 #define mmDCP5_GRPH_PITCH 0x4406 2329 #define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2330 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2331 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 2332 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 2333 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 2334 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 2335 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 2336 #define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2337 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2338 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 2339 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 2340 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 2341 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 2342 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 2343 #define mmGRPH_SURFACE_OFFSET_X 0x1a09 2344 #define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 2345 #define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 2346 #define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 2347 #define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 2348 #define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 2349 #define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 2350 #define mmGRPH_SURFACE_OFFSET_Y 0x1a0a 2351 #define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a 2352 #define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a 2353 #define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a 2354 #define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a 2355 #define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a 2356 #define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a 2357 #define mmGRPH_X_START 0x1a0b 2358 #define mmDCP0_GRPH_X_START 0x1a0b 2359 #define mmDCP1_GRPH_X_START 0x1c0b 2360 #define mmDCP2_GRPH_X_START 0x1e0b 2361 #define mmDCP3_GRPH_X_START 0x400b 2362 #define mmDCP4_GRPH_X_START 0x420b 2363 #define mmDCP5_GRPH_X_START 0x440b 2364 #define mmGRPH_Y_START 0x1a0c 2365 #define mmDCP0_GRPH_Y_START 0x1a0c 2366 #define mmDCP1_GRPH_Y_START 0x1c0c 2367 #define mmDCP2_GRPH_Y_START 0x1e0c 2368 #define mmDCP3_GRPH_Y_START 0x400c 2369 #define mmDCP4_GRPH_Y_START 0x420c 2370 #define mmDCP5_GRPH_Y_START 0x440c 2371 #define mmGRPH_X_END 0x1a0d 2372 #define mmDCP0_GRPH_X_END 0x1a0d 2373 #define mmDCP1_GRPH_X_END 0x1c0d 2374 #define mmDCP2_GRPH_X_END 0x1e0d 2375 #define mmDCP3_GRPH_X_END 0x400d 2376 #define mmDCP4_GRPH_X_END 0x420d 2377 #define mmDCP5_GRPH_X_END 0x440d 2378 #define mmGRPH_Y_END 0x1a0e 2379 #define mmDCP0_GRPH_Y_END 0x1a0e 2380 #define mmDCP1_GRPH_Y_END 0x1c0e 2381 #define mmDCP2_GRPH_Y_END 0x1e0e 2382 #define mmDCP3_GRPH_Y_END 0x400e 2383 #define mmDCP4_GRPH_Y_END 0x420e 2384 #define mmDCP5_GRPH_Y_END 0x440e 2385 #define mmINPUT_GAMMA_CONTROL 0x1a10 2386 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 2387 #define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 2388 #define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 2389 #define mmDCP3_INPUT_GAMMA_CONTROL 0x4010 2390 #define mmDCP4_INPUT_GAMMA_CONTROL 0x4210 2391 #define mmDCP5_INPUT_GAMMA_CONTROL 0x4410 2392 #define mmGRPH_UPDATE 0x1a11 2393 #define mmDCP0_GRPH_UPDATE 0x1a11 2394 #define mmDCP1_GRPH_UPDATE 0x1c11 2395 #define mmDCP2_GRPH_UPDATE 0x1e11 2396 #define mmDCP3_GRPH_UPDATE 0x4011 2397 #define mmDCP4_GRPH_UPDATE 0x4211 2398 #define mmDCP5_GRPH_UPDATE 0x4411 2399 #define mmGRPH_FLIP_CONTROL 0x1a12 2400 #define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 2401 #define mmDCP1_GRPH_FLIP_CONTROL 0x1c12 2402 #define mmDCP2_GRPH_FLIP_CONTROL 0x1e12 2403 #define mmDCP3_GRPH_FLIP_CONTROL 0x4012 2404 #define mmDCP4_GRPH_FLIP_CONTROL 0x4212 2405 #define mmDCP5_GRPH_FLIP_CONTROL 0x4412 2406 #define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 2407 #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 2408 #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 2409 #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 2410 #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 2411 #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 2412 #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 2413 #define mmGRPH_DFQ_CONTROL 0x1a14 2414 #define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 2415 #define mmDCP1_GRPH_DFQ_CONTROL 0x1c14 2416 #define mmDCP2_GRPH_DFQ_CONTROL 0x1e14 2417 #define mmDCP3_GRPH_DFQ_CONTROL 0x4014 2418 #define mmDCP4_GRPH_DFQ_CONTROL 0x4214 2419 #define mmDCP5_GRPH_DFQ_CONTROL 0x4414 2420 #define mmGRPH_DFQ_STATUS 0x1a15 2421 #define mmDCP0_GRPH_DFQ_STATUS 0x1a15 2422 #define mmDCP1_GRPH_DFQ_STATUS 0x1c15 2423 #define mmDCP2_GRPH_DFQ_STATUS 0x1e15 2424 #define mmDCP3_GRPH_DFQ_STATUS 0x4015 2425 #define mmDCP4_GRPH_DFQ_STATUS 0x4215 2426 #define mmDCP5_GRPH_DFQ_STATUS 0x4415 2427 #define mmGRPH_INTERRUPT_STATUS 0x1a16 2428 #define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 2429 #define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 2430 #define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 2431 #define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 2432 #define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 2433 #define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 2434 #define mmGRPH_INTERRUPT_CONTROL 0x1a17 2435 #define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 2436 #define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 2437 #define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 2438 #define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 2439 #define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 2440 #define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 2441 #define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 2442 #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 2443 #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 2444 #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 2445 #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 2446 #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 2447 #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 2448 #define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 2449 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 2450 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 2451 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 2452 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 2453 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 2454 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 2455 #define mmGRPH_COMPRESS_PITCH 0x1a1a 2456 #define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a 2457 #define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a 2458 #define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a 2459 #define mmDCP3_GRPH_COMPRESS_PITCH 0x401a 2460 #define mmDCP4_GRPH_COMPRESS_PITCH 0x421a 2461 #define mmDCP5_GRPH_COMPRESS_PITCH 0x441a 2462 #define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b 2463 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b 2464 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b 2465 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b 2466 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b 2467 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b 2468 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b 2469 #define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c 2470 #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c 2471 #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c 2472 #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c 2473 #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c 2474 #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c 2475 #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c 2476 #define mmPRESCALE_GRPH_CONTROL 0x1a2d 2477 #define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d 2478 #define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d 2479 #define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d 2480 #define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d 2481 #define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d 2482 #define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d 2483 #define mmPRESCALE_VALUES_GRPH_R 0x1a2e 2484 #define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e 2485 #define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e 2486 #define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e 2487 #define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e 2488 #define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e 2489 #define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e 2490 #define mmPRESCALE_VALUES_GRPH_G 0x1a2f 2491 #define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f 2492 #define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f 2493 #define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f 2494 #define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f 2495 #define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f 2496 #define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f 2497 #define mmPRESCALE_VALUES_GRPH_B 0x1a30 2498 #define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 2499 #define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 2500 #define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 2501 #define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 2502 #define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 2503 #define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 2504 #define mmINPUT_CSC_CONTROL 0x1a35 2505 #define mmDCP0_INPUT_CSC_CONTROL 0x1a35 2506 #define mmDCP1_INPUT_CSC_CONTROL 0x1c35 2507 #define mmDCP2_INPUT_CSC_CONTROL 0x1e35 2508 #define mmDCP3_INPUT_CSC_CONTROL 0x4035 2509 #define mmDCP4_INPUT_CSC_CONTROL 0x4235 2510 #define mmDCP5_INPUT_CSC_CONTROL 0x4435 2511 #define mmINPUT_CSC_C11_C12 0x1a36 2512 #define mmDCP0_INPUT_CSC_C11_C12 0x1a36 2513 #define mmDCP1_INPUT_CSC_C11_C12 0x1c36 2514 #define mmDCP2_INPUT_CSC_C11_C12 0x1e36 2515 #define mmDCP3_INPUT_CSC_C11_C12 0x4036 2516 #define mmDCP4_INPUT_CSC_C11_C12 0x4236 2517 #define mmDCP5_INPUT_CSC_C11_C12 0x4436 2518 #define mmINPUT_CSC_C13_C14 0x1a37 2519 #define mmDCP0_INPUT_CSC_C13_C14 0x1a37 2520 #define mmDCP1_INPUT_CSC_C13_C14 0x1c37 2521 #define mmDCP2_INPUT_CSC_C13_C14 0x1e37 2522 #define mmDCP3_INPUT_CSC_C13_C14 0x4037 2523 #define mmDCP4_INPUT_CSC_C13_C14 0x4237 2524 #define mmDCP5_INPUT_CSC_C13_C14 0x4437 2525 #define mmINPUT_CSC_C21_C22 0x1a38 2526 #define mmDCP0_INPUT_CSC_C21_C22 0x1a38 2527 #define mmDCP1_INPUT_CSC_C21_C22 0x1c38 2528 #define mmDCP2_INPUT_CSC_C21_C22 0x1e38 2529 #define mmDCP3_INPUT_CSC_C21_C22 0x4038 2530 #define mmDCP4_INPUT_CSC_C21_C22 0x4238 2531 #define mmDCP5_INPUT_CSC_C21_C22 0x4438 2532 #define mmINPUT_CSC_C23_C24 0x1a39 2533 #define mmDCP0_INPUT_CSC_C23_C24 0x1a39 2534 #define mmDCP1_INPUT_CSC_C23_C24 0x1c39 2535 #define mmDCP2_INPUT_CSC_C23_C24 0x1e39 2536 #define mmDCP3_INPUT_CSC_C23_C24 0x4039 2537 #define mmDCP4_INPUT_CSC_C23_C24 0x4239 2538 #define mmDCP5_INPUT_CSC_C23_C24 0x4439 2539 #define mmINPUT_CSC_C31_C32 0x1a3a 2540 #define mmDCP0_INPUT_CSC_C31_C32 0x1a3a 2541 #define mmDCP1_INPUT_CSC_C31_C32 0x1c3a 2542 #define mmDCP2_INPUT_CSC_C31_C32 0x1e3a 2543 #define mmDCP3_INPUT_CSC_C31_C32 0x403a 2544 #define mmDCP4_INPUT_CSC_C31_C32 0x423a 2545 #define mmDCP5_INPUT_CSC_C31_C32 0x443a 2546 #define mmINPUT_CSC_C33_C34 0x1a3b 2547 #define mmDCP0_INPUT_CSC_C33_C34 0x1a3b 2548 #define mmDCP1_INPUT_CSC_C33_C34 0x1c3b 2549 #define mmDCP2_INPUT_CSC_C33_C34 0x1e3b 2550 #define mmDCP3_INPUT_CSC_C33_C34 0x403b 2551 #define mmDCP4_INPUT_CSC_C33_C34 0x423b 2552 #define mmDCP5_INPUT_CSC_C33_C34 0x443b 2553 #define mmOUTPUT_CSC_CONTROL 0x1a3c 2554 #define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c 2555 #define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c 2556 #define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c 2557 #define mmDCP3_OUTPUT_CSC_CONTROL 0x403c 2558 #define mmDCP4_OUTPUT_CSC_CONTROL 0x423c 2559 #define mmDCP5_OUTPUT_CSC_CONTROL 0x443c 2560 #define mmOUTPUT_CSC_C11_C12 0x1a3d 2561 #define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d 2562 #define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d 2563 #define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d 2564 #define mmDCP3_OUTPUT_CSC_C11_C12 0x403d 2565 #define mmDCP4_OUTPUT_CSC_C11_C12 0x423d 2566 #define mmDCP5_OUTPUT_CSC_C11_C12 0x443d 2567 #define mmOUTPUT_CSC_C13_C14 0x1a3e 2568 #define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e 2569 #define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e 2570 #define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e 2571 #define mmDCP3_OUTPUT_CSC_C13_C14 0x403e 2572 #define mmDCP4_OUTPUT_CSC_C13_C14 0x423e 2573 #define mmDCP5_OUTPUT_CSC_C13_C14 0x443e 2574 #define mmOUTPUT_CSC_C21_C22 0x1a3f 2575 #define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f 2576 #define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f 2577 #define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f 2578 #define mmDCP3_OUTPUT_CSC_C21_C22 0x403f 2579 #define mmDCP4_OUTPUT_CSC_C21_C22 0x423f 2580 #define mmDCP5_OUTPUT_CSC_C21_C22 0x443f 2581 #define mmOUTPUT_CSC_C23_C24 0x1a40 2582 #define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 2583 #define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 2584 #define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 2585 #define mmDCP3_OUTPUT_CSC_C23_C24 0x4040 2586 #define mmDCP4_OUTPUT_CSC_C23_C24 0x4240 2587 #define mmDCP5_OUTPUT_CSC_C23_C24 0x4440 2588 #define mmOUTPUT_CSC_C31_C32 0x1a41 2589 #define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 2590 #define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 2591 #define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 2592 #define mmDCP3_OUTPUT_CSC_C31_C32 0x4041 2593 #define mmDCP4_OUTPUT_CSC_C31_C32 0x4241 2594 #define mmDCP5_OUTPUT_CSC_C31_C32 0x4441 2595 #define mmOUTPUT_CSC_C33_C34 0x1a42 2596 #define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 2597 #define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 2598 #define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 2599 #define mmDCP3_OUTPUT_CSC_C33_C34 0x4042 2600 #define mmDCP4_OUTPUT_CSC_C33_C34 0x4242 2601 #define mmDCP5_OUTPUT_CSC_C33_C34 0x4442 2602 #define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 2603 #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 2604 #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 2605 #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 2606 #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 2607 #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 2608 #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 2609 #define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 2610 #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 2611 #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 2612 #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 2613 #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 2614 #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 2615 #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 2616 #define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 2617 #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 2618 #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 2619 #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 2620 #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 2621 #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 2622 #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 2623 #define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 2624 #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 2625 #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 2626 #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 2627 #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 2628 #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 2629 #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 2630 #define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 2631 #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 2632 #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 2633 #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 2634 #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 2635 #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 2636 #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 2637 #define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 2638 #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 2639 #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 2640 #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 2641 #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 2642 #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 2643 #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 2644 #define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 2645 #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 2646 #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 2647 #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 2648 #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 2649 #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 2650 #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 2651 #define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a 2652 #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a 2653 #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a 2654 #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a 2655 #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a 2656 #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a 2657 #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a 2658 #define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b 2659 #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b 2660 #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b 2661 #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b 2662 #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b 2663 #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b 2664 #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b 2665 #define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c 2666 #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c 2667 #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c 2668 #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c 2669 #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c 2670 #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c 2671 #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c 2672 #define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d 2673 #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d 2674 #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d 2675 #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d 2676 #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d 2677 #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d 2678 #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d 2679 #define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e 2680 #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e 2681 #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e 2682 #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e 2683 #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e 2684 #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e 2685 #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e 2686 #define mmDENORM_CONTROL 0x1a50 2687 #define mmDCP0_DENORM_CONTROL 0x1a50 2688 #define mmDCP1_DENORM_CONTROL 0x1c50 2689 #define mmDCP2_DENORM_CONTROL 0x1e50 2690 #define mmDCP3_DENORM_CONTROL 0x4050 2691 #define mmDCP4_DENORM_CONTROL 0x4250 2692 #define mmDCP5_DENORM_CONTROL 0x4450 2693 #define mmOUT_ROUND_CONTROL 0x1a51 2694 #define mmDCP0_OUT_ROUND_CONTROL 0x1a51 2695 #define mmDCP1_OUT_ROUND_CONTROL 0x1c51 2696 #define mmDCP2_OUT_ROUND_CONTROL 0x1e51 2697 #define mmDCP3_OUT_ROUND_CONTROL 0x4051 2698 #define mmDCP4_OUT_ROUND_CONTROL 0x4251 2699 #define mmDCP5_OUT_ROUND_CONTROL 0x4451 2700 #define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 2701 #define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 2702 #define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 2703 #define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 2704 #define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 2705 #define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 2706 #define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 2707 #define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c 2708 #define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c 2709 #define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c 2710 #define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c 2711 #define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c 2712 #define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c 2713 #define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c 2714 #define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d 2715 #define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d 2716 #define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d 2717 #define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d 2718 #define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d 2719 #define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d 2720 #define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d 2721 #define mmKEY_CONTROL 0x1a53 2722 #define mmDCP0_KEY_CONTROL 0x1a53 2723 #define mmDCP1_KEY_CONTROL 0x1c53 2724 #define mmDCP2_KEY_CONTROL 0x1e53 2725 #define mmDCP3_KEY_CONTROL 0x4053 2726 #define mmDCP4_KEY_CONTROL 0x4253 2727 #define mmDCP5_KEY_CONTROL 0x4453 2728 #define mmKEY_RANGE_ALPHA 0x1a54 2729 #define mmDCP0_KEY_RANGE_ALPHA 0x1a54 2730 #define mmDCP1_KEY_RANGE_ALPHA 0x1c54 2731 #define mmDCP2_KEY_RANGE_ALPHA 0x1e54 2732 #define mmDCP3_KEY_RANGE_ALPHA 0x4054 2733 #define mmDCP4_KEY_RANGE_ALPHA 0x4254 2734 #define mmDCP5_KEY_RANGE_ALPHA 0x4454 2735 #define mmKEY_RANGE_RED 0x1a55 2736 #define mmDCP0_KEY_RANGE_RED 0x1a55 2737 #define mmDCP1_KEY_RANGE_RED 0x1c55 2738 #define mmDCP2_KEY_RANGE_RED 0x1e55 2739 #define mmDCP3_KEY_RANGE_RED 0x4055 2740 #define mmDCP4_KEY_RANGE_RED 0x4255 2741 #define mmDCP5_KEY_RANGE_RED 0x4455 2742 #define mmKEY_RANGE_GREEN 0x1a56 2743 #define mmDCP0_KEY_RANGE_GREEN 0x1a56 2744 #define mmDCP1_KEY_RANGE_GREEN 0x1c56 2745 #define mmDCP2_KEY_RANGE_GREEN 0x1e56 2746 #define mmDCP3_KEY_RANGE_GREEN 0x4056 2747 #define mmDCP4_KEY_RANGE_GREEN 0x4256 2748 #define mmDCP5_KEY_RANGE_GREEN 0x4456 2749 #define mmKEY_RANGE_BLUE 0x1a57 2750 #define mmDCP0_KEY_RANGE_BLUE 0x1a57 2751 #define mmDCP1_KEY_RANGE_BLUE 0x1c57 2752 #define mmDCP2_KEY_RANGE_BLUE 0x1e57 2753 #define mmDCP3_KEY_RANGE_BLUE 0x4057 2754 #define mmDCP4_KEY_RANGE_BLUE 0x4257 2755 #define mmDCP5_KEY_RANGE_BLUE 0x4457 2756 #define mmDEGAMMA_CONTROL 0x1a58 2757 #define mmDCP0_DEGAMMA_CONTROL 0x1a58 2758 #define mmDCP1_DEGAMMA_CONTROL 0x1c58 2759 #define mmDCP2_DEGAMMA_CONTROL 0x1e58 2760 #define mmDCP3_DEGAMMA_CONTROL 0x4058 2761 #define mmDCP4_DEGAMMA_CONTROL 0x4258 2762 #define mmDCP5_DEGAMMA_CONTROL 0x4458 2763 #define mmGAMUT_REMAP_CONTROL 0x1a59 2764 #define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 2765 #define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 2766 #define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 2767 #define mmDCP3_GAMUT_REMAP_CONTROL 0x4059 2768 #define mmDCP4_GAMUT_REMAP_CONTROL 0x4259 2769 #define mmDCP5_GAMUT_REMAP_CONTROL 0x4459 2770 #define mmGAMUT_REMAP_C11_C12 0x1a5a 2771 #define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a 2772 #define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a 2773 #define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a 2774 #define mmDCP3_GAMUT_REMAP_C11_C12 0x405a 2775 #define mmDCP4_GAMUT_REMAP_C11_C12 0x425a 2776 #define mmDCP5_GAMUT_REMAP_C11_C12 0x445a 2777 #define mmGAMUT_REMAP_C13_C14 0x1a5b 2778 #define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b 2779 #define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b 2780 #define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b 2781 #define mmDCP3_GAMUT_REMAP_C13_C14 0x405b 2782 #define mmDCP4_GAMUT_REMAP_C13_C14 0x425b 2783 #define mmDCP5_GAMUT_REMAP_C13_C14 0x445b 2784 #define mmGAMUT_REMAP_C21_C22 0x1a5c 2785 #define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c 2786 #define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c 2787 #define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c 2788 #define mmDCP3_GAMUT_REMAP_C21_C22 0x405c 2789 #define mmDCP4_GAMUT_REMAP_C21_C22 0x425c 2790 #define mmDCP5_GAMUT_REMAP_C21_C22 0x445c 2791 #define mmGAMUT_REMAP_C23_C24 0x1a5d 2792 #define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d 2793 #define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d 2794 #define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d 2795 #define mmDCP3_GAMUT_REMAP_C23_C24 0x405d 2796 #define mmDCP4_GAMUT_REMAP_C23_C24 0x425d 2797 #define mmDCP5_GAMUT_REMAP_C23_C24 0x445d 2798 #define mmGAMUT_REMAP_C31_C32 0x1a5e 2799 #define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e 2800 #define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e 2801 #define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e 2802 #define mmDCP3_GAMUT_REMAP_C31_C32 0x405e 2803 #define mmDCP4_GAMUT_REMAP_C31_C32 0x425e 2804 #define mmDCP5_GAMUT_REMAP_C31_C32 0x445e 2805 #define mmGAMUT_REMAP_C33_C34 0x1a5f 2806 #define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f 2807 #define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f 2808 #define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f 2809 #define mmDCP3_GAMUT_REMAP_C33_C34 0x405f 2810 #define mmDCP4_GAMUT_REMAP_C33_C34 0x425f 2811 #define mmDCP5_GAMUT_REMAP_C33_C34 0x445f 2812 #define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 2813 #define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 2814 #define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 2815 #define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 2816 #define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 2817 #define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 2818 #define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 2819 #define mmDCP_FP_CONVERTED_FIELD 0x1a65 2820 #define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 2821 #define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 2822 #define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 2823 #define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 2824 #define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 2825 #define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 2826 #define mmCUR_CONTROL 0x1a66 2827 #define mmDCP0_CUR_CONTROL 0x1a66 2828 #define mmDCP1_CUR_CONTROL 0x1c66 2829 #define mmDCP2_CUR_CONTROL 0x1e66 2830 #define mmDCP3_CUR_CONTROL 0x4066 2831 #define mmDCP4_CUR_CONTROL 0x4266 2832 #define mmDCP5_CUR_CONTROL 0x4466 2833 #define mmCUR_SURFACE_ADDRESS 0x1a67 2834 #define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 2835 #define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 2836 #define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 2837 #define mmDCP3_CUR_SURFACE_ADDRESS 0x4067 2838 #define mmDCP4_CUR_SURFACE_ADDRESS 0x4267 2839 #define mmDCP5_CUR_SURFACE_ADDRESS 0x4467 2840 #define mmCUR_SIZE 0x1a68 2841 #define mmDCP0_CUR_SIZE 0x1a68 2842 #define mmDCP1_CUR_SIZE 0x1c68 2843 #define mmDCP2_CUR_SIZE 0x1e68 2844 #define mmDCP3_CUR_SIZE 0x4068 2845 #define mmDCP4_CUR_SIZE 0x4268 2846 #define mmDCP5_CUR_SIZE 0x4468 2847 #define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 2848 #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 2849 #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 2850 #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 2851 #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 2852 #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 2853 #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 2854 #define mmCUR_POSITION 0x1a6a 2855 #define mmDCP0_CUR_POSITION 0x1a6a 2856 #define mmDCP1_CUR_POSITION 0x1c6a 2857 #define mmDCP2_CUR_POSITION 0x1e6a 2858 #define mmDCP3_CUR_POSITION 0x406a 2859 #define mmDCP4_CUR_POSITION 0x426a 2860 #define mmDCP5_CUR_POSITION 0x446a 2861 #define mmCUR_HOT_SPOT 0x1a6b 2862 #define mmDCP0_CUR_HOT_SPOT 0x1a6b 2863 #define mmDCP1_CUR_HOT_SPOT 0x1c6b 2864 #define mmDCP2_CUR_HOT_SPOT 0x1e6b 2865 #define mmDCP3_CUR_HOT_SPOT 0x406b 2866 #define mmDCP4_CUR_HOT_SPOT 0x426b 2867 #define mmDCP5_CUR_HOT_SPOT 0x446b 2868 #define mmCUR_COLOR1 0x1a6c 2869 #define mmDCP0_CUR_COLOR1 0x1a6c 2870 #define mmDCP1_CUR_COLOR1 0x1c6c 2871 #define mmDCP2_CUR_COLOR1 0x1e6c 2872 #define mmDCP3_CUR_COLOR1 0x406c 2873 #define mmDCP4_CUR_COLOR1 0x426c 2874 #define mmDCP5_CUR_COLOR1 0x446c 2875 #define mmCUR_COLOR2 0x1a6d 2876 #define mmDCP0_CUR_COLOR2 0x1a6d 2877 #define mmDCP1_CUR_COLOR2 0x1c6d 2878 #define mmDCP2_CUR_COLOR2 0x1e6d 2879 #define mmDCP3_CUR_COLOR2 0x406d 2880 #define mmDCP4_CUR_COLOR2 0x426d 2881 #define mmDCP5_CUR_COLOR2 0x446d 2882 #define mmCUR_UPDATE 0x1a6e 2883 #define mmDCP0_CUR_UPDATE 0x1a6e 2884 #define mmDCP1_CUR_UPDATE 0x1c6e 2885 #define mmDCP2_CUR_UPDATE 0x1e6e 2886 #define mmDCP3_CUR_UPDATE 0x406e 2887 #define mmDCP4_CUR_UPDATE 0x426e 2888 #define mmDCP5_CUR_UPDATE 0x446e 2889 #define mmCUR_REQUEST_FILTER_CNTL 0x1a99 2890 #define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 2891 #define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 2892 #define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 2893 #define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 2894 #define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 2895 #define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 2896 #define mmCUR_STEREO_CONTROL 0x1a9a 2897 #define mmDCP0_CUR_STEREO_CONTROL 0x1a9a 2898 #define mmDCP1_CUR_STEREO_CONTROL 0x1c9a 2899 #define mmDCP2_CUR_STEREO_CONTROL 0x1e9a 2900 #define mmDCP3_CUR_STEREO_CONTROL 0x409a 2901 #define mmDCP4_CUR_STEREO_CONTROL 0x429a 2902 #define mmDCP5_CUR_STEREO_CONTROL 0x449a 2903 #define mmDC_LUT_RW_MODE 0x1a78 2904 #define mmDCP0_DC_LUT_RW_MODE 0x1a78 2905 #define mmDCP1_DC_LUT_RW_MODE 0x1c78 2906 #define mmDCP2_DC_LUT_RW_MODE 0x1e78 2907 #define mmDCP3_DC_LUT_RW_MODE 0x4078 2908 #define mmDCP4_DC_LUT_RW_MODE 0x4278 2909 #define mmDCP5_DC_LUT_RW_MODE 0x4478 2910 #define mmDC_LUT_RW_INDEX 0x1a79 2911 #define mmDCP0_DC_LUT_RW_INDEX 0x1a79 2912 #define mmDCP1_DC_LUT_RW_INDEX 0x1c79 2913 #define mmDCP2_DC_LUT_RW_INDEX 0x1e79 2914 #define mmDCP3_DC_LUT_RW_INDEX 0x4079 2915 #define mmDCP4_DC_LUT_RW_INDEX 0x4279 2916 #define mmDCP5_DC_LUT_RW_INDEX 0x4479 2917 #define mmDC_LUT_SEQ_COLOR 0x1a7a 2918 #define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a 2919 #define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a 2920 #define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a 2921 #define mmDCP3_DC_LUT_SEQ_COLOR 0x407a 2922 #define mmDCP4_DC_LUT_SEQ_COLOR 0x427a 2923 #define mmDCP5_DC_LUT_SEQ_COLOR 0x447a 2924 #define mmDC_LUT_PWL_DATA 0x1a7b 2925 #define mmDCP0_DC_LUT_PWL_DATA 0x1a7b 2926 #define mmDCP1_DC_LUT_PWL_DATA 0x1c7b 2927 #define mmDCP2_DC_LUT_PWL_DATA 0x1e7b 2928 #define mmDCP3_DC_LUT_PWL_DATA 0x407b 2929 #define mmDCP4_DC_LUT_PWL_DATA 0x427b 2930 #define mmDCP5_DC_LUT_PWL_DATA 0x447b 2931 #define mmDC_LUT_30_COLOR 0x1a7c 2932 #define mmDCP0_DC_LUT_30_COLOR 0x1a7c 2933 #define mmDCP1_DC_LUT_30_COLOR 0x1c7c 2934 #define mmDCP2_DC_LUT_30_COLOR 0x1e7c 2935 #define mmDCP3_DC_LUT_30_COLOR 0x407c 2936 #define mmDCP4_DC_LUT_30_COLOR 0x427c 2937 #define mmDCP5_DC_LUT_30_COLOR 0x447c 2938 #define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d 2939 #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d 2940 #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d 2941 #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d 2942 #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d 2943 #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d 2944 #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d 2945 #define mmDC_LUT_WRITE_EN_MASK 0x1a7e 2946 #define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e 2947 #define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e 2948 #define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e 2949 #define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e 2950 #define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e 2951 #define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e 2952 #define mmDC_LUT_AUTOFILL 0x1a7f 2953 #define mmDCP0_DC_LUT_AUTOFILL 0x1a7f 2954 #define mmDCP1_DC_LUT_AUTOFILL 0x1c7f 2955 #define mmDCP2_DC_LUT_AUTOFILL 0x1e7f 2956 #define mmDCP3_DC_LUT_AUTOFILL 0x407f 2957 #define mmDCP4_DC_LUT_AUTOFILL 0x427f 2958 #define mmDCP5_DC_LUT_AUTOFILL 0x447f 2959 #define mmDC_LUT_CONTROL 0x1a80 2960 #define mmDCP0_DC_LUT_CONTROL 0x1a80 2961 #define mmDCP1_DC_LUT_CONTROL 0x1c80 2962 #define mmDCP2_DC_LUT_CONTROL 0x1e80 2963 #define mmDCP3_DC_LUT_CONTROL 0x4080 2964 #define mmDCP4_DC_LUT_CONTROL 0x4280 2965 #define mmDCP5_DC_LUT_CONTROL 0x4480 2966 #define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 2967 #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 2968 #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 2969 #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 2970 #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 2971 #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 2972 #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 2973 #define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 2974 #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 2975 #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 2976 #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 2977 #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 2978 #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 2979 #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 2980 #define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 2981 #define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 2982 #define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 2983 #define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 2984 #define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 2985 #define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 2986 #define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 2987 #define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 2988 #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 2989 #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 2990 #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 2991 #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 2992 #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 2993 #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 2994 #define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 2995 #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 2996 #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 2997 #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 2998 #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 2999 #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 3000 #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 3001 #define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 3002 #define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 3003 #define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 3004 #define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 3005 #define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 3006 #define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 3007 #define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 3008 #define mmDCP_CRC_CONTROL 0x1a87 3009 #define mmDCP0_DCP_CRC_CONTROL 0x1a87 3010 #define mmDCP1_DCP_CRC_CONTROL 0x1c87 3011 #define mmDCP2_DCP_CRC_CONTROL 0x1e87 3012 #define mmDCP3_DCP_CRC_CONTROL 0x4087 3013 #define mmDCP4_DCP_CRC_CONTROL 0x4287 3014 #define mmDCP5_DCP_CRC_CONTROL 0x4487 3015 #define mmDCP_CRC_MASK 0x1a88 3016 #define mmDCP0_DCP_CRC_MASK 0x1a88 3017 #define mmDCP1_DCP_CRC_MASK 0x1c88 3018 #define mmDCP2_DCP_CRC_MASK 0x1e88 3019 #define mmDCP3_DCP_CRC_MASK 0x4088 3020 #define mmDCP4_DCP_CRC_MASK 0x4288 3021 #define mmDCP5_DCP_CRC_MASK 0x4488 3022 #define mmDCP_CRC_CURRENT 0x1a89 3023 #define mmDCP0_DCP_CRC_CURRENT 0x1a89 3024 #define mmDCP1_DCP_CRC_CURRENT 0x1c89 3025 #define mmDCP2_DCP_CRC_CURRENT 0x1e89 3026 #define mmDCP3_DCP_CRC_CURRENT 0x4089 3027 #define mmDCP4_DCP_CRC_CURRENT 0x4289 3028 #define mmDCP5_DCP_CRC_CURRENT 0x4489 3029 #define mmDVMM_PTE_CONTROL 0x1a8a 3030 #define mmDCP0_DVMM_PTE_CONTROL 0x1a8a 3031 #define mmDCP1_DVMM_PTE_CONTROL 0x1c8a 3032 #define mmDCP2_DVMM_PTE_CONTROL 0x1e8a 3033 #define mmDCP3_DVMM_PTE_CONTROL 0x408a 3034 #define mmDCP4_DVMM_PTE_CONTROL 0x428a 3035 #define mmDCP5_DVMM_PTE_CONTROL 0x448a 3036 #define mmDCP_CRC_LAST 0x1a8b 3037 #define mmDCP0_DCP_CRC_LAST 0x1a8b 3038 #define mmDCP1_DCP_CRC_LAST 0x1c8b 3039 #define mmDCP2_DCP_CRC_LAST 0x1e8b 3040 #define mmDCP3_DCP_CRC_LAST 0x408b 3041 #define mmDCP4_DCP_CRC_LAST 0x428b 3042 #define mmDCP5_DCP_CRC_LAST 0x448b 3043 #define mmDVMM_PTE_ARB_CONTROL 0x1a8c 3044 #define mmDCP0_DVMM_PTE_ARB_CONTROL 0x1a8c 3045 #define mmDCP1_DVMM_PTE_ARB_CONTROL 0x1c8c 3046 #define mmDCP2_DVMM_PTE_ARB_CONTROL 0x1e8c 3047 #define mmDCP3_DVMM_PTE_ARB_CONTROL 0x408c 3048 #define mmDCP4_DVMM_PTE_ARB_CONTROL 0x428c 3049 #define mmDCP5_DVMM_PTE_ARB_CONTROL 0x448c 3050 #define mmDCP_DEBUG 0x1a8d 3051 #define mmDCP0_DCP_DEBUG 0x1a8d 3052 #define mmDCP1_DCP_DEBUG 0x1c8d 3053 #define mmDCP2_DCP_DEBUG 0x1e8d 3054 #define mmDCP3_DCP_DEBUG 0x408d 3055 #define mmDCP4_DCP_DEBUG 0x428d 3056 #define mmDCP5_DCP_DEBUG 0x448d 3057 #define mmGRPH_FLIP_RATE_CNTL 0x1a8e 3058 #define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e 3059 #define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e 3060 #define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e 3061 #define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e 3062 #define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e 3063 #define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e 3064 #define mmDCP_GSL_CONTROL 0x1a90 3065 #define mmDCP0_DCP_GSL_CONTROL 0x1a90 3066 #define mmDCP1_DCP_GSL_CONTROL 0x1c90 3067 #define mmDCP2_DCP_GSL_CONTROL 0x1e90 3068 #define mmDCP3_DCP_GSL_CONTROL 0x4090 3069 #define mmDCP4_DCP_GSL_CONTROL 0x4290 3070 #define mmDCP5_DCP_GSL_CONTROL 0x4490 3071 #define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 3072 #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 3073 #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 3074 #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 3075 #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 3076 #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 3077 #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 3078 #define mmDCP_DEBUG_SG 0x1a92 3079 #define mmDCP0_DCP_DEBUG_SG 0x1a92 3080 #define mmDCP1_DCP_DEBUG_SG 0x1c92 3081 #define mmDCP2_DCP_DEBUG_SG 0x1e92 3082 #define mmDCP3_DCP_DEBUG_SG 0x4092 3083 #define mmDCP4_DCP_DEBUG_SG 0x4292 3084 #define mmDCP5_DCP_DEBUG_SG 0x4492 3085 #define mmDCP_DEBUG_SG2 0x1a94 3086 #define mmDCP0_DCP_DEBUG_SG2 0x1a94 3087 #define mmDCP1_DCP_DEBUG_SG2 0x1c94 3088 #define mmDCP2_DCP_DEBUG_SG2 0x1e94 3089 #define mmDCP3_DCP_DEBUG_SG2 0x4094 3090 #define mmDCP4_DCP_DEBUG_SG2 0x4294 3091 #define mmDCP5_DCP_DEBUG_SG2 0x4494 3092 #define mmDCP_DVMM_DEBUG 0x1a93 3093 #define mmDCP0_DCP_DVMM_DEBUG 0x1a93 3094 #define mmDCP1_DCP_DVMM_DEBUG 0x1c93 3095 #define mmDCP2_DCP_DVMM_DEBUG 0x1e93 3096 #define mmDCP3_DCP_DVMM_DEBUG 0x4093 3097 #define mmDCP4_DCP_DVMM_DEBUG 0x4293 3098 #define mmDCP5_DCP_DVMM_DEBUG 0x4493 3099 #define mmDCP_TEST_DEBUG_INDEX 0x1a95 3100 #define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 3101 #define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 3102 #define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 3103 #define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 3104 #define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 3105 #define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 3106 #define mmDCP_TEST_DEBUG_DATA 0x1a96 3107 #define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 3108 #define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 3109 #define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 3110 #define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 3111 #define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 3112 #define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 3113 #define mmGRPH_STEREOSYNC_FLIP 0x1a97 3114 #define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 3115 #define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 3116 #define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 3117 #define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 3118 #define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 3119 #define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 3120 #define mmDCP_DEBUG2 0x1a98 3121 #define mmDCP0_DCP_DEBUG2 0x1a98 3122 #define mmDCP1_DCP_DEBUG2 0x1c98 3123 #define mmDCP2_DCP_DEBUG2 0x1e98 3124 #define mmDCP3_DCP_DEBUG2 0x4098 3125 #define mmDCP4_DCP_DEBUG2 0x4298 3126 #define mmDCP5_DCP_DEBUG2 0x4498 3127 #define mmHW_ROTATION 0x1a9e 3128 #define mmDCP0_HW_ROTATION 0x1a9e 3129 #define mmDCP1_HW_ROTATION 0x1c9e 3130 #define mmDCP2_HW_ROTATION 0x1e9e 3131 #define mmDCP3_HW_ROTATION 0x409e 3132 #define mmDCP4_HW_ROTATION 0x429e 3133 #define mmDCP5_HW_ROTATION 0x449e 3134 #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f 3135 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f 3136 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f 3137 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f 3138 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f 3139 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f 3140 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f 3141 #define mmREGAMMA_CONTROL 0x1aa0 3142 #define mmDCP0_REGAMMA_CONTROL 0x1aa0 3143 #define mmDCP1_REGAMMA_CONTROL 0x1ca0 3144 #define mmDCP2_REGAMMA_CONTROL 0x1ea0 3145 #define mmDCP3_REGAMMA_CONTROL 0x40a0 3146 #define mmDCP4_REGAMMA_CONTROL 0x42a0 3147 #define mmDCP5_REGAMMA_CONTROL 0x44a0 3148 #define mmREGAMMA_LUT_INDEX 0x1aa1 3149 #define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 3150 #define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 3151 #define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 3152 #define mmDCP3_REGAMMA_LUT_INDEX 0x40a1 3153 #define mmDCP4_REGAMMA_LUT_INDEX 0x42a1 3154 #define mmDCP5_REGAMMA_LUT_INDEX 0x44a1 3155 #define mmREGAMMA_LUT_DATA 0x1aa2 3156 #define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 3157 #define mmDCP1_REGAMMA_LUT_DATA 0x1ca2 3158 #define mmDCP2_REGAMMA_LUT_DATA 0x1ea2 3159 #define mmDCP3_REGAMMA_LUT_DATA 0x40a2 3160 #define mmDCP4_REGAMMA_LUT_DATA 0x42a2 3161 #define mmDCP5_REGAMMA_LUT_DATA 0x44a2 3162 #define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 3163 #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 3164 #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 3165 #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 3166 #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 3167 #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 3168 #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 3169 #define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 3170 #define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 3171 #define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 3172 #define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 3173 #define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 3174 #define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 3175 #define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 3176 #define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 3177 #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 3178 #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 3179 #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 3180 #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 3181 #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 3182 #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 3183 #define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 3184 #define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 3185 #define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 3186 #define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 3187 #define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 3188 #define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 3189 #define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 3190 #define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 3191 #define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 3192 #define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 3193 #define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 3194 #define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 3195 #define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 3196 #define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 3197 #define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 3198 #define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 3199 #define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 3200 #define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 3201 #define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 3202 #define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 3203 #define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 3204 #define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 3205 #define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 3206 #define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 3207 #define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 3208 #define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 3209 #define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 3210 #define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 3211 #define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa 3212 #define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa 3213 #define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa 3214 #define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa 3215 #define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa 3216 #define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa 3217 #define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa 3218 #define mmREGAMMA_CNTLA_REGION_6_7 0x1aab 3219 #define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab 3220 #define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab 3221 #define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab 3222 #define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab 3223 #define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab 3224 #define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab 3225 #define mmREGAMMA_CNTLA_REGION_8_9 0x1aac 3226 #define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac 3227 #define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac 3228 #define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac 3229 #define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac 3230 #define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac 3231 #define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac 3232 #define mmREGAMMA_CNTLA_REGION_10_11 0x1aad 3233 #define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad 3234 #define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad 3235 #define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead 3236 #define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad 3237 #define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad 3238 #define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad 3239 #define mmREGAMMA_CNTLA_REGION_12_13 0x1aae 3240 #define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae 3241 #define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae 3242 #define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae 3243 #define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae 3244 #define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae 3245 #define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae 3246 #define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf 3247 #define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf 3248 #define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf 3249 #define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf 3250 #define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af 3251 #define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af 3252 #define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af 3253 #define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 3254 #define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 3255 #define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 3256 #define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 3257 #define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 3258 #define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 3259 #define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 3260 #define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 3261 #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 3262 #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 3263 #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 3264 #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 3265 #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 3266 #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 3267 #define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 3268 #define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 3269 #define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 3270 #define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 3271 #define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 3272 #define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 3273 #define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 3274 #define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 3275 #define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 3276 #define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 3277 #define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 3278 #define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 3279 #define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 3280 #define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 3281 #define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 3282 #define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 3283 #define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 3284 #define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 3285 #define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 3286 #define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 3287 #define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 3288 #define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 3289 #define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 3290 #define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 3291 #define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 3292 #define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 3293 #define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 3294 #define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 3295 #define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 3296 #define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 3297 #define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 3298 #define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 3299 #define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 3300 #define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 3301 #define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 3302 #define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 3303 #define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 3304 #define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 3305 #define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 3306 #define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 3307 #define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 3308 #define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 3309 #define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 3310 #define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 3311 #define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 3312 #define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 3313 #define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 3314 #define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 3315 #define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 3316 #define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 3317 #define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 3318 #define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 3319 #define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 3320 #define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 3321 #define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 3322 #define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 3323 #define mmREGAMMA_CNTLB_REGION_12_13 0x1aba 3324 #define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba 3325 #define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba 3326 #define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba 3327 #define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba 3328 #define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba 3329 #define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba 3330 #define mmREGAMMA_CNTLB_REGION_14_15 0x1abb 3331 #define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb 3332 #define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb 3333 #define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb 3334 #define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb 3335 #define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb 3336 #define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb 3337 #define mmALPHA_CONTROL 0x1abc 3338 #define mmDCP0_ALPHA_CONTROL 0x1abc 3339 #define mmDCP1_ALPHA_CONTROL 0x1cbc 3340 #define mmDCP2_ALPHA_CONTROL 0x1ebc 3341 #define mmDCP3_ALPHA_CONTROL 0x40bc 3342 #define mmDCP4_ALPHA_CONTROL 0x42bc 3343 #define mmDCP5_ALPHA_CONTROL 0x44bc 3344 #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd 3345 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd 3346 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd 3347 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd 3348 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd 3349 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd 3350 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd 3351 #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe 3352 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe 3353 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe 3354 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe 3355 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be 3356 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be 3357 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be 3358 #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf 3359 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf 3360 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf 3361 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf 3362 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf 3363 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf 3364 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf 3365 #define mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f 3366 #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f 3367 #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f 3368 #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f 3369 #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f 3370 #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f 3371 #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f 3372 #define mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d 3373 #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d 3374 #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d 3375 #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d 3376 #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d 3377 #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d 3378 #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d 3379 #define mmDIG_FE_CNTL 0x4a00 3380 #define mmDIG0_DIG_FE_CNTL 0x4a00 3381 #define mmDIG1_DIG_FE_CNTL 0x4b00 3382 #define mmDIG2_DIG_FE_CNTL 0x4c00 3383 #define mmDIG3_DIG_FE_CNTL 0x4d00 3384 #define mmDIG4_DIG_FE_CNTL 0x4e00 3385 #define mmDIG5_DIG_FE_CNTL 0x4f00 3386 #define mmDIG6_DIG_FE_CNTL 0x5400 3387 #define mmDIG7_DIG_FE_CNTL 0x5600 3388 #define mmDIG8_DIG_FE_CNTL 0x5700 3389 #define mmDIG_OUTPUT_CRC_CNTL 0x4a01 3390 #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 3391 #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 3392 #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 3393 #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 3394 #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 3395 #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 3396 #define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 3397 #define mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601 3398 #define mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701 3399 #define mmDIG_OUTPUT_CRC_RESULT 0x4a02 3400 #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 3401 #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 3402 #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 3403 #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 3404 #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 3405 #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 3406 #define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 3407 #define mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602 3408 #define mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702 3409 #define mmDIG_CLOCK_PATTERN 0x4a03 3410 #define mmDIG0_DIG_CLOCK_PATTERN 0x4a03 3411 #define mmDIG1_DIG_CLOCK_PATTERN 0x4b03 3412 #define mmDIG2_DIG_CLOCK_PATTERN 0x4c03 3413 #define mmDIG3_DIG_CLOCK_PATTERN 0x4d03 3414 #define mmDIG4_DIG_CLOCK_PATTERN 0x4e03 3415 #define mmDIG5_DIG_CLOCK_PATTERN 0x4f03 3416 #define mmDIG6_DIG_CLOCK_PATTERN 0x5403 3417 #define mmDIG7_DIG_CLOCK_PATTERN 0x5603 3418 #define mmDIG8_DIG_CLOCK_PATTERN 0x5703 3419 #define mmDIG_TEST_PATTERN 0x4a04 3420 #define mmDIG0_DIG_TEST_PATTERN 0x4a04 3421 #define mmDIG1_DIG_TEST_PATTERN 0x4b04 3422 #define mmDIG2_DIG_TEST_PATTERN 0x4c04 3423 #define mmDIG3_DIG_TEST_PATTERN 0x4d04 3424 #define mmDIG4_DIG_TEST_PATTERN 0x4e04 3425 #define mmDIG5_DIG_TEST_PATTERN 0x4f04 3426 #define mmDIG6_DIG_TEST_PATTERN 0x5404 3427 #define mmDIG7_DIG_TEST_PATTERN 0x5604 3428 #define mmDIG8_DIG_TEST_PATTERN 0x5704 3429 #define mmDIG_RANDOM_PATTERN_SEED 0x4a05 3430 #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 3431 #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 3432 #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 3433 #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 3434 #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 3435 #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 3436 #define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 3437 #define mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605 3438 #define mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705 3439 #define mmDIG_FIFO_STATUS 0x4a06 3440 #define mmDIG0_DIG_FIFO_STATUS 0x4a06 3441 #define mmDIG1_DIG_FIFO_STATUS 0x4b06 3442 #define mmDIG2_DIG_FIFO_STATUS 0x4c06 3443 #define mmDIG3_DIG_FIFO_STATUS 0x4d06 3444 #define mmDIG4_DIG_FIFO_STATUS 0x4e06 3445 #define mmDIG5_DIG_FIFO_STATUS 0x4f06 3446 #define mmDIG6_DIG_FIFO_STATUS 0x5406 3447 #define mmDIG7_DIG_FIFO_STATUS 0x5606 3448 #define mmDIG8_DIG_FIFO_STATUS 0x5706 3449 #define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 3450 #define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 3451 #define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 3452 #define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 3453 #define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 3454 #define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 3455 #define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 3456 #define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 3457 #define mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607 3458 #define mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707 3459 #define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 3460 #define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 3461 #define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 3462 #define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 3463 #define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 3464 #define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 3465 #define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 3466 #define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 3467 #define mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608 3468 #define mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708 3469 #define mmHDMI_CONTROL 0x4a09 3470 #define mmDIG0_HDMI_CONTROL 0x4a09 3471 #define mmDIG1_HDMI_CONTROL 0x4b09 3472 #define mmDIG2_HDMI_CONTROL 0x4c09 3473 #define mmDIG3_HDMI_CONTROL 0x4d09 3474 #define mmDIG4_HDMI_CONTROL 0x4e09 3475 #define mmDIG5_HDMI_CONTROL 0x4f09 3476 #define mmDIG6_HDMI_CONTROL 0x5409 3477 #define mmDIG7_HDMI_CONTROL 0x5609 3478 #define mmDIG8_HDMI_CONTROL 0x5709 3479 #define mmHDMI_STATUS 0x4a0a 3480 #define mmDIG0_HDMI_STATUS 0x4a0a 3481 #define mmDIG1_HDMI_STATUS 0x4b0a 3482 #define mmDIG2_HDMI_STATUS 0x4c0a 3483 #define mmDIG3_HDMI_STATUS 0x4d0a 3484 #define mmDIG4_HDMI_STATUS 0x4e0a 3485 #define mmDIG5_HDMI_STATUS 0x4f0a 3486 #define mmDIG6_HDMI_STATUS 0x540a 3487 #define mmDIG7_HDMI_STATUS 0x560a 3488 #define mmDIG8_HDMI_STATUS 0x570a 3489 #define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b 3490 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b 3491 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b 3492 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b 3493 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b 3494 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b 3495 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b 3496 #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b 3497 #define mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b 3498 #define mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b 3499 #define mmHDMI_ACR_PACKET_CONTROL 0x4a0c 3500 #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c 3501 #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c 3502 #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c 3503 #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c 3504 #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c 3505 #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c 3506 #define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c 3507 #define mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c 3508 #define mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c 3509 #define mmHDMI_VBI_PACKET_CONTROL 0x4a0d 3510 #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d 3511 #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d 3512 #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d 3513 #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d 3514 #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d 3515 #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d 3516 #define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d 3517 #define mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d 3518 #define mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d 3519 #define mmHDMI_INFOFRAME_CONTROL0 0x4a0e 3520 #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e 3521 #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e 3522 #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e 3523 #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e 3524 #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e 3525 #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e 3526 #define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e 3527 #define mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e 3528 #define mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e 3529 #define mmHDMI_INFOFRAME_CONTROL1 0x4a0f 3530 #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f 3531 #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f 3532 #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f 3533 #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f 3534 #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f 3535 #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f 3536 #define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f 3537 #define mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f 3538 #define mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f 3539 #define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 3540 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 3541 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 3542 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 3543 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 3544 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 3545 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 3546 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 3547 #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610 3548 #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710 3549 #define mmAFMT_INTERRUPT_STATUS 0x4a11 3550 #define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 3551 #define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 3552 #define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 3553 #define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 3554 #define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 3555 #define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 3556 #define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 3557 #define mmDIG7_AFMT_INTERRUPT_STATUS 0x5611 3558 #define mmDIG8_AFMT_INTERRUPT_STATUS 0x5711 3559 #define mmHDMI_GC 0x4a13 3560 #define mmDIG0_HDMI_GC 0x4a13 3561 #define mmDIG1_HDMI_GC 0x4b13 3562 #define mmDIG2_HDMI_GC 0x4c13 3563 #define mmDIG3_HDMI_GC 0x4d13 3564 #define mmDIG4_HDMI_GC 0x4e13 3565 #define mmDIG5_HDMI_GC 0x4f13 3566 #define mmDIG6_HDMI_GC 0x5413 3567 #define mmDIG7_HDMI_GC 0x5613 3568 #define mmDIG8_HDMI_GC 0x5713 3569 #define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 3570 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 3571 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 3572 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 3573 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 3574 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 3575 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 3576 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 3577 #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614 3578 #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714 3579 #define mmAFMT_ISRC1_0 0x4a15 3580 #define mmDIG0_AFMT_ISRC1_0 0x4a15 3581 #define mmDIG1_AFMT_ISRC1_0 0x4b15 3582 #define mmDIG2_AFMT_ISRC1_0 0x4c15 3583 #define mmDIG3_AFMT_ISRC1_0 0x4d15 3584 #define mmDIG4_AFMT_ISRC1_0 0x4e15 3585 #define mmDIG5_AFMT_ISRC1_0 0x4f15 3586 #define mmDIG6_AFMT_ISRC1_0 0x5415 3587 #define mmDIG7_AFMT_ISRC1_0 0x5615 3588 #define mmDIG8_AFMT_ISRC1_0 0x5715 3589 #define mmAFMT_ISRC1_1 0x4a16 3590 #define mmDIG0_AFMT_ISRC1_1 0x4a16 3591 #define mmDIG1_AFMT_ISRC1_1 0x4b16 3592 #define mmDIG2_AFMT_ISRC1_1 0x4c16 3593 #define mmDIG3_AFMT_ISRC1_1 0x4d16 3594 #define mmDIG4_AFMT_ISRC1_1 0x4e16 3595 #define mmDIG5_AFMT_ISRC1_1 0x4f16 3596 #define mmDIG6_AFMT_ISRC1_1 0x5416 3597 #define mmDIG7_AFMT_ISRC1_1 0x5616 3598 #define mmDIG8_AFMT_ISRC1_1 0x5716 3599 #define mmAFMT_ISRC1_2 0x4a17 3600 #define mmDIG0_AFMT_ISRC1_2 0x4a17 3601 #define mmDIG1_AFMT_ISRC1_2 0x4b17 3602 #define mmDIG2_AFMT_ISRC1_2 0x4c17 3603 #define mmDIG3_AFMT_ISRC1_2 0x4d17 3604 #define mmDIG4_AFMT_ISRC1_2 0x4e17 3605 #define mmDIG5_AFMT_ISRC1_2 0x4f17 3606 #define mmDIG6_AFMT_ISRC1_2 0x5417 3607 #define mmDIG7_AFMT_ISRC1_2 0x5617 3608 #define mmDIG8_AFMT_ISRC1_2 0x5717 3609 #define mmAFMT_ISRC1_3 0x4a18 3610 #define mmDIG0_AFMT_ISRC1_3 0x4a18 3611 #define mmDIG1_AFMT_ISRC1_3 0x4b18 3612 #define mmDIG2_AFMT_ISRC1_3 0x4c18 3613 #define mmDIG3_AFMT_ISRC1_3 0x4d18 3614 #define mmDIG4_AFMT_ISRC1_3 0x4e18 3615 #define mmDIG5_AFMT_ISRC1_3 0x4f18 3616 #define mmDIG6_AFMT_ISRC1_3 0x5418 3617 #define mmDIG7_AFMT_ISRC1_3 0x5618 3618 #define mmDIG8_AFMT_ISRC1_3 0x5718 3619 #define mmAFMT_ISRC1_4 0x4a19 3620 #define mmDIG0_AFMT_ISRC1_4 0x4a19 3621 #define mmDIG1_AFMT_ISRC1_4 0x4b19 3622 #define mmDIG2_AFMT_ISRC1_4 0x4c19 3623 #define mmDIG3_AFMT_ISRC1_4 0x4d19 3624 #define mmDIG4_AFMT_ISRC1_4 0x4e19 3625 #define mmDIG5_AFMT_ISRC1_4 0x4f19 3626 #define mmDIG6_AFMT_ISRC1_4 0x5419 3627 #define mmDIG7_AFMT_ISRC1_4 0x5619 3628 #define mmDIG8_AFMT_ISRC1_4 0x5719 3629 #define mmAFMT_ISRC2_0 0x4a1a 3630 #define mmDIG0_AFMT_ISRC2_0 0x4a1a 3631 #define mmDIG1_AFMT_ISRC2_0 0x4b1a 3632 #define mmDIG2_AFMT_ISRC2_0 0x4c1a 3633 #define mmDIG3_AFMT_ISRC2_0 0x4d1a 3634 #define mmDIG4_AFMT_ISRC2_0 0x4e1a 3635 #define mmDIG5_AFMT_ISRC2_0 0x4f1a 3636 #define mmDIG6_AFMT_ISRC2_0 0x541a 3637 #define mmDIG7_AFMT_ISRC2_0 0x561a 3638 #define mmDIG8_AFMT_ISRC2_0 0x571a 3639 #define mmAFMT_ISRC2_1 0x4a1b 3640 #define mmDIG0_AFMT_ISRC2_1 0x4a1b 3641 #define mmDIG1_AFMT_ISRC2_1 0x4b1b 3642 #define mmDIG2_AFMT_ISRC2_1 0x4c1b 3643 #define mmDIG3_AFMT_ISRC2_1 0x4d1b 3644 #define mmDIG4_AFMT_ISRC2_1 0x4e1b 3645 #define mmDIG5_AFMT_ISRC2_1 0x4f1b 3646 #define mmDIG6_AFMT_ISRC2_1 0x541b 3647 #define mmDIG7_AFMT_ISRC2_1 0x561b 3648 #define mmDIG8_AFMT_ISRC2_1 0x571b 3649 #define mmAFMT_ISRC2_2 0x4a1c 3650 #define mmDIG0_AFMT_ISRC2_2 0x4a1c 3651 #define mmDIG1_AFMT_ISRC2_2 0x4b1c 3652 #define mmDIG2_AFMT_ISRC2_2 0x4c1c 3653 #define mmDIG3_AFMT_ISRC2_2 0x4d1c 3654 #define mmDIG4_AFMT_ISRC2_2 0x4e1c 3655 #define mmDIG5_AFMT_ISRC2_2 0x4f1c 3656 #define mmDIG6_AFMT_ISRC2_2 0x541c 3657 #define mmDIG7_AFMT_ISRC2_2 0x561c 3658 #define mmDIG8_AFMT_ISRC2_2 0x571c 3659 #define mmAFMT_ISRC2_3 0x4a1d 3660 #define mmDIG0_AFMT_ISRC2_3 0x4a1d 3661 #define mmDIG1_AFMT_ISRC2_3 0x4b1d 3662 #define mmDIG2_AFMT_ISRC2_3 0x4c1d 3663 #define mmDIG3_AFMT_ISRC2_3 0x4d1d 3664 #define mmDIG4_AFMT_ISRC2_3 0x4e1d 3665 #define mmDIG5_AFMT_ISRC2_3 0x4f1d 3666 #define mmDIG6_AFMT_ISRC2_3 0x541d 3667 #define mmDIG7_AFMT_ISRC2_3 0x561d 3668 #define mmDIG8_AFMT_ISRC2_3 0x571d 3669 #define mmAFMT_AVI_INFO0 0x4a1e 3670 #define mmDIG0_AFMT_AVI_INFO0 0x4a1e 3671 #define mmDIG1_AFMT_AVI_INFO0 0x4b1e 3672 #define mmDIG2_AFMT_AVI_INFO0 0x4c1e 3673 #define mmDIG3_AFMT_AVI_INFO0 0x4d1e 3674 #define mmDIG4_AFMT_AVI_INFO0 0x4e1e 3675 #define mmDIG5_AFMT_AVI_INFO0 0x4f1e 3676 #define mmDIG6_AFMT_AVI_INFO0 0x541e 3677 #define mmDIG7_AFMT_AVI_INFO0 0x561e 3678 #define mmDIG8_AFMT_AVI_INFO0 0x571e 3679 #define mmAFMT_AVI_INFO1 0x4a1f 3680 #define mmDIG0_AFMT_AVI_INFO1 0x4a1f 3681 #define mmDIG1_AFMT_AVI_INFO1 0x4b1f 3682 #define mmDIG2_AFMT_AVI_INFO1 0x4c1f 3683 #define mmDIG3_AFMT_AVI_INFO1 0x4d1f 3684 #define mmDIG4_AFMT_AVI_INFO1 0x4e1f 3685 #define mmDIG5_AFMT_AVI_INFO1 0x4f1f 3686 #define mmDIG6_AFMT_AVI_INFO1 0x541f 3687 #define mmDIG7_AFMT_AVI_INFO1 0x561f 3688 #define mmDIG8_AFMT_AVI_INFO1 0x571f 3689 #define mmAFMT_AVI_INFO2 0x4a20 3690 #define mmDIG0_AFMT_AVI_INFO2 0x4a20 3691 #define mmDIG1_AFMT_AVI_INFO2 0x4b20 3692 #define mmDIG2_AFMT_AVI_INFO2 0x4c20 3693 #define mmDIG3_AFMT_AVI_INFO2 0x4d20 3694 #define mmDIG4_AFMT_AVI_INFO2 0x4e20 3695 #define mmDIG5_AFMT_AVI_INFO2 0x4f20 3696 #define mmDIG6_AFMT_AVI_INFO2 0x5420 3697 #define mmDIG7_AFMT_AVI_INFO2 0x5620 3698 #define mmDIG8_AFMT_AVI_INFO2 0x5720 3699 #define mmAFMT_AVI_INFO3 0x4a21 3700 #define mmDIG0_AFMT_AVI_INFO3 0x4a21 3701 #define mmDIG1_AFMT_AVI_INFO3 0x4b21 3702 #define mmDIG2_AFMT_AVI_INFO3 0x4c21 3703 #define mmDIG3_AFMT_AVI_INFO3 0x4d21 3704 #define mmDIG4_AFMT_AVI_INFO3 0x4e21 3705 #define mmDIG5_AFMT_AVI_INFO3 0x4f21 3706 #define mmDIG6_AFMT_AVI_INFO3 0x5421 3707 #define mmDIG7_AFMT_AVI_INFO3 0x5621 3708 #define mmDIG8_AFMT_AVI_INFO3 0x5721 3709 #define mmAFMT_MPEG_INFO0 0x4a22 3710 #define mmDIG0_AFMT_MPEG_INFO0 0x4a22 3711 #define mmDIG1_AFMT_MPEG_INFO0 0x4b22 3712 #define mmDIG2_AFMT_MPEG_INFO0 0x4c22 3713 #define mmDIG3_AFMT_MPEG_INFO0 0x4d22 3714 #define mmDIG4_AFMT_MPEG_INFO0 0x4e22 3715 #define mmDIG5_AFMT_MPEG_INFO0 0x4f22 3716 #define mmDIG6_AFMT_MPEG_INFO0 0x5422 3717 #define mmDIG7_AFMT_MPEG_INFO0 0x5622 3718 #define mmDIG8_AFMT_MPEG_INFO0 0x5722 3719 #define mmAFMT_MPEG_INFO1 0x4a23 3720 #define mmDIG0_AFMT_MPEG_INFO1 0x4a23 3721 #define mmDIG1_AFMT_MPEG_INFO1 0x4b23 3722 #define mmDIG2_AFMT_MPEG_INFO1 0x4c23 3723 #define mmDIG3_AFMT_MPEG_INFO1 0x4d23 3724 #define mmDIG4_AFMT_MPEG_INFO1 0x4e23 3725 #define mmDIG5_AFMT_MPEG_INFO1 0x4f23 3726 #define mmDIG6_AFMT_MPEG_INFO1 0x5423 3727 #define mmDIG7_AFMT_MPEG_INFO1 0x5623 3728 #define mmDIG8_AFMT_MPEG_INFO1 0x5723 3729 #define mmAFMT_GENERIC_HDR 0x4a24 3730 #define mmDIG0_AFMT_GENERIC_HDR 0x4a24 3731 #define mmDIG1_AFMT_GENERIC_HDR 0x4b24 3732 #define mmDIG2_AFMT_GENERIC_HDR 0x4c24 3733 #define mmDIG3_AFMT_GENERIC_HDR 0x4d24 3734 #define mmDIG4_AFMT_GENERIC_HDR 0x4e24 3735 #define mmDIG5_AFMT_GENERIC_HDR 0x4f24 3736 #define mmDIG6_AFMT_GENERIC_HDR 0x5424 3737 #define mmDIG7_AFMT_GENERIC_HDR 0x5624 3738 #define mmDIG8_AFMT_GENERIC_HDR 0x5724 3739 #define mmAFMT_GENERIC_0 0x4a25 3740 #define mmDIG0_AFMT_GENERIC_0 0x4a25 3741 #define mmDIG1_AFMT_GENERIC_0 0x4b25 3742 #define mmDIG2_AFMT_GENERIC_0 0x4c25 3743 #define mmDIG3_AFMT_GENERIC_0 0x4d25 3744 #define mmDIG4_AFMT_GENERIC_0 0x4e25 3745 #define mmDIG5_AFMT_GENERIC_0 0x4f25 3746 #define mmDIG6_AFMT_GENERIC_0 0x5425 3747 #define mmDIG7_AFMT_GENERIC_0 0x5625 3748 #define mmDIG8_AFMT_GENERIC_0 0x5725 3749 #define mmAFMT_GENERIC_1 0x4a26 3750 #define mmDIG0_AFMT_GENERIC_1 0x4a26 3751 #define mmDIG1_AFMT_GENERIC_1 0x4b26 3752 #define mmDIG2_AFMT_GENERIC_1 0x4c26 3753 #define mmDIG3_AFMT_GENERIC_1 0x4d26 3754 #define mmDIG4_AFMT_GENERIC_1 0x4e26 3755 #define mmDIG5_AFMT_GENERIC_1 0x4f26 3756 #define mmDIG6_AFMT_GENERIC_1 0x5426 3757 #define mmDIG7_AFMT_GENERIC_1 0x5626 3758 #define mmDIG8_AFMT_GENERIC_1 0x5726 3759 #define mmAFMT_GENERIC_2 0x4a27 3760 #define mmDIG0_AFMT_GENERIC_2 0x4a27 3761 #define mmDIG1_AFMT_GENERIC_2 0x4b27 3762 #define mmDIG2_AFMT_GENERIC_2 0x4c27 3763 #define mmDIG3_AFMT_GENERIC_2 0x4d27 3764 #define mmDIG4_AFMT_GENERIC_2 0x4e27 3765 #define mmDIG5_AFMT_GENERIC_2 0x4f27 3766 #define mmDIG6_AFMT_GENERIC_2 0x5427 3767 #define mmDIG7_AFMT_GENERIC_2 0x5627 3768 #define mmDIG8_AFMT_GENERIC_2 0x5727 3769 #define mmAFMT_GENERIC_3 0x4a28 3770 #define mmDIG0_AFMT_GENERIC_3 0x4a28 3771 #define mmDIG1_AFMT_GENERIC_3 0x4b28 3772 #define mmDIG2_AFMT_GENERIC_3 0x4c28 3773 #define mmDIG3_AFMT_GENERIC_3 0x4d28 3774 #define mmDIG4_AFMT_GENERIC_3 0x4e28 3775 #define mmDIG5_AFMT_GENERIC_3 0x4f28 3776 #define mmDIG6_AFMT_GENERIC_3 0x5428 3777 #define mmDIG7_AFMT_GENERIC_3 0x5628 3778 #define mmDIG8_AFMT_GENERIC_3 0x5728 3779 #define mmAFMT_GENERIC_4 0x4a29 3780 #define mmDIG0_AFMT_GENERIC_4 0x4a29 3781 #define mmDIG1_AFMT_GENERIC_4 0x4b29 3782 #define mmDIG2_AFMT_GENERIC_4 0x4c29 3783 #define mmDIG3_AFMT_GENERIC_4 0x4d29 3784 #define mmDIG4_AFMT_GENERIC_4 0x4e29 3785 #define mmDIG5_AFMT_GENERIC_4 0x4f29 3786 #define mmDIG6_AFMT_GENERIC_4 0x5429 3787 #define mmDIG7_AFMT_GENERIC_4 0x5629 3788 #define mmDIG8_AFMT_GENERIC_4 0x5729 3789 #define mmAFMT_GENERIC_5 0x4a2a 3790 #define mmDIG0_AFMT_GENERIC_5 0x4a2a 3791 #define mmDIG1_AFMT_GENERIC_5 0x4b2a 3792 #define mmDIG2_AFMT_GENERIC_5 0x4c2a 3793 #define mmDIG3_AFMT_GENERIC_5 0x4d2a 3794 #define mmDIG4_AFMT_GENERIC_5 0x4e2a 3795 #define mmDIG5_AFMT_GENERIC_5 0x4f2a 3796 #define mmDIG6_AFMT_GENERIC_5 0x542a 3797 #define mmDIG7_AFMT_GENERIC_5 0x562a 3798 #define mmDIG8_AFMT_GENERIC_5 0x572a 3799 #define mmAFMT_GENERIC_6 0x4a2b 3800 #define mmDIG0_AFMT_GENERIC_6 0x4a2b 3801 #define mmDIG1_AFMT_GENERIC_6 0x4b2b 3802 #define mmDIG2_AFMT_GENERIC_6 0x4c2b 3803 #define mmDIG3_AFMT_GENERIC_6 0x4d2b 3804 #define mmDIG4_AFMT_GENERIC_6 0x4e2b 3805 #define mmDIG5_AFMT_GENERIC_6 0x4f2b 3806 #define mmDIG6_AFMT_GENERIC_6 0x542b 3807 #define mmDIG7_AFMT_GENERIC_6 0x562b 3808 #define mmDIG8_AFMT_GENERIC_6 0x572b 3809 #define mmAFMT_GENERIC_7 0x4a2c 3810 #define mmDIG0_AFMT_GENERIC_7 0x4a2c 3811 #define mmDIG1_AFMT_GENERIC_7 0x4b2c 3812 #define mmDIG2_AFMT_GENERIC_7 0x4c2c 3813 #define mmDIG3_AFMT_GENERIC_7 0x4d2c 3814 #define mmDIG4_AFMT_GENERIC_7 0x4e2c 3815 #define mmDIG5_AFMT_GENERIC_7 0x4f2c 3816 #define mmDIG6_AFMT_GENERIC_7 0x542c 3817 #define mmDIG7_AFMT_GENERIC_7 0x562c 3818 #define mmDIG8_AFMT_GENERIC_7 0x572c 3819 #define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d 3820 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d 3821 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d 3822 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d 3823 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d 3824 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d 3825 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d 3826 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d 3827 #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d 3828 #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d 3829 #define mmHDMI_ACR_32_0 0x4a2e 3830 #define mmDIG0_HDMI_ACR_32_0 0x4a2e 3831 #define mmDIG1_HDMI_ACR_32_0 0x4b2e 3832 #define mmDIG2_HDMI_ACR_32_0 0x4c2e 3833 #define mmDIG3_HDMI_ACR_32_0 0x4d2e 3834 #define mmDIG4_HDMI_ACR_32_0 0x4e2e 3835 #define mmDIG5_HDMI_ACR_32_0 0x4f2e 3836 #define mmDIG6_HDMI_ACR_32_0 0x542e 3837 #define mmDIG7_HDMI_ACR_32_0 0x562e 3838 #define mmDIG8_HDMI_ACR_32_0 0x572e 3839 #define mmHDMI_ACR_32_1 0x4a2f 3840 #define mmDIG0_HDMI_ACR_32_1 0x4a2f 3841 #define mmDIG1_HDMI_ACR_32_1 0x4b2f 3842 #define mmDIG2_HDMI_ACR_32_1 0x4c2f 3843 #define mmDIG3_HDMI_ACR_32_1 0x4d2f 3844 #define mmDIG4_HDMI_ACR_32_1 0x4e2f 3845 #define mmDIG5_HDMI_ACR_32_1 0x4f2f 3846 #define mmDIG6_HDMI_ACR_32_1 0x542f 3847 #define mmDIG7_HDMI_ACR_32_1 0x562f 3848 #define mmDIG8_HDMI_ACR_32_1 0x572f 3849 #define mmHDMI_ACR_44_0 0x4a30 3850 #define mmDIG0_HDMI_ACR_44_0 0x4a30 3851 #define mmDIG1_HDMI_ACR_44_0 0x4b30 3852 #define mmDIG2_HDMI_ACR_44_0 0x4c30 3853 #define mmDIG3_HDMI_ACR_44_0 0x4d30 3854 #define mmDIG4_HDMI_ACR_44_0 0x4e30 3855 #define mmDIG5_HDMI_ACR_44_0 0x4f30 3856 #define mmDIG6_HDMI_ACR_44_0 0x5430 3857 #define mmDIG7_HDMI_ACR_44_0 0x5630 3858 #define mmDIG8_HDMI_ACR_44_0 0x5730 3859 #define mmHDMI_ACR_44_1 0x4a31 3860 #define mmDIG0_HDMI_ACR_44_1 0x4a31 3861 #define mmDIG1_HDMI_ACR_44_1 0x4b31 3862 #define mmDIG2_HDMI_ACR_44_1 0x4c31 3863 #define mmDIG3_HDMI_ACR_44_1 0x4d31 3864 #define mmDIG4_HDMI_ACR_44_1 0x4e31 3865 #define mmDIG5_HDMI_ACR_44_1 0x4f31 3866 #define mmDIG6_HDMI_ACR_44_1 0x5431 3867 #define mmDIG7_HDMI_ACR_44_1 0x5631 3868 #define mmDIG8_HDMI_ACR_44_1 0x5731 3869 #define mmHDMI_ACR_48_0 0x4a32 3870 #define mmDIG0_HDMI_ACR_48_0 0x4a32 3871 #define mmDIG1_HDMI_ACR_48_0 0x4b32 3872 #define mmDIG2_HDMI_ACR_48_0 0x4c32 3873 #define mmDIG3_HDMI_ACR_48_0 0x4d32 3874 #define mmDIG4_HDMI_ACR_48_0 0x4e32 3875 #define mmDIG5_HDMI_ACR_48_0 0x4f32 3876 #define mmDIG6_HDMI_ACR_48_0 0x5432 3877 #define mmDIG7_HDMI_ACR_48_0 0x5632 3878 #define mmDIG8_HDMI_ACR_48_0 0x5732 3879 #define mmHDMI_ACR_48_1 0x4a33 3880 #define mmDIG0_HDMI_ACR_48_1 0x4a33 3881 #define mmDIG1_HDMI_ACR_48_1 0x4b33 3882 #define mmDIG2_HDMI_ACR_48_1 0x4c33 3883 #define mmDIG3_HDMI_ACR_48_1 0x4d33 3884 #define mmDIG4_HDMI_ACR_48_1 0x4e33 3885 #define mmDIG5_HDMI_ACR_48_1 0x4f33 3886 #define mmDIG6_HDMI_ACR_48_1 0x5433 3887 #define mmDIG7_HDMI_ACR_48_1 0x5633 3888 #define mmDIG8_HDMI_ACR_48_1 0x5733 3889 #define mmHDMI_ACR_STATUS_0 0x4a34 3890 #define mmDIG0_HDMI_ACR_STATUS_0 0x4a34 3891 #define mmDIG1_HDMI_ACR_STATUS_0 0x4b34 3892 #define mmDIG2_HDMI_ACR_STATUS_0 0x4c34 3893 #define mmDIG3_HDMI_ACR_STATUS_0 0x4d34 3894 #define mmDIG4_HDMI_ACR_STATUS_0 0x4e34 3895 #define mmDIG5_HDMI_ACR_STATUS_0 0x4f34 3896 #define mmDIG6_HDMI_ACR_STATUS_0 0x5434 3897 #define mmDIG7_HDMI_ACR_STATUS_0 0x5634 3898 #define mmDIG8_HDMI_ACR_STATUS_0 0x5734 3899 #define mmHDMI_ACR_STATUS_1 0x4a35 3900 #define mmDIG0_HDMI_ACR_STATUS_1 0x4a35 3901 #define mmDIG1_HDMI_ACR_STATUS_1 0x4b35 3902 #define mmDIG2_HDMI_ACR_STATUS_1 0x4c35 3903 #define mmDIG3_HDMI_ACR_STATUS_1 0x4d35 3904 #define mmDIG4_HDMI_ACR_STATUS_1 0x4e35 3905 #define mmDIG5_HDMI_ACR_STATUS_1 0x4f35 3906 #define mmDIG6_HDMI_ACR_STATUS_1 0x5435 3907 #define mmDIG7_HDMI_ACR_STATUS_1 0x5635 3908 #define mmDIG8_HDMI_ACR_STATUS_1 0x5735 3909 #define mmAFMT_AUDIO_INFO0 0x4a36 3910 #define mmDIG0_AFMT_AUDIO_INFO0 0x4a36 3911 #define mmDIG1_AFMT_AUDIO_INFO0 0x4b36 3912 #define mmDIG2_AFMT_AUDIO_INFO0 0x4c36 3913 #define mmDIG3_AFMT_AUDIO_INFO0 0x4d36 3914 #define mmDIG4_AFMT_AUDIO_INFO0 0x4e36 3915 #define mmDIG5_AFMT_AUDIO_INFO0 0x4f36 3916 #define mmDIG6_AFMT_AUDIO_INFO0 0x5436 3917 #define mmDIG7_AFMT_AUDIO_INFO0 0x5636 3918 #define mmDIG8_AFMT_AUDIO_INFO0 0x5736 3919 #define mmAFMT_AUDIO_INFO1 0x4a37 3920 #define mmDIG0_AFMT_AUDIO_INFO1 0x4a37 3921 #define mmDIG1_AFMT_AUDIO_INFO1 0x4b37 3922 #define mmDIG2_AFMT_AUDIO_INFO1 0x4c37 3923 #define mmDIG3_AFMT_AUDIO_INFO1 0x4d37 3924 #define mmDIG4_AFMT_AUDIO_INFO1 0x4e37 3925 #define mmDIG5_AFMT_AUDIO_INFO1 0x4f37 3926 #define mmDIG6_AFMT_AUDIO_INFO1 0x5437 3927 #define mmDIG7_AFMT_AUDIO_INFO1 0x5637 3928 #define mmDIG8_AFMT_AUDIO_INFO1 0x5737 3929 #define mmAFMT_60958_0 0x4a38 3930 #define mmDIG0_AFMT_60958_0 0x4a38 3931 #define mmDIG1_AFMT_60958_0 0x4b38 3932 #define mmDIG2_AFMT_60958_0 0x4c38 3933 #define mmDIG3_AFMT_60958_0 0x4d38 3934 #define mmDIG4_AFMT_60958_0 0x4e38 3935 #define mmDIG5_AFMT_60958_0 0x4f38 3936 #define mmDIG6_AFMT_60958_0 0x5438 3937 #define mmDIG7_AFMT_60958_0 0x5638 3938 #define mmDIG8_AFMT_60958_0 0x5738 3939 #define mmAFMT_60958_1 0x4a39 3940 #define mmDIG0_AFMT_60958_1 0x4a39 3941 #define mmDIG1_AFMT_60958_1 0x4b39 3942 #define mmDIG2_AFMT_60958_1 0x4c39 3943 #define mmDIG3_AFMT_60958_1 0x4d39 3944 #define mmDIG4_AFMT_60958_1 0x4e39 3945 #define mmDIG5_AFMT_60958_1 0x4f39 3946 #define mmDIG6_AFMT_60958_1 0x5439 3947 #define mmDIG7_AFMT_60958_1 0x5639 3948 #define mmDIG8_AFMT_60958_1 0x5739 3949 #define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a 3950 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a 3951 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a 3952 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a 3953 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a 3954 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a 3955 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a 3956 #define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a 3957 #define mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a 3958 #define mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a 3959 #define mmAFMT_RAMP_CONTROL0 0x4a3b 3960 #define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b 3961 #define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b 3962 #define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b 3963 #define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b 3964 #define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b 3965 #define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b 3966 #define mmDIG6_AFMT_RAMP_CONTROL0 0x543b 3967 #define mmDIG7_AFMT_RAMP_CONTROL0 0x563b 3968 #define mmDIG8_AFMT_RAMP_CONTROL0 0x573b 3969 #define mmAFMT_RAMP_CONTROL1 0x4a3c 3970 #define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c 3971 #define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c 3972 #define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c 3973 #define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c 3974 #define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c 3975 #define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c 3976 #define mmDIG6_AFMT_RAMP_CONTROL1 0x543c 3977 #define mmDIG7_AFMT_RAMP_CONTROL1 0x563c 3978 #define mmDIG8_AFMT_RAMP_CONTROL1 0x573c 3979 #define mmAFMT_RAMP_CONTROL2 0x4a3d 3980 #define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d 3981 #define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d 3982 #define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d 3983 #define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d 3984 #define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d 3985 #define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d 3986 #define mmDIG6_AFMT_RAMP_CONTROL2 0x543d 3987 #define mmDIG7_AFMT_RAMP_CONTROL2 0x563d 3988 #define mmDIG8_AFMT_RAMP_CONTROL2 0x573d 3989 #define mmAFMT_RAMP_CONTROL3 0x4a3e 3990 #define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e 3991 #define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e 3992 #define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e 3993 #define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e 3994 #define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e 3995 #define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e 3996 #define mmDIG6_AFMT_RAMP_CONTROL3 0x543e 3997 #define mmDIG7_AFMT_RAMP_CONTROL3 0x563e 3998 #define mmDIG8_AFMT_RAMP_CONTROL3 0x573e 3999 #define mmAFMT_60958_2 0x4a3f 4000 #define mmDIG0_AFMT_60958_2 0x4a3f 4001 #define mmDIG1_AFMT_60958_2 0x4b3f 4002 #define mmDIG2_AFMT_60958_2 0x4c3f 4003 #define mmDIG3_AFMT_60958_2 0x4d3f 4004 #define mmDIG4_AFMT_60958_2 0x4e3f 4005 #define mmDIG5_AFMT_60958_2 0x4f3f 4006 #define mmDIG6_AFMT_60958_2 0x543f 4007 #define mmDIG7_AFMT_60958_2 0x563f 4008 #define mmDIG8_AFMT_60958_2 0x573f 4009 #define mmAFMT_AUDIO_CRC_RESULT 0x4a40 4010 #define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 4011 #define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 4012 #define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 4013 #define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 4014 #define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 4015 #define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 4016 #define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 4017 #define mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640 4018 #define mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740 4019 #define mmAFMT_STATUS 0x4a41 4020 #define mmDIG0_AFMT_STATUS 0x4a41 4021 #define mmDIG1_AFMT_STATUS 0x4b41 4022 #define mmDIG2_AFMT_STATUS 0x4c41 4023 #define mmDIG3_AFMT_STATUS 0x4d41 4024 #define mmDIG4_AFMT_STATUS 0x4e41 4025 #define mmDIG5_AFMT_STATUS 0x4f41 4026 #define mmDIG6_AFMT_STATUS 0x5441 4027 #define mmDIG7_AFMT_STATUS 0x5641 4028 #define mmDIG8_AFMT_STATUS 0x5741 4029 #define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 4030 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 4031 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 4032 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 4033 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 4034 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 4035 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 4036 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 4037 #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642 4038 #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742 4039 #define mmAFMT_VBI_PACKET_CONTROL 0x4a43 4040 #define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 4041 #define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 4042 #define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 4043 #define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 4044 #define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 4045 #define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 4046 #define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 4047 #define mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643 4048 #define mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743 4049 #define mmAFMT_INFOFRAME_CONTROL0 0x4a44 4050 #define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 4051 #define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 4052 #define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 4053 #define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 4054 #define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 4055 #define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 4056 #define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 4057 #define mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644 4058 #define mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744 4059 #define mmAFMT_AUDIO_SRC_CONTROL 0x4a45 4060 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 4061 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 4062 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 4063 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 4064 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 4065 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 4066 #define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 4067 #define mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645 4068 #define mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745 4069 #define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 4070 #define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 4071 #define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 4072 #define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 4073 #define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 4074 #define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 4075 #define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 4076 #define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 4077 #define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646 4078 #define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746 4079 #define mmAFMT_CNTL 0x4a7e 4080 #define mmDIG0_AFMT_CNTL 0x4a7e 4081 #define mmDIG1_AFMT_CNTL 0x4b7e 4082 #define mmDIG2_AFMT_CNTL 0x4c7e 4083 #define mmDIG3_AFMT_CNTL 0x4d7e 4084 #define mmDIG4_AFMT_CNTL 0x4e7e 4085 #define mmDIG5_AFMT_CNTL 0x4f7e 4086 #define mmDIG6_AFMT_CNTL 0x547e 4087 #define mmDIG7_AFMT_CNTL 0x567e 4088 #define mmDIG8_AFMT_CNTL 0x577e 4089 #define mmDIG_BE_CNTL 0x4a47 4090 #define mmDIG0_DIG_BE_CNTL 0x4a47 4091 #define mmDIG1_DIG_BE_CNTL 0x4b47 4092 #define mmDIG2_DIG_BE_CNTL 0x4c47 4093 #define mmDIG3_DIG_BE_CNTL 0x4d47 4094 #define mmDIG4_DIG_BE_CNTL 0x4e47 4095 #define mmDIG5_DIG_BE_CNTL 0x4f47 4096 #define mmDIG6_DIG_BE_CNTL 0x5447 4097 #define mmDIG7_DIG_BE_CNTL 0x5647 4098 #define mmDIG8_DIG_BE_CNTL 0x5747 4099 #define mmDIG_BE_EN_CNTL 0x4a48 4100 #define mmDIG0_DIG_BE_EN_CNTL 0x4a48 4101 #define mmDIG1_DIG_BE_EN_CNTL 0x4b48 4102 #define mmDIG2_DIG_BE_EN_CNTL 0x4c48 4103 #define mmDIG3_DIG_BE_EN_CNTL 0x4d48 4104 #define mmDIG4_DIG_BE_EN_CNTL 0x4e48 4105 #define mmDIG5_DIG_BE_EN_CNTL 0x4f48 4106 #define mmDIG6_DIG_BE_EN_CNTL 0x5448 4107 #define mmDIG7_DIG_BE_EN_CNTL 0x5648 4108 #define mmDIG8_DIG_BE_EN_CNTL 0x5748 4109 #define mmTMDS_CNTL 0x4a6b 4110 #define mmDIG0_TMDS_CNTL 0x4a6b 4111 #define mmDIG1_TMDS_CNTL 0x4b6b 4112 #define mmDIG2_TMDS_CNTL 0x4c6b 4113 #define mmDIG3_TMDS_CNTL 0x4d6b 4114 #define mmDIG4_TMDS_CNTL 0x4e6b 4115 #define mmDIG5_TMDS_CNTL 0x4f6b 4116 #define mmDIG6_TMDS_CNTL 0x546b 4117 #define mmDIG7_TMDS_CNTL 0x566b 4118 #define mmDIG8_TMDS_CNTL 0x576b 4119 #define mmTMDS_CONTROL_CHAR 0x4a6c 4120 #define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c 4121 #define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c 4122 #define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c 4123 #define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c 4124 #define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c 4125 #define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c 4126 #define mmDIG6_TMDS_CONTROL_CHAR 0x546c 4127 #define mmDIG7_TMDS_CONTROL_CHAR 0x566c 4128 #define mmDIG8_TMDS_CONTROL_CHAR 0x576c 4129 #define mmTMDS_CONTROL0_FEEDBACK 0x4a6d 4130 #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d 4131 #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d 4132 #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d 4133 #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d 4134 #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d 4135 #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d 4136 #define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d 4137 #define mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d 4138 #define mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d 4139 #define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e 4140 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e 4141 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e 4142 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e 4143 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e 4144 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e 4145 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e 4146 #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e 4147 #define mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e 4148 #define mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e 4149 #define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f 4150 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f 4151 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f 4152 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f 4153 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f 4154 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f 4155 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f 4156 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f 4157 #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f 4158 #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f 4159 #define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 4160 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 4161 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 4162 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 4163 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 4164 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 4165 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 4166 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 4167 #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670 4168 #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770 4169 #define mmTMDS_DEBUG 0x4a71 4170 #define mmDIG0_TMDS_DEBUG 0x4a71 4171 #define mmDIG1_TMDS_DEBUG 0x4b71 4172 #define mmDIG2_TMDS_DEBUG 0x4c71 4173 #define mmDIG3_TMDS_DEBUG 0x4d71 4174 #define mmDIG4_TMDS_DEBUG 0x4e71 4175 #define mmDIG5_TMDS_DEBUG 0x4f71 4176 #define mmDIG6_TMDS_DEBUG 0x5471 4177 #define mmDIG7_TMDS_DEBUG 0x5671 4178 #define mmDIG8_TMDS_DEBUG 0x5771 4179 #define mmTMDS_CTL_BITS 0x4a72 4180 #define mmDIG0_TMDS_CTL_BITS 0x4a72 4181 #define mmDIG1_TMDS_CTL_BITS 0x4b72 4182 #define mmDIG2_TMDS_CTL_BITS 0x4c72 4183 #define mmDIG3_TMDS_CTL_BITS 0x4d72 4184 #define mmDIG4_TMDS_CTL_BITS 0x4e72 4185 #define mmDIG5_TMDS_CTL_BITS 0x4f72 4186 #define mmDIG6_TMDS_CTL_BITS 0x5472 4187 #define mmDIG7_TMDS_CTL_BITS 0x5672 4188 #define mmDIG8_TMDS_CTL_BITS 0x5772 4189 #define mmTMDS_DCBALANCER_CONTROL 0x4a73 4190 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 4191 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 4192 #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 4193 #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 4194 #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 4195 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 4196 #define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 4197 #define mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673 4198 #define mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773 4199 #define mmTMDS_CTL0_1_GEN_CNTL 0x4a75 4200 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 4201 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 4202 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 4203 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 4204 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 4205 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 4206 #define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 4207 #define mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675 4208 #define mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775 4209 #define mmTMDS_CTL2_3_GEN_CNTL 0x4a76 4210 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 4211 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 4212 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 4213 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 4214 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 4215 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 4216 #define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 4217 #define mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676 4218 #define mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776 4219 #define mmDIG_VERSION 0x4a78 4220 #define mmDIG0_DIG_VERSION 0x4a78 4221 #define mmDIG1_DIG_VERSION 0x4b78 4222 #define mmDIG2_DIG_VERSION 0x4c78 4223 #define mmDIG3_DIG_VERSION 0x4d78 4224 #define mmDIG4_DIG_VERSION 0x4e78 4225 #define mmDIG5_DIG_VERSION 0x4f78 4226 #define mmDIG6_DIG_VERSION 0x5478 4227 #define mmDIG7_DIG_VERSION 0x5678 4228 #define mmDIG8_DIG_VERSION 0x5778 4229 #define mmDIG_LANE_ENABLE 0x4a79 4230 #define mmDIG0_DIG_LANE_ENABLE 0x4a79 4231 #define mmDIG1_DIG_LANE_ENABLE 0x4b79 4232 #define mmDIG2_DIG_LANE_ENABLE 0x4c79 4233 #define mmDIG3_DIG_LANE_ENABLE 0x4d79 4234 #define mmDIG4_DIG_LANE_ENABLE 0x4e79 4235 #define mmDIG5_DIG_LANE_ENABLE 0x4f79 4236 #define mmDIG6_DIG_LANE_ENABLE 0x5479 4237 #define mmDIG7_DIG_LANE_ENABLE 0x5679 4238 #define mmDIG8_DIG_LANE_ENABLE 0x5779 4239 #define mmDIG_TEST_DEBUG_INDEX 0x4a7a 4240 #define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a 4241 #define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a 4242 #define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a 4243 #define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a 4244 #define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a 4245 #define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a 4246 #define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a 4247 #define mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a 4248 #define mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a 4249 #define mmDIG_TEST_DEBUG_DATA 0x4a7b 4250 #define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b 4251 #define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b 4252 #define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b 4253 #define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b 4254 #define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b 4255 #define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b 4256 #define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b 4257 #define mmDIG7_DIG_TEST_DEBUG_DATA 0x567b 4258 #define mmDIG8_DIG_TEST_DEBUG_DATA 0x577b 4259 #define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c 4260 #define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c 4261 #define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c 4262 #define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c 4263 #define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c 4264 #define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c 4265 #define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c 4266 #define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c 4267 #define mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c 4268 #define mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c 4269 #define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d 4270 #define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d 4271 #define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d 4272 #define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d 4273 #define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d 4274 #define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d 4275 #define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d 4276 #define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d 4277 #define mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d 4278 #define mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d 4279 #define mmDMCU_CTRL 0x1600 4280 #define mmDMCU_STATUS 0x1601 4281 #define mmDMCU_PC_START_ADDR 0x1602 4282 #define mmDMCU_FW_START_ADDR 0x1603 4283 #define mmDMCU_FW_END_ADDR 0x1604 4284 #define mmDMCU_FW_ISR_START_ADDR 0x1605 4285 #define mmDMCU_FW_CS_HI 0x1606 4286 #define mmDMCU_FW_CS_LO 0x1607 4287 #define mmDMCU_RAM_ACCESS_CTRL 0x1608 4288 #define mmDMCU_ERAM_WR_CTRL 0x1609 4289 #define mmDMCU_ERAM_WR_DATA 0x160a 4290 #define mmDMCU_ERAM_RD_CTRL 0x160b 4291 #define mmDMCU_ERAM_RD_DATA 0x160c 4292 #define mmDMCU_IRAM_WR_CTRL 0x160d 4293 #define mmDMCU_IRAM_WR_DATA 0x160e 4294 #define mmDMCU_IRAM_RD_CTRL 0x160f 4295 #define mmDMCU_IRAM_RD_DATA 0x1610 4296 #define mmDMCU_EVENT_TRIGGER 0x1611 4297 #define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 4298 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 4299 #define mmDMCU_INTERRUPT_STATUS 0x1614 4300 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 4301 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 4302 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631 4303 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 4304 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632 4305 #define mmDC_DMCU_SCRATCH 0x1618 4306 #define mmDMCU_INT_CNT 0x1619 4307 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a 4308 #define mmDMCU_UC_CLK_GATING_CNTL 0x161b 4309 #define mmMASTER_COMM_DATA_REG1 0x161c 4310 #define mmMASTER_COMM_DATA_REG2 0x161d 4311 #define mmMASTER_COMM_DATA_REG3 0x161e 4312 #define mmMASTER_COMM_CMD_REG 0x161f 4313 #define mmMASTER_COMM_CNTL_REG 0x1620 4314 #define mmSLAVE_COMM_DATA_REG1 0x1621 4315 #define mmSLAVE_COMM_DATA_REG2 0x1622 4316 #define mmSLAVE_COMM_DATA_REG3 0x1623 4317 #define mmSLAVE_COMM_CMD_REG 0x1624 4318 #define mmSLAVE_COMM_CNTL_REG 0x1625 4319 #define mmDMCU_TEST_DEBUG_INDEX 0x1626 4320 #define mmDMCU_TEST_DEBUG_DATA 0x1627 4321 #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 4322 #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 4323 #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 4324 #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 4325 #define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 4326 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 4327 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 4328 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 4329 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 4330 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 4331 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 4332 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 4333 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a 4334 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b 4335 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 4336 #define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 4337 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 4338 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 4339 #define mmDP_LINK_CNTL 0x4aa0 4340 #define mmDP0_DP_LINK_CNTL 0x4aa0 4341 #define mmDP1_DP_LINK_CNTL 0x4ba0 4342 #define mmDP2_DP_LINK_CNTL 0x4ca0 4343 #define mmDP3_DP_LINK_CNTL 0x4da0 4344 #define mmDP4_DP_LINK_CNTL 0x4ea0 4345 #define mmDP5_DP_LINK_CNTL 0x4fa0 4346 #define mmDP6_DP_LINK_CNTL 0x54a0 4347 #define mmDP7_DP_LINK_CNTL 0x56a0 4348 #define mmDP8_DP_LINK_CNTL 0x57a0 4349 #define mmDP_PIXEL_FORMAT 0x4aa1 4350 #define mmDP0_DP_PIXEL_FORMAT 0x4aa1 4351 #define mmDP1_DP_PIXEL_FORMAT 0x4ba1 4352 #define mmDP2_DP_PIXEL_FORMAT 0x4ca1 4353 #define mmDP3_DP_PIXEL_FORMAT 0x4da1 4354 #define mmDP4_DP_PIXEL_FORMAT 0x4ea1 4355 #define mmDP5_DP_PIXEL_FORMAT 0x4fa1 4356 #define mmDP6_DP_PIXEL_FORMAT 0x54a1 4357 #define mmDP7_DP_PIXEL_FORMAT 0x56a1 4358 #define mmDP8_DP_PIXEL_FORMAT 0x57a1 4359 #define mmDP_MSA_COLORIMETRY 0x4aa2 4360 #define mmDP0_DP_MSA_COLORIMETRY 0x4aa2 4361 #define mmDP1_DP_MSA_COLORIMETRY 0x4ba2 4362 #define mmDP2_DP_MSA_COLORIMETRY 0x4ca2 4363 #define mmDP3_DP_MSA_COLORIMETRY 0x4da2 4364 #define mmDP4_DP_MSA_COLORIMETRY 0x4ea2 4365 #define mmDP5_DP_MSA_COLORIMETRY 0x4fa2 4366 #define mmDP6_DP_MSA_COLORIMETRY 0x54a2 4367 #define mmDP7_DP_MSA_COLORIMETRY 0x56a2 4368 #define mmDP8_DP_MSA_COLORIMETRY 0x57a2 4369 #define mmDP_CONFIG 0x4aa3 4370 #define mmDP0_DP_CONFIG 0x4aa3 4371 #define mmDP1_DP_CONFIG 0x4ba3 4372 #define mmDP2_DP_CONFIG 0x4ca3 4373 #define mmDP3_DP_CONFIG 0x4da3 4374 #define mmDP4_DP_CONFIG 0x4ea3 4375 #define mmDP5_DP_CONFIG 0x4fa3 4376 #define mmDP6_DP_CONFIG 0x54a3 4377 #define mmDP7_DP_CONFIG 0x56a3 4378 #define mmDP8_DP_CONFIG 0x57a3 4379 #define mmDP_VID_STREAM_CNTL 0x4aa4 4380 #define mmDP0_DP_VID_STREAM_CNTL 0x4aa4 4381 #define mmDP1_DP_VID_STREAM_CNTL 0x4ba4 4382 #define mmDP2_DP_VID_STREAM_CNTL 0x4ca4 4383 #define mmDP3_DP_VID_STREAM_CNTL 0x4da4 4384 #define mmDP4_DP_VID_STREAM_CNTL 0x4ea4 4385 #define mmDP5_DP_VID_STREAM_CNTL 0x4fa4 4386 #define mmDP6_DP_VID_STREAM_CNTL 0x54a4 4387 #define mmDP7_DP_VID_STREAM_CNTL 0x56a4 4388 #define mmDP8_DP_VID_STREAM_CNTL 0x57a4 4389 #define mmDP_STEER_FIFO 0x4aa5 4390 #define mmDP0_DP_STEER_FIFO 0x4aa5 4391 #define mmDP1_DP_STEER_FIFO 0x4ba5 4392 #define mmDP2_DP_STEER_FIFO 0x4ca5 4393 #define mmDP3_DP_STEER_FIFO 0x4da5 4394 #define mmDP4_DP_STEER_FIFO 0x4ea5 4395 #define mmDP5_DP_STEER_FIFO 0x4fa5 4396 #define mmDP6_DP_STEER_FIFO 0x54a5 4397 #define mmDP7_DP_STEER_FIFO 0x56a5 4398 #define mmDP8_DP_STEER_FIFO 0x57a5 4399 #define mmDP_MSA_MISC 0x4aa6 4400 #define mmDP0_DP_MSA_MISC 0x4aa6 4401 #define mmDP1_DP_MSA_MISC 0x4ba6 4402 #define mmDP2_DP_MSA_MISC 0x4ca6 4403 #define mmDP3_DP_MSA_MISC 0x4da6 4404 #define mmDP4_DP_MSA_MISC 0x4ea6 4405 #define mmDP5_DP_MSA_MISC 0x4fa6 4406 #define mmDP6_DP_MSA_MISC 0x54a6 4407 #define mmDP7_DP_MSA_MISC 0x56a6 4408 #define mmDP8_DP_MSA_MISC 0x57a6 4409 #define mmDP_VID_TIMING 0x4aa8 4410 #define mmDP0_DP_VID_TIMING 0x4aa8 4411 #define mmDP1_DP_VID_TIMING 0x4ba8 4412 #define mmDP2_DP_VID_TIMING 0x4ca8 4413 #define mmDP3_DP_VID_TIMING 0x4da8 4414 #define mmDP4_DP_VID_TIMING 0x4ea8 4415 #define mmDP5_DP_VID_TIMING 0x4fa8 4416 #define mmDP6_DP_VID_TIMING 0x54a8 4417 #define mmDP7_DP_VID_TIMING 0x56a8 4418 #define mmDP8_DP_VID_TIMING 0x57a8 4419 #define mmDP_VID_N 0x4aa9 4420 #define mmDP0_DP_VID_N 0x4aa9 4421 #define mmDP1_DP_VID_N 0x4ba9 4422 #define mmDP2_DP_VID_N 0x4ca9 4423 #define mmDP3_DP_VID_N 0x4da9 4424 #define mmDP4_DP_VID_N 0x4ea9 4425 #define mmDP5_DP_VID_N 0x4fa9 4426 #define mmDP6_DP_VID_N 0x54a9 4427 #define mmDP7_DP_VID_N 0x56a9 4428 #define mmDP8_DP_VID_N 0x57a9 4429 #define mmDP_VID_M 0x4aaa 4430 #define mmDP0_DP_VID_M 0x4aaa 4431 #define mmDP1_DP_VID_M 0x4baa 4432 #define mmDP2_DP_VID_M 0x4caa 4433 #define mmDP3_DP_VID_M 0x4daa 4434 #define mmDP4_DP_VID_M 0x4eaa 4435 #define mmDP5_DP_VID_M 0x4faa 4436 #define mmDP6_DP_VID_M 0x54aa 4437 #define mmDP7_DP_VID_M 0x56aa 4438 #define mmDP8_DP_VID_M 0x57aa 4439 #define mmDP_LINK_FRAMING_CNTL 0x4aab 4440 #define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab 4441 #define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab 4442 #define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab 4443 #define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab 4444 #define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab 4445 #define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab 4446 #define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab 4447 #define mmDP7_DP_LINK_FRAMING_CNTL 0x56ab 4448 #define mmDP8_DP_LINK_FRAMING_CNTL 0x57ab 4449 #define mmDP_HBR2_EYE_PATTERN 0x4aac 4450 #define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac 4451 #define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac 4452 #define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac 4453 #define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac 4454 #define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac 4455 #define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac 4456 #define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac 4457 #define mmDP7_DP_HBR2_EYE_PATTERN 0x56ac 4458 #define mmDP8_DP_HBR2_EYE_PATTERN 0x57ac 4459 #define mmDP_VID_MSA_VBID 0x4aad 4460 #define mmDP0_DP_VID_MSA_VBID 0x4aad 4461 #define mmDP1_DP_VID_MSA_VBID 0x4bad 4462 #define mmDP2_DP_VID_MSA_VBID 0x4cad 4463 #define mmDP3_DP_VID_MSA_VBID 0x4dad 4464 #define mmDP4_DP_VID_MSA_VBID 0x4ead 4465 #define mmDP5_DP_VID_MSA_VBID 0x4fad 4466 #define mmDP6_DP_VID_MSA_VBID 0x54ad 4467 #define mmDP7_DP_VID_MSA_VBID 0x56ad 4468 #define mmDP8_DP_VID_MSA_VBID 0x57ad 4469 #define mmDP_VID_INTERRUPT_CNTL 0x4aae 4470 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae 4471 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae 4472 #define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae 4473 #define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae 4474 #define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae 4475 #define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae 4476 #define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae 4477 #define mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae 4478 #define mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae 4479 #define mmDP_DPHY_CNTL 0x4aaf 4480 #define mmDP0_DP_DPHY_CNTL 0x4aaf 4481 #define mmDP1_DP_DPHY_CNTL 0x4baf 4482 #define mmDP2_DP_DPHY_CNTL 0x4caf 4483 #define mmDP3_DP_DPHY_CNTL 0x4daf 4484 #define mmDP4_DP_DPHY_CNTL 0x4eaf 4485 #define mmDP5_DP_DPHY_CNTL 0x4faf 4486 #define mmDP6_DP_DPHY_CNTL 0x54af 4487 #define mmDP7_DP_DPHY_CNTL 0x56af 4488 #define mmDP8_DP_DPHY_CNTL 0x57af 4489 #define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 4490 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 4491 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 4492 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 4493 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 4494 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 4495 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 4496 #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 4497 #define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0 4498 #define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0 4499 #define mmDP_DPHY_SYM0 0x4ab1 4500 #define mmDP0_DP_DPHY_SYM0 0x4ab1 4501 #define mmDP1_DP_DPHY_SYM0 0x4bb1 4502 #define mmDP2_DP_DPHY_SYM0 0x4cb1 4503 #define mmDP3_DP_DPHY_SYM0 0x4db1 4504 #define mmDP4_DP_DPHY_SYM0 0x4eb1 4505 #define mmDP5_DP_DPHY_SYM0 0x4fb1 4506 #define mmDP6_DP_DPHY_SYM0 0x54b1 4507 #define mmDP7_DP_DPHY_SYM0 0x56b1 4508 #define mmDP8_DP_DPHY_SYM0 0x57b1 4509 #define mmDP_DPHY_SYM1 0x4ab2 4510 #define mmDP0_DP_DPHY_SYM1 0x4ab2 4511 #define mmDP1_DP_DPHY_SYM1 0x4bb2 4512 #define mmDP2_DP_DPHY_SYM1 0x4cb2 4513 #define mmDP3_DP_DPHY_SYM1 0x4db2 4514 #define mmDP4_DP_DPHY_SYM1 0x4eb2 4515 #define mmDP5_DP_DPHY_SYM1 0x4fb2 4516 #define mmDP6_DP_DPHY_SYM1 0x54b2 4517 #define mmDP7_DP_DPHY_SYM1 0x56b2 4518 #define mmDP8_DP_DPHY_SYM1 0x57b2 4519 #define mmDP_DPHY_SYM2 0x4ab3 4520 #define mmDP0_DP_DPHY_SYM2 0x4ab3 4521 #define mmDP1_DP_DPHY_SYM2 0x4bb3 4522 #define mmDP2_DP_DPHY_SYM2 0x4cb3 4523 #define mmDP3_DP_DPHY_SYM2 0x4db3 4524 #define mmDP4_DP_DPHY_SYM2 0x4eb3 4525 #define mmDP5_DP_DPHY_SYM2 0x4fb3 4526 #define mmDP6_DP_DPHY_SYM2 0x54b3 4527 #define mmDP7_DP_DPHY_SYM2 0x56b3 4528 #define mmDP8_DP_DPHY_SYM2 0x57b3 4529 #define mmDP_DPHY_8B10B_CNTL 0x4ab4 4530 #define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 4531 #define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 4532 #define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 4533 #define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 4534 #define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 4535 #define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 4536 #define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 4537 #define mmDP7_DP_DPHY_8B10B_CNTL 0x56b4 4538 #define mmDP8_DP_DPHY_8B10B_CNTL 0x57b4 4539 #define mmDP_DPHY_PRBS_CNTL 0x4ab5 4540 #define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 4541 #define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 4542 #define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 4543 #define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 4544 #define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 4545 #define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 4546 #define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 4547 #define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 4548 #define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 4549 #define mmDP_DPHY_SCRAM_CNTL 0x4ab6 4550 #define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6 4551 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 4552 #define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6 4553 #define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6 4554 #define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6 4555 #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6 4556 #define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6 4557 #define mmDP8_DP_DPHY_SCRAM_CNTL 0x56b6 4558 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc 4559 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc 4560 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc 4561 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc 4562 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc 4563 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc 4564 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc 4565 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc 4566 #define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc 4567 #define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc 4568 #define mmDP_DPHY_CRC_EN 0x4ab7 4569 #define mmDP0_DP_DPHY_CRC_EN 0x4ab7 4570 #define mmDP1_DP_DPHY_CRC_EN 0x4bb7 4571 #define mmDP2_DP_DPHY_CRC_EN 0x4cb7 4572 #define mmDP3_DP_DPHY_CRC_EN 0x4db7 4573 #define mmDP4_DP_DPHY_CRC_EN 0x4eb7 4574 #define mmDP5_DP_DPHY_CRC_EN 0x4fb7 4575 #define mmDP6_DP_DPHY_CRC_EN 0x54b7 4576 #define mmDP7_DP_DPHY_CRC_EN 0x56b7 4577 #define mmDP8_DP_DPHY_CRC_EN 0x57b7 4578 #define mmDP_DPHY_CRC_CNTL 0x4ab8 4579 #define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 4580 #define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 4581 #define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 4582 #define mmDP3_DP_DPHY_CRC_CNTL 0x4db8 4583 #define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 4584 #define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 4585 #define mmDP6_DP_DPHY_CRC_CNTL 0x54b8 4586 #define mmDP7_DP_DPHY_CRC_CNTL 0x56b8 4587 #define mmDP8_DP_DPHY_CRC_CNTL 0x57b8 4588 #define mmDP_DPHY_CRC_RESULT 0x4ab9 4589 #define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 4590 #define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 4591 #define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 4592 #define mmDP3_DP_DPHY_CRC_RESULT 0x4db9 4593 #define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 4594 #define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 4595 #define mmDP6_DP_DPHY_CRC_RESULT 0x54b9 4596 #define mmDP7_DP_DPHY_CRC_RESULT 0x56b9 4597 #define mmDP8_DP_DPHY_CRC_RESULT 0x57b9 4598 #define mmDP_DPHY_CRC_MST_CNTL 0x4aba 4599 #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba 4600 #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba 4601 #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba 4602 #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba 4603 #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba 4604 #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba 4605 #define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba 4606 #define mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba 4607 #define mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba 4608 #define mmDP_DPHY_CRC_MST_STATUS 0x4abb 4609 #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb 4610 #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb 4611 #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb 4612 #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb 4613 #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb 4614 #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb 4615 #define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb 4616 #define mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb 4617 #define mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb 4618 #define mmDP_DPHY_FAST_TRAINING 0x4abc 4619 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc 4620 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc 4621 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc 4622 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc 4623 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc 4624 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc 4625 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc 4626 #define mmDP7_DP_DPHY_FAST_TRAINING 0x56bc 4627 #define mmDP8_DP_DPHY_FAST_TRAINING 0x57bc 4628 #define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd 4629 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd 4630 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd 4631 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd 4632 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd 4633 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd 4634 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd 4635 #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd 4636 #define mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd 4637 #define mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd 4638 #define mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add 4639 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add 4640 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd 4641 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd 4642 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd 4643 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd 4644 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd 4645 #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd 4646 #define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd 4647 #define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd 4648 #define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe 4649 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe 4650 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe 4651 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe 4652 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe 4653 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe 4654 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe 4655 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be 4656 #define mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be 4657 #define mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be 4658 #define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf 4659 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf 4660 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf 4661 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf 4662 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf 4663 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf 4664 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf 4665 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf 4666 #define mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf 4667 #define mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf 4668 #define mmDP_SEC_CNTL 0x4ac3 4669 #define mmDP0_DP_SEC_CNTL 0x4ac3 4670 #define mmDP1_DP_SEC_CNTL 0x4bc3 4671 #define mmDP2_DP_SEC_CNTL 0x4cc3 4672 #define mmDP3_DP_SEC_CNTL 0x4dc3 4673 #define mmDP4_DP_SEC_CNTL 0x4ec3 4674 #define mmDP5_DP_SEC_CNTL 0x4fc3 4675 #define mmDP6_DP_SEC_CNTL 0x54c3 4676 #define mmDP7_DP_SEC_CNTL 0x56c3 4677 #define mmDP8_DP_SEC_CNTL 0x57c3 4678 #define mmDP_SEC_CNTL1 0x4ac4 4679 #define mmDP0_DP_SEC_CNTL1 0x4ac4 4680 #define mmDP1_DP_SEC_CNTL1 0x4bc4 4681 #define mmDP2_DP_SEC_CNTL1 0x4cc4 4682 #define mmDP3_DP_SEC_CNTL1 0x4dc4 4683 #define mmDP4_DP_SEC_CNTL1 0x4ec4 4684 #define mmDP5_DP_SEC_CNTL1 0x4fc4 4685 #define mmDP6_DP_SEC_CNTL1 0x54c4 4686 #define mmDP7_DP_SEC_CNTL1 0x56c4 4687 #define mmDP8_DP_SEC_CNTL1 0x57c4 4688 #define mmDP_SEC_FRAMING1 0x4ac5 4689 #define mmDP0_DP_SEC_FRAMING1 0x4ac5 4690 #define mmDP1_DP_SEC_FRAMING1 0x4bc5 4691 #define mmDP2_DP_SEC_FRAMING1 0x4cc5 4692 #define mmDP3_DP_SEC_FRAMING1 0x4dc5 4693 #define mmDP4_DP_SEC_FRAMING1 0x4ec5 4694 #define mmDP5_DP_SEC_FRAMING1 0x4fc5 4695 #define mmDP6_DP_SEC_FRAMING1 0x54c5 4696 #define mmDP7_DP_SEC_FRAMING1 0x56c5 4697 #define mmDP8_DP_SEC_FRAMING1 0x57c5 4698 #define mmDP_SEC_FRAMING2 0x4ac6 4699 #define mmDP0_DP_SEC_FRAMING2 0x4ac6 4700 #define mmDP1_DP_SEC_FRAMING2 0x4bc6 4701 #define mmDP2_DP_SEC_FRAMING2 0x4cc6 4702 #define mmDP3_DP_SEC_FRAMING2 0x4dc6 4703 #define mmDP4_DP_SEC_FRAMING2 0x4ec6 4704 #define mmDP5_DP_SEC_FRAMING2 0x4fc6 4705 #define mmDP6_DP_SEC_FRAMING2 0x54c6 4706 #define mmDP7_DP_SEC_FRAMING2 0x56c6 4707 #define mmDP8_DP_SEC_FRAMING2 0x57c6 4708 #define mmDP_SEC_FRAMING3 0x4ac7 4709 #define mmDP0_DP_SEC_FRAMING3 0x4ac7 4710 #define mmDP1_DP_SEC_FRAMING3 0x4bc7 4711 #define mmDP2_DP_SEC_FRAMING3 0x4cc7 4712 #define mmDP3_DP_SEC_FRAMING3 0x4dc7 4713 #define mmDP4_DP_SEC_FRAMING3 0x4ec7 4714 #define mmDP5_DP_SEC_FRAMING3 0x4fc7 4715 #define mmDP6_DP_SEC_FRAMING3 0x54c7 4716 #define mmDP7_DP_SEC_FRAMING3 0x56c7 4717 #define mmDP8_DP_SEC_FRAMING3 0x57c7 4718 #define mmDP_SEC_FRAMING4 0x4ac8 4719 #define mmDP0_DP_SEC_FRAMING4 0x4ac8 4720 #define mmDP1_DP_SEC_FRAMING4 0x4bc8 4721 #define mmDP2_DP_SEC_FRAMING4 0x4cc8 4722 #define mmDP3_DP_SEC_FRAMING4 0x4dc8 4723 #define mmDP4_DP_SEC_FRAMING4 0x4ec8 4724 #define mmDP5_DP_SEC_FRAMING4 0x4fc8 4725 #define mmDP6_DP_SEC_FRAMING4 0x54c8 4726 #define mmDP7_DP_SEC_FRAMING4 0x56c8 4727 #define mmDP8_DP_SEC_FRAMING4 0x57c8 4728 #define mmDP_SEC_AUD_N 0x4ac9 4729 #define mmDP0_DP_SEC_AUD_N 0x4ac9 4730 #define mmDP1_DP_SEC_AUD_N 0x4bc9 4731 #define mmDP2_DP_SEC_AUD_N 0x4cc9 4732 #define mmDP3_DP_SEC_AUD_N 0x4dc9 4733 #define mmDP4_DP_SEC_AUD_N 0x4ec9 4734 #define mmDP5_DP_SEC_AUD_N 0x4fc9 4735 #define mmDP6_DP_SEC_AUD_N 0x54c9 4736 #define mmDP7_DP_SEC_AUD_N 0x56c9 4737 #define mmDP8_DP_SEC_AUD_N 0x57c9 4738 #define mmDP_SEC_AUD_N_READBACK 0x4aca 4739 #define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca 4740 #define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca 4741 #define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca 4742 #define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca 4743 #define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca 4744 #define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca 4745 #define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca 4746 #define mmDP7_DP_SEC_AUD_N_READBACK 0x56ca 4747 #define mmDP8_DP_SEC_AUD_N_READBACK 0x57ca 4748 #define mmDP_SEC_AUD_M 0x4acb 4749 #define mmDP0_DP_SEC_AUD_M 0x4acb 4750 #define mmDP1_DP_SEC_AUD_M 0x4bcb 4751 #define mmDP2_DP_SEC_AUD_M 0x4ccb 4752 #define mmDP3_DP_SEC_AUD_M 0x4dcb 4753 #define mmDP4_DP_SEC_AUD_M 0x4ecb 4754 #define mmDP5_DP_SEC_AUD_M 0x4fcb 4755 #define mmDP6_DP_SEC_AUD_M 0x54cb 4756 #define mmDP7_DP_SEC_AUD_M 0x56cb 4757 #define mmDP8_DP_SEC_AUD_M 0x57cb 4758 #define mmDP_SEC_AUD_M_READBACK 0x4acc 4759 #define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc 4760 #define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc 4761 #define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc 4762 #define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc 4763 #define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc 4764 #define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc 4765 #define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc 4766 #define mmDP7_DP_SEC_AUD_M_READBACK 0x56cc 4767 #define mmDP8_DP_SEC_AUD_M_READBACK 0x57cc 4768 #define mmDP_SEC_TIMESTAMP 0x4acd 4769 #define mmDP0_DP_SEC_TIMESTAMP 0x4acd 4770 #define mmDP1_DP_SEC_TIMESTAMP 0x4bcd 4771 #define mmDP2_DP_SEC_TIMESTAMP 0x4ccd 4772 #define mmDP3_DP_SEC_TIMESTAMP 0x4dcd 4773 #define mmDP4_DP_SEC_TIMESTAMP 0x4ecd 4774 #define mmDP5_DP_SEC_TIMESTAMP 0x4fcd 4775 #define mmDP6_DP_SEC_TIMESTAMP 0x54cd 4776 #define mmDP7_DP_SEC_TIMESTAMP 0x56cd 4777 #define mmDP8_DP_SEC_TIMESTAMP 0x57cd 4778 #define mmDP_SEC_PACKET_CNTL 0x4ace 4779 #define mmDP0_DP_SEC_PACKET_CNTL 0x4ace 4780 #define mmDP1_DP_SEC_PACKET_CNTL 0x4bce 4781 #define mmDP2_DP_SEC_PACKET_CNTL 0x4cce 4782 #define mmDP3_DP_SEC_PACKET_CNTL 0x4dce 4783 #define mmDP4_DP_SEC_PACKET_CNTL 0x4ece 4784 #define mmDP5_DP_SEC_PACKET_CNTL 0x4fce 4785 #define mmDP6_DP_SEC_PACKET_CNTL 0x54ce 4786 #define mmDP7_DP_SEC_PACKET_CNTL 0x56ce 4787 #define mmDP8_DP_SEC_PACKET_CNTL 0x57ce 4788 #define mmDP_MSE_RATE_CNTL 0x4acf 4789 #define mmDP0_DP_MSE_RATE_CNTL 0x4acf 4790 #define mmDP1_DP_MSE_RATE_CNTL 0x4bcf 4791 #define mmDP2_DP_MSE_RATE_CNTL 0x4ccf 4792 #define mmDP3_DP_MSE_RATE_CNTL 0x4dcf 4793 #define mmDP4_DP_MSE_RATE_CNTL 0x4ecf 4794 #define mmDP5_DP_MSE_RATE_CNTL 0x4fcf 4795 #define mmDP6_DP_MSE_RATE_CNTL 0x54cf 4796 #define mmDP7_DP_MSE_RATE_CNTL 0x56cf 4797 #define mmDP8_DP_MSE_RATE_CNTL 0x57cf 4798 #define mmDP_MSE_RATE_UPDATE 0x4ad1 4799 #define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 4800 #define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 4801 #define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 4802 #define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 4803 #define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 4804 #define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 4805 #define mmDP6_DP_MSE_RATE_UPDATE 0x54d1 4806 #define mmDP7_DP_MSE_RATE_UPDATE 0x56d1 4807 #define mmDP8_DP_MSE_RATE_UPDATE 0x57d1 4808 #define mmDP_MSE_SAT0 0x4ad2 4809 #define mmDP0_DP_MSE_SAT0 0x4ad2 4810 #define mmDP1_DP_MSE_SAT0 0x4bd2 4811 #define mmDP2_DP_MSE_SAT0 0x4cd2 4812 #define mmDP3_DP_MSE_SAT0 0x4dd2 4813 #define mmDP4_DP_MSE_SAT0 0x4ed2 4814 #define mmDP5_DP_MSE_SAT0 0x4fd2 4815 #define mmDP6_DP_MSE_SAT0 0x54d2 4816 #define mmDP7_DP_MSE_SAT0 0x56d2 4817 #define mmDP8_DP_MSE_SAT0 0x57d2 4818 #define mmDP_MSE_SAT1 0x4ad3 4819 #define mmDP0_DP_MSE_SAT1 0x4ad3 4820 #define mmDP1_DP_MSE_SAT1 0x4bd3 4821 #define mmDP2_DP_MSE_SAT1 0x4cd3 4822 #define mmDP3_DP_MSE_SAT1 0x4dd3 4823 #define mmDP4_DP_MSE_SAT1 0x4ed3 4824 #define mmDP5_DP_MSE_SAT1 0x4fd3 4825 #define mmDP6_DP_MSE_SAT1 0x54d3 4826 #define mmDP7_DP_MSE_SAT1 0x56d3 4827 #define mmDP8_DP_MSE_SAT1 0x57d3 4828 #define mmDP_MSE_SAT2 0x4ad4 4829 #define mmDP0_DP_MSE_SAT2 0x4ad4 4830 #define mmDP1_DP_MSE_SAT2 0x4bd4 4831 #define mmDP2_DP_MSE_SAT2 0x4cd4 4832 #define mmDP3_DP_MSE_SAT2 0x4dd4 4833 #define mmDP4_DP_MSE_SAT2 0x4ed4 4834 #define mmDP5_DP_MSE_SAT2 0x4fd4 4835 #define mmDP6_DP_MSE_SAT2 0x54d4 4836 #define mmDP7_DP_MSE_SAT2 0x56d4 4837 #define mmDP8_DP_MSE_SAT2 0x57d4 4838 #define mmDP_MSE_SAT_UPDATE 0x4ad5 4839 #define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 4840 #define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 4841 #define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 4842 #define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 4843 #define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 4844 #define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 4845 #define mmDP6_DP_MSE_SAT_UPDATE 0x54d5 4846 #define mmDP7_DP_MSE_SAT_UPDATE 0x56d5 4847 #define mmDP8_DP_MSE_SAT_UPDATE 0x57d5 4848 #define mmDP_MSE_LINK_TIMING 0x4ad6 4849 #define mmDP0_DP_MSE_LINK_TIMING 0x4ad6 4850 #define mmDP1_DP_MSE_LINK_TIMING 0x4bd6 4851 #define mmDP2_DP_MSE_LINK_TIMING 0x4cd6 4852 #define mmDP3_DP_MSE_LINK_TIMING 0x4dd6 4853 #define mmDP4_DP_MSE_LINK_TIMING 0x4ed6 4854 #define mmDP5_DP_MSE_LINK_TIMING 0x4fd6 4855 #define mmDP6_DP_MSE_LINK_TIMING 0x54d6 4856 #define mmDP7_DP_MSE_LINK_TIMING 0x56d6 4857 #define mmDP8_DP_MSE_LINK_TIMING 0x57d6 4858 #define mmDP_MSE_MISC_CNTL 0x4ad7 4859 #define mmDP0_DP_MSE_MISC_CNTL 0x4ad7 4860 #define mmDP1_DP_MSE_MISC_CNTL 0x4bd7 4861 #define mmDP2_DP_MSE_MISC_CNTL 0x4cd7 4862 #define mmDP3_DP_MSE_MISC_CNTL 0x4dd7 4863 #define mmDP4_DP_MSE_MISC_CNTL 0x4ed7 4864 #define mmDP5_DP_MSE_MISC_CNTL 0x4fd7 4865 #define mmDP6_DP_MSE_MISC_CNTL 0x54d7 4866 #define mmDP7_DP_MSE_MISC_CNTL 0x56d7 4867 #define mmDP8_DP_MSE_MISC_CNTL 0x57d7 4868 #define mmDP_TEST_DEBUG_INDEX 0x4ad8 4869 #define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 4870 #define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 4871 #define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 4872 #define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 4873 #define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 4874 #define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 4875 #define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 4876 #define mmDP7_DP_TEST_DEBUG_INDEX 0x56d8 4877 #define mmDP8_DP_TEST_DEBUG_INDEX 0x57d8 4878 #define mmDP_TEST_DEBUG_DATA 0x4ad9 4879 #define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 4880 #define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 4881 #define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 4882 #define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 4883 #define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 4884 #define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 4885 #define mmDP6_DP_TEST_DEBUG_DATA 0x54d9 4886 #define mmDP7_DP_TEST_DEBUG_DATA 0x56d9 4887 #define mmDP8_DP_TEST_DEBUG_DATA 0x57d9 4888 #define mmDP_FE_TEST_DEBUG_INDEX 0x4ada 4889 #define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada 4890 #define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda 4891 #define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda 4892 #define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda 4893 #define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda 4894 #define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda 4895 #define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da 4896 #define mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da 4897 #define mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da 4898 #define mmDP_FE_TEST_DEBUG_DATA 0x4adb 4899 #define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb 4900 #define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb 4901 #define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb 4902 #define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb 4903 #define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb 4904 #define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb 4905 #define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db 4906 #define mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db 4907 #define mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db 4908 #define mmAUX_CONTROL 0x5c00 4909 #define mmDP_AUX0_AUX_CONTROL 0x5c00 4910 #define mmDP_AUX1_AUX_CONTROL 0x5c1c 4911 #define mmDP_AUX2_AUX_CONTROL 0x5c38 4912 #define mmDP_AUX3_AUX_CONTROL 0x5c54 4913 #define mmDP_AUX4_AUX_CONTROL 0x5c70 4914 #define mmDP_AUX5_AUX_CONTROL 0x5c8c 4915 #define mmAUX_SW_CONTROL 0x5c01 4916 #define mmDP_AUX0_AUX_SW_CONTROL 0x5c01 4917 #define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d 4918 #define mmDP_AUX2_AUX_SW_CONTROL 0x5c39 4919 #define mmDP_AUX3_AUX_SW_CONTROL 0x5c55 4920 #define mmDP_AUX4_AUX_SW_CONTROL 0x5c71 4921 #define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d 4922 #define mmAUX_ARB_CONTROL 0x5c02 4923 #define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 4924 #define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e 4925 #define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a 4926 #define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 4927 #define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 4928 #define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e 4929 #define mmAUX_INTERRUPT_CONTROL 0x5c03 4930 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 4931 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f 4932 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b 4933 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 4934 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 4935 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f 4936 #define mmAUX_SW_STATUS 0x5c04 4937 #define mmDP_AUX0_AUX_SW_STATUS 0x5c04 4938 #define mmDP_AUX1_AUX_SW_STATUS 0x5c20 4939 #define mmDP_AUX2_AUX_SW_STATUS 0x5c3c 4940 #define mmDP_AUX3_AUX_SW_STATUS 0x5c58 4941 #define mmDP_AUX4_AUX_SW_STATUS 0x5c74 4942 #define mmDP_AUX5_AUX_SW_STATUS 0x5c90 4943 #define mmAUX_LS_STATUS 0x5c05 4944 #define mmDP_AUX0_AUX_LS_STATUS 0x5c05 4945 #define mmDP_AUX1_AUX_LS_STATUS 0x5c21 4946 #define mmDP_AUX2_AUX_LS_STATUS 0x5c3d 4947 #define mmDP_AUX3_AUX_LS_STATUS 0x5c59 4948 #define mmDP_AUX4_AUX_LS_STATUS 0x5c75 4949 #define mmDP_AUX5_AUX_LS_STATUS 0x5c91 4950 #define mmAUX_SW_DATA 0x5c06 4951 #define mmDP_AUX0_AUX_SW_DATA 0x5c06 4952 #define mmDP_AUX1_AUX_SW_DATA 0x5c22 4953 #define mmDP_AUX2_AUX_SW_DATA 0x5c3e 4954 #define mmDP_AUX3_AUX_SW_DATA 0x5c5a 4955 #define mmDP_AUX4_AUX_SW_DATA 0x5c76 4956 #define mmDP_AUX5_AUX_SW_DATA 0x5c92 4957 #define mmAUX_LS_DATA 0x5c07 4958 #define mmDP_AUX0_AUX_LS_DATA 0x5c07 4959 #define mmDP_AUX1_AUX_LS_DATA 0x5c23 4960 #define mmDP_AUX2_AUX_LS_DATA 0x5c3f 4961 #define mmDP_AUX3_AUX_LS_DATA 0x5c5b 4962 #define mmDP_AUX4_AUX_LS_DATA 0x5c77 4963 #define mmDP_AUX5_AUX_LS_DATA 0x5c93 4964 #define mmAUX_DPHY_TX_REF_CONTROL 0x5c08 4965 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 4966 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 4967 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 4968 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c 4969 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 4970 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 4971 #define mmAUX_DPHY_TX_CONTROL 0x5c09 4972 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 4973 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 4974 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 4975 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d 4976 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 4977 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 4978 #define mmAUX_DPHY_RX_CONTROL0 0x5c0a 4979 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a 4980 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 4981 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 4982 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e 4983 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a 4984 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 4985 #define mmAUX_DPHY_RX_CONTROL1 0x5c0b 4986 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b 4987 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 4988 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 4989 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f 4990 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b 4991 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 4992 #define mmAUX_DPHY_TX_STATUS 0x5c0c 4993 #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c 4994 #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 4995 #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 4996 #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 4997 #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c 4998 #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 4999 #define mmAUX_DPHY_RX_STATUS 0x5c0d 5000 #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d 5001 #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 5002 #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 5003 #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 5004 #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d 5005 #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 5006 #define mmAUX_GTC_SYNC_CONTROL 0x5c0e 5007 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e 5008 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a 5009 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 5010 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 5011 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e 5012 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a 5013 #define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f 5014 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f 5015 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b 5016 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 5017 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 5018 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f 5019 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b 5020 #define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 5021 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 5022 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c 5023 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 5024 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 5025 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 5026 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c 5027 #define mmAUX_GTC_SYNC_STATUS 0x5c11 5028 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 5029 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d 5030 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 5031 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 5032 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 5033 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d 5034 #define mmAUX_GTC_SYNC_DATA 0x5c12 5035 #define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 5036 #define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e 5037 #define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a 5038 #define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 5039 #define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 5040 #define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e 5041 #define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 5042 #define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 5043 #define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f 5044 #define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b 5045 #define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 5046 #define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 5047 #define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f 5048 #define mmAUX_TEST_DEBUG_INDEX 0x5c14 5049 #define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 5050 #define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 5051 #define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c 5052 #define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 5053 #define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 5054 #define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 5055 #define mmAUX_TEST_DEBUG_DATA 0x5c15 5056 #define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 5057 #define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 5058 #define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d 5059 #define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 5060 #define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 5061 #define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 5062 #define ixDP_AUX_DEBUG_A 0x10 5063 #define ixDP_AUX_DEBUG_B 0x11 5064 #define ixDP_AUX_DEBUG_C 0x12 5065 #define ixDP_AUX_DEBUG_D 0x13 5066 #define ixDP_AUX_DEBUG_E 0x14 5067 #define ixDP_AUX_DEBUG_F 0x15 5068 #define ixDP_AUX_DEBUG_G 0x16 5069 #define ixDP_AUX_DEBUG_H 0x17 5070 #define ixDP_AUX_DEBUG_I 0x18 5071 #define ixDP_AUX_DEBUG_J 0x19 5072 #define ixDP_AUX_DEBUG_K 0x1a 5073 #define ixDP_AUX_DEBUG_L 0x1b 5074 #define ixDP_AUX_DEBUG_M 0x1c 5075 #define ixDP_AUX_DEBUG_N 0x1d 5076 #define ixDP_AUX_DEBUG_O 0x1e 5077 #define ixDP_AUX_DEBUG_P 0x1f 5078 #define ixDP_AUX_DEBUG_Q 0x20 5079 #define mmDVO_ENABLE 0x16a0 5080 #define mmDVO_SOURCE_SELECT 0x16a1 5081 #define mmDVO_OUTPUT 0x16a2 5082 #define mmDVO_CONTROL 0x16a3 5083 #define mmDVO_CRC_EN 0x16a4 5084 #define mmDVO_CRC2_SIG_MASK 0x16a5 5085 #define mmDVO_CRC2_SIG_RESULT 0x16a6 5086 #define mmDVO_FIFO_ERROR_STATUS 0x16a7 5087 #define mmDVO_TEST_DEBUG_INDEX 0x16a8 5088 #define mmDVO_TEST_DEBUG_DATA 0x16a9 5089 #define mmFBC_CNTL 0x280 5090 #define mmFBC_IDLE_MASK 0x281 5091 #define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 5092 #define mmFBC_START_STOP_DELAY 0x283 5093 #define mmFBC_COMP_CNTL 0x284 5094 #define mmFBC_COMP_MODE 0x285 5095 #define mmFBC_DEBUG0 0x286 5096 #define mmFBC_DEBUG1 0x287 5097 #define mmFBC_DEBUG2 0x288 5098 #define mmFBC_IND_LUT0 0x289 5099 #define mmFBC_IND_LUT1 0x28a 5100 #define mmFBC_IND_LUT2 0x28b 5101 #define mmFBC_IND_LUT3 0x28c 5102 #define mmFBC_IND_LUT4 0x28d 5103 #define mmFBC_IND_LUT5 0x28e 5104 #define mmFBC_IND_LUT6 0x28f 5105 #define mmFBC_IND_LUT7 0x290 5106 #define mmFBC_IND_LUT8 0x291 5107 #define mmFBC_IND_LUT9 0x292 5108 #define mmFBC_IND_LUT10 0x293 5109 #define mmFBC_IND_LUT11 0x294 5110 #define mmFBC_IND_LUT12 0x295 5111 #define mmFBC_IND_LUT13 0x296 5112 #define mmFBC_IND_LUT14 0x297 5113 #define mmFBC_IND_LUT15 0x298 5114 #define mmFBC_CSM_REGION_OFFSET_01 0x299 5115 #define mmFBC_CSM_REGION_OFFSET_23 0x29a 5116 #define mmFBC_CLIENT_REGION_MASK 0x29b 5117 #define mmFBC_DEBUG_COMP 0x29c 5118 #define mmFBC_DEBUG_CSR 0x29d 5119 #define mmFBC_DEBUG_CSR_RDATA 0x29e 5120 #define mmFBC_DEBUG_CSR_WDATA 0x29f 5121 #define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 5122 #define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 5123 #define mmFBC_MISC 0x2a2 5124 #define mmFBC_STATUS 0x2a3 5125 #define mmFBC_TEST_DEBUG_INDEX 0x2a4 5126 #define mmFBC_TEST_DEBUG_DATA 0x2a5 5127 #define mmFMT_CLAMP_COMPONENT_R 0x1be8 5128 #define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 5129 #define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 5130 #define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 5131 #define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 5132 #define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 5133 #define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 5134 #define mmFMT_CLAMP_COMPONENT_G 0x1be9 5135 #define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 5136 #define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 5137 #define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 5138 #define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 5139 #define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 5140 #define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 5141 #define mmFMT_CLAMP_COMPONENT_B 0x1bea 5142 #define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea 5143 #define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea 5144 #define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea 5145 #define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea 5146 #define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea 5147 #define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea 5148 #define mmFMT_DYNAMIC_EXP_CNTL 0x1bed 5149 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed 5150 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded 5151 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed 5152 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed 5153 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed 5154 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed 5155 #define mmFMT_CONTROL 0x1bee 5156 #define mmFMT0_FMT_CONTROL 0x1bee 5157 #define mmFMT1_FMT_CONTROL 0x1dee 5158 #define mmFMT2_FMT_CONTROL 0x1fee 5159 #define mmFMT3_FMT_CONTROL 0x41ee 5160 #define mmFMT4_FMT_CONTROL 0x43ee 5161 #define mmFMT5_FMT_CONTROL 0x45ee 5162 #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 5163 #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 5164 #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 5165 #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 5166 #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 5167 #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 5168 #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 5169 #define mmFMT_DITHER_RAND_R_SEED 0x1bf3 5170 #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 5171 #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 5172 #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 5173 #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 5174 #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 5175 #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 5176 #define mmFMT_DITHER_RAND_G_SEED 0x1bf4 5177 #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 5178 #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 5179 #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 5180 #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 5181 #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 5182 #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 5183 #define mmFMT_DITHER_RAND_B_SEED 0x1bf5 5184 #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 5185 #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 5186 #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 5187 #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 5188 #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 5189 #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 5190 #define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 5191 #define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 5192 #define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 5193 #define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 5194 #define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 5195 #define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 5196 #define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 5197 #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 5198 #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 5199 #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 5200 #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 5201 #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 5202 #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 5203 #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 5204 #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 5205 #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 5206 #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 5207 #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 5208 #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 5209 #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 5210 #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 5211 #define mmFMT_CLAMP_CNTL 0x1bf9 5212 #define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 5213 #define mmFMT1_FMT_CLAMP_CNTL 0x1df9 5214 #define mmFMT2_FMT_CLAMP_CNTL 0x1ff9 5215 #define mmFMT3_FMT_CLAMP_CNTL 0x41f9 5216 #define mmFMT4_FMT_CLAMP_CNTL 0x43f9 5217 #define mmFMT5_FMT_CLAMP_CNTL 0x45f9 5218 #define mmFMT_CRC_CNTL 0x1bfa 5219 #define mmFMT0_FMT_CRC_CNTL 0x1bfa 5220 #define mmFMT1_FMT_CRC_CNTL 0x1dfa 5221 #define mmFMT2_FMT_CRC_CNTL 0x1ffa 5222 #define mmFMT3_FMT_CRC_CNTL 0x41fa 5223 #define mmFMT4_FMT_CRC_CNTL 0x43fa 5224 #define mmFMT5_FMT_CRC_CNTL 0x45fa 5225 #define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb 5226 #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb 5227 #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb 5228 #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb 5229 #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb 5230 #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb 5231 #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb 5232 #define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc 5233 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc 5234 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc 5235 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc 5236 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc 5237 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc 5238 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc 5239 #define mmFMT_CRC_SIG_RED_GREEN 0x1bfd 5240 #define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd 5241 #define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd 5242 #define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd 5243 #define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd 5244 #define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd 5245 #define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd 5246 #define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe 5247 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe 5248 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe 5249 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe 5250 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe 5251 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe 5252 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe 5253 #define mmFMT_DEBUG_CNTL 0x1bff 5254 #define mmFMT0_FMT_DEBUG_CNTL 0x1bff 5255 #define mmFMT1_FMT_DEBUG_CNTL 0x1dff 5256 #define mmFMT2_FMT_DEBUG_CNTL 0x1fff 5257 #define mmFMT3_FMT_DEBUG_CNTL 0x41ff 5258 #define mmFMT4_FMT_DEBUG_CNTL 0x43ff 5259 #define mmFMT5_FMT_DEBUG_CNTL 0x45ff 5260 #define mmFMT_TEST_DEBUG_INDEX 0x1beb 5261 #define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb 5262 #define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb 5263 #define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb 5264 #define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb 5265 #define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb 5266 #define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb 5267 #define mmFMT_TEST_DEBUG_DATA 0x1bec 5268 #define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec 5269 #define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec 5270 #define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec 5271 #define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec 5272 #define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec 5273 #define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec 5274 #define ixFMT_DEBUG0 0x1 5275 #define ixFMT_DEBUG1 0x2 5276 #define ixFMT_DEBUG2 0x3 5277 #define ixFMT_DEBUG_ID 0x0 5278 #define mmLB_DATA_FORMAT 0x1ac0 5279 #define mmLB0_LB_DATA_FORMAT 0x1ac0 5280 #define mmLB1_LB_DATA_FORMAT 0x1cc0 5281 #define mmLB2_LB_DATA_FORMAT 0x1ec0 5282 #define mmLB3_LB_DATA_FORMAT 0x40c0 5283 #define mmLB4_LB_DATA_FORMAT 0x42c0 5284 #define mmLB5_LB_DATA_FORMAT 0x44c0 5285 #define mmLB_MEMORY_CTRL 0x1ac1 5286 #define mmLB0_LB_MEMORY_CTRL 0x1ac1 5287 #define mmLB1_LB_MEMORY_CTRL 0x1cc1 5288 #define mmLB2_LB_MEMORY_CTRL 0x1ec1 5289 #define mmLB3_LB_MEMORY_CTRL 0x40c1 5290 #define mmLB4_LB_MEMORY_CTRL 0x42c1 5291 #define mmLB5_LB_MEMORY_CTRL 0x44c1 5292 #define mmLB_MEMORY_SIZE_STATUS 0x1ac2 5293 #define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 5294 #define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 5295 #define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 5296 #define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 5297 #define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 5298 #define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 5299 #define mmLB_DESKTOP_HEIGHT 0x1ac3 5300 #define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 5301 #define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 5302 #define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 5303 #define mmLB3_LB_DESKTOP_HEIGHT 0x40c3 5304 #define mmLB4_LB_DESKTOP_HEIGHT 0x42c3 5305 #define mmLB5_LB_DESKTOP_HEIGHT 0x44c3 5306 #define mmLB_VLINE_START_END 0x1ac4 5307 #define mmLB0_LB_VLINE_START_END 0x1ac4 5308 #define mmLB1_LB_VLINE_START_END 0x1cc4 5309 #define mmLB2_LB_VLINE_START_END 0x1ec4 5310 #define mmLB3_LB_VLINE_START_END 0x40c4 5311 #define mmLB4_LB_VLINE_START_END 0x42c4 5312 #define mmLB5_LB_VLINE_START_END 0x44c4 5313 #define mmLB_VLINE2_START_END 0x1ac5 5314 #define mmLB0_LB_VLINE2_START_END 0x1ac5 5315 #define mmLB1_LB_VLINE2_START_END 0x1cc5 5316 #define mmLB2_LB_VLINE2_START_END 0x1ec5 5317 #define mmLB3_LB_VLINE2_START_END 0x40c5 5318 #define mmLB4_LB_VLINE2_START_END 0x42c5 5319 #define mmLB5_LB_VLINE2_START_END 0x44c5 5320 #define mmLB_V_COUNTER 0x1ac6 5321 #define mmLB0_LB_V_COUNTER 0x1ac6 5322 #define mmLB1_LB_V_COUNTER 0x1cc6 5323 #define mmLB2_LB_V_COUNTER 0x1ec6 5324 #define mmLB3_LB_V_COUNTER 0x40c6 5325 #define mmLB4_LB_V_COUNTER 0x42c6 5326 #define mmLB5_LB_V_COUNTER 0x44c6 5327 #define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 5328 #define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 5329 #define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 5330 #define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 5331 #define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 5332 #define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 5333 #define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 5334 #define mmLB_INTERRUPT_MASK 0x1ac8 5335 #define mmLB0_LB_INTERRUPT_MASK 0x1ac8 5336 #define mmLB1_LB_INTERRUPT_MASK 0x1cc8 5337 #define mmLB2_LB_INTERRUPT_MASK 0x1ec8 5338 #define mmLB3_LB_INTERRUPT_MASK 0x40c8 5339 #define mmLB4_LB_INTERRUPT_MASK 0x42c8 5340 #define mmLB5_LB_INTERRUPT_MASK 0x44c8 5341 #define mmLB_VLINE_STATUS 0x1ac9 5342 #define mmLB0_LB_VLINE_STATUS 0x1ac9 5343 #define mmLB1_LB_VLINE_STATUS 0x1cc9 5344 #define mmLB2_LB_VLINE_STATUS 0x1ec9 5345 #define mmLB3_LB_VLINE_STATUS 0x40c9 5346 #define mmLB4_LB_VLINE_STATUS 0x42c9 5347 #define mmLB5_LB_VLINE_STATUS 0x44c9 5348 #define mmLB_VLINE2_STATUS 0x1aca 5349 #define mmLB0_LB_VLINE2_STATUS 0x1aca 5350 #define mmLB1_LB_VLINE2_STATUS 0x1cca 5351 #define mmLB2_LB_VLINE2_STATUS 0x1eca 5352 #define mmLB3_LB_VLINE2_STATUS 0x40ca 5353 #define mmLB4_LB_VLINE2_STATUS 0x42ca 5354 #define mmLB5_LB_VLINE2_STATUS 0x44ca 5355 #define mmLB_VBLANK_STATUS 0x1acb 5356 #define mmLB0_LB_VBLANK_STATUS 0x1acb 5357 #define mmLB1_LB_VBLANK_STATUS 0x1ccb 5358 #define mmLB2_LB_VBLANK_STATUS 0x1ecb 5359 #define mmLB3_LB_VBLANK_STATUS 0x40cb 5360 #define mmLB4_LB_VBLANK_STATUS 0x42cb 5361 #define mmLB5_LB_VBLANK_STATUS 0x44cb 5362 #define mmLB_SYNC_RESET_SEL 0x1acc 5363 #define mmLB0_LB_SYNC_RESET_SEL 0x1acc 5364 #define mmLB1_LB_SYNC_RESET_SEL 0x1ccc 5365 #define mmLB2_LB_SYNC_RESET_SEL 0x1ecc 5366 #define mmLB3_LB_SYNC_RESET_SEL 0x40cc 5367 #define mmLB4_LB_SYNC_RESET_SEL 0x42cc 5368 #define mmLB5_LB_SYNC_RESET_SEL 0x44cc 5369 #define mmLB_BLACK_KEYER_R_CR 0x1acd 5370 #define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd 5371 #define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd 5372 #define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd 5373 #define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd 5374 #define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd 5375 #define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd 5376 #define mmLB_BLACK_KEYER_G_Y 0x1ace 5377 #define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace 5378 #define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce 5379 #define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece 5380 #define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce 5381 #define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce 5382 #define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce 5383 #define mmLB_BLACK_KEYER_B_CB 0x1acf 5384 #define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf 5385 #define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf 5386 #define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf 5387 #define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf 5388 #define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf 5389 #define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf 5390 #define mmLB_KEYER_COLOR_CTRL 0x1ad0 5391 #define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 5392 #define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 5393 #define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 5394 #define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 5395 #define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 5396 #define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 5397 #define mmLB_KEYER_COLOR_R_CR 0x1ad1 5398 #define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 5399 #define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 5400 #define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 5401 #define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 5402 #define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 5403 #define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 5404 #define mmLB_KEYER_COLOR_G_Y 0x1ad2 5405 #define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 5406 #define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 5407 #define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 5408 #define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 5409 #define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 5410 #define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 5411 #define mmLB_KEYER_COLOR_B_CB 0x1ad3 5412 #define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 5413 #define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 5414 #define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 5415 #define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 5416 #define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 5417 #define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 5418 #define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 5419 #define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 5420 #define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 5421 #define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 5422 #define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 5423 #define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 5424 #define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 5425 #define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 5426 #define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 5427 #define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 5428 #define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 5429 #define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 5430 #define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 5431 #define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 5432 #define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 5433 #define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 5434 #define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 5435 #define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 5436 #define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 5437 #define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 5438 #define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 5439 #define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 5440 #define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 5441 #define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 5442 #define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 5443 #define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 5444 #define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 5445 #define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 5446 #define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 5447 #define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 5448 #define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 5449 #define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 5450 #define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 5451 #define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 5452 #define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 5453 #define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 5454 #define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 5455 #define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 5456 #define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 5457 #define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 5458 #define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 5459 #define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 5460 #define mmLB_BUFFER_STATUS 0x1ada 5461 #define mmLB0_LB_BUFFER_STATUS 0x1ada 5462 #define mmLB1_LB_BUFFER_STATUS 0x1cda 5463 #define mmLB2_LB_BUFFER_STATUS 0x1eda 5464 #define mmLB3_LB_BUFFER_STATUS 0x40da 5465 #define mmLB4_LB_BUFFER_STATUS 0x42da 5466 #define mmLB5_LB_BUFFER_STATUS 0x44da 5467 #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc 5468 #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc 5469 #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc 5470 #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc 5471 #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc 5472 #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc 5473 #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc 5474 #define mmMVP_AFR_FLIP_MODE 0x1ae0 5475 #define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 5476 #define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 5477 #define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 5478 #define mmLB3_MVP_AFR_FLIP_MODE 0x40e0 5479 #define mmLB4_MVP_AFR_FLIP_MODE 0x42e0 5480 #define mmLB5_MVP_AFR_FLIP_MODE 0x44e0 5481 #define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 5482 #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 5483 #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 5484 #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 5485 #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 5486 #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 5487 #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 5488 #define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 5489 #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 5490 #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 5491 #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 5492 #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 5493 #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 5494 #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 5495 #define mmDC_MVP_LB_CONTROL 0x1ae3 5496 #define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 5497 #define mmLB1_DC_MVP_LB_CONTROL 0x1ce3 5498 #define mmLB2_DC_MVP_LB_CONTROL 0x1ee3 5499 #define mmLB3_DC_MVP_LB_CONTROL 0x40e3 5500 #define mmLB4_DC_MVP_LB_CONTROL 0x42e3 5501 #define mmLB5_DC_MVP_LB_CONTROL 0x44e3 5502 #define mmLB_DEBUG 0x1ae4 5503 #define mmLB0_LB_DEBUG 0x1ae4 5504 #define mmLB1_LB_DEBUG 0x1ce4 5505 #define mmLB2_LB_DEBUG 0x1ee4 5506 #define mmLB3_LB_DEBUG 0x40e4 5507 #define mmLB4_LB_DEBUG 0x42e4 5508 #define mmLB5_LB_DEBUG 0x44e4 5509 #define mmLB_DEBUG2 0x1ae5 5510 #define mmLB0_LB_DEBUG2 0x1ae5 5511 #define mmLB1_LB_DEBUG2 0x1ce5 5512 #define mmLB2_LB_DEBUG2 0x1ee5 5513 #define mmLB3_LB_DEBUG2 0x40e5 5514 #define mmLB4_LB_DEBUG2 0x42e5 5515 #define mmLB5_LB_DEBUG2 0x44e5 5516 #define mmLB_DEBUG3 0x1ae6 5517 #define mmLB0_LB_DEBUG3 0x1ae6 5518 #define mmLB1_LB_DEBUG3 0x1ce6 5519 #define mmLB2_LB_DEBUG3 0x1ee6 5520 #define mmLB3_LB_DEBUG3 0x40e6 5521 #define mmLB4_LB_DEBUG3 0x42e6 5522 #define mmLB5_LB_DEBUG3 0x44e6 5523 #define mmLB_TEST_DEBUG_INDEX 0x1afe 5524 #define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe 5525 #define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe 5526 #define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe 5527 #define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe 5528 #define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe 5529 #define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe 5530 #define mmLB_TEST_DEBUG_DATA 0x1aff 5531 #define mmLB0_LB_TEST_DEBUG_DATA 0x1aff 5532 #define mmLB1_LB_TEST_DEBUG_DATA 0x1cff 5533 #define mmLB2_LB_TEST_DEBUG_DATA 0x1eff 5534 #define mmLB3_LB_TEST_DEBUG_DATA 0x40ff 5535 #define mmLB4_LB_TEST_DEBUG_DATA 0x42ff 5536 #define mmLB5_LB_TEST_DEBUG_DATA 0x44ff 5537 #define mmLBV_DATA_FORMAT 0x463c 5538 #define mmLBV_MEMORY_CTRL 0x463d 5539 #define mmLBV_MEMORY_SIZE_STATUS 0x463e 5540 #define mmLBV_DESKTOP_HEIGHT 0x463f 5541 #define mmLBV_VLINE_START_END 0x4640 5542 #define mmLBV_VLINE2_START_END 0x4641 5543 #define mmLBV_V_COUNTER 0x4642 5544 #define mmLBV_SNAPSHOT_V_COUNTER 0x4643 5545 #define mmLBV_V_COUNTER_CHROMA 0x4644 5546 #define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 5547 #define mmLBV_INTERRUPT_MASK 0x4646 5548 #define mmLBV_VLINE_STATUS 0x4647 5549 #define mmLBV_VLINE2_STATUS 0x4648 5550 #define mmLBV_VBLANK_STATUS 0x4649 5551 #define mmLBV_SYNC_RESET_SEL 0x464a 5552 #define mmLBV_BLACK_KEYER_R_CR 0x464b 5553 #define mmLBV_BLACK_KEYER_G_Y 0x464c 5554 #define mmLBV_BLACK_KEYER_B_CB 0x464d 5555 #define mmLBV_KEYER_COLOR_CTRL 0x464e 5556 #define mmLBV_KEYER_COLOR_R_CR 0x464f 5557 #define mmLBV_KEYER_COLOR_G_Y 0x4650 5558 #define mmLBV_KEYER_COLOR_B_CB 0x4651 5559 #define mmLBV_KEYER_COLOR_REP_R_CR 0x4652 5560 #define mmLBV_KEYER_COLOR_REP_G_Y 0x4653 5561 #define mmLBV_KEYER_COLOR_REP_B_CB 0x4654 5562 #define mmLBV_BUFFER_LEVEL_STATUS 0x4655 5563 #define mmLBV_BUFFER_URGENCY_CTRL 0x4656 5564 #define mmLBV_BUFFER_URGENCY_STATUS 0x4657 5565 #define mmLBV_BUFFER_STATUS 0x4658 5566 #define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 5567 #define mmLBV_DEBUG 0x465a 5568 #define mmLBV_DEBUG2 0x465b 5569 #define mmLBV_DEBUG3 0x465c 5570 #define mmLBV_TEST_DEBUG_INDEX 0x4666 5571 #define mmLBV_TEST_DEBUG_DATA 0x4667 5572 #define mmMVP_CONTROL1 0x2ac 5573 #define mmMVP_CONTROL2 0x2ad 5574 #define mmMVP_FIFO_CONTROL 0x2ae 5575 #define mmMVP_FIFO_STATUS 0x2af 5576 #define mmMVP_SLAVE_STATUS 0x2b0 5577 #define mmMVP_INBAND_CNTL_CAP 0x2b1 5578 #define mmMVP_BLACK_KEYER 0x2b2 5579 #define mmMVP_CRC_CNTL 0x2b3 5580 #define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 5581 #define mmMVP_CRC_RESULT_RED 0x2b5 5582 #define mmMVP_CONTROL3 0x2b6 5583 #define mmMVP_RECEIVE_CNT_CNTL1 0x2b7 5584 #define mmMVP_RECEIVE_CNT_CNTL2 0x2b8 5585 #define mmMVP_DEBUG 0x2bb 5586 #define mmMVP_TEST_DEBUG_INDEX 0x2b9 5587 #define mmMVP_TEST_DEBUG_DATA 0x2ba 5588 #define ixMVP_DEBUG_12 0xc 5589 #define ixMVP_DEBUG_13 0xd 5590 #define ixMVP_DEBUG_14 0xe 5591 #define ixMVP_DEBUG_15 0xf 5592 #define ixMVP_DEBUG_16 0x10 5593 #define ixMVP_DEBUG_17 0x11 5594 #define mmSCL_COEF_RAM_SELECT 0x1b40 5595 #define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 5596 #define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 5597 #define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 5598 #define mmSCL3_SCL_COEF_RAM_SELECT 0x4140 5599 #define mmSCL4_SCL_COEF_RAM_SELECT 0x4340 5600 #define mmSCL5_SCL_COEF_RAM_SELECT 0x4540 5601 #define mmSCL_COEF_RAM_TAP_DATA 0x1b41 5602 #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 5603 #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 5604 #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 5605 #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 5606 #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 5607 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 5608 #define mmSCL_MODE 0x1b42 5609 #define mmSCL0_SCL_MODE 0x1b42 5610 #define mmSCL1_SCL_MODE 0x1d42 5611 #define mmSCL2_SCL_MODE 0x1f42 5612 #define mmSCL3_SCL_MODE 0x4142 5613 #define mmSCL4_SCL_MODE 0x4342 5614 #define mmSCL5_SCL_MODE 0x4542 5615 #define mmSCL_TAP_CONTROL 0x1b43 5616 #define mmSCL0_SCL_TAP_CONTROL 0x1b43 5617 #define mmSCL1_SCL_TAP_CONTROL 0x1d43 5618 #define mmSCL2_SCL_TAP_CONTROL 0x1f43 5619 #define mmSCL3_SCL_TAP_CONTROL 0x4143 5620 #define mmSCL4_SCL_TAP_CONTROL 0x4343 5621 #define mmSCL5_SCL_TAP_CONTROL 0x4543 5622 #define mmSCL_CONTROL 0x1b44 5623 #define mmSCL0_SCL_CONTROL 0x1b44 5624 #define mmSCL1_SCL_CONTROL 0x1d44 5625 #define mmSCL2_SCL_CONTROL 0x1f44 5626 #define mmSCL3_SCL_CONTROL 0x4144 5627 #define mmSCL4_SCL_CONTROL 0x4344 5628 #define mmSCL5_SCL_CONTROL 0x4544 5629 #define mmSCL_BYPASS_CONTROL 0x1b45 5630 #define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 5631 #define mmSCL1_SCL_BYPASS_CONTROL 0x1d45 5632 #define mmSCL2_SCL_BYPASS_CONTROL 0x1f45 5633 #define mmSCL3_SCL_BYPASS_CONTROL 0x4145 5634 #define mmSCL4_SCL_BYPASS_CONTROL 0x4345 5635 #define mmSCL5_SCL_BYPASS_CONTROL 0x4545 5636 #define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 5637 #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 5638 #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 5639 #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 5640 #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 5641 #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 5642 #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 5643 #define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 5644 #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 5645 #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 5646 #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 5647 #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 5648 #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 5649 #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 5650 #define mmSCL_HORZ_FILTER_CONTROL 0x1b48 5651 #define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 5652 #define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 5653 #define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 5654 #define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 5655 #define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 5656 #define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 5657 #define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 5658 #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 5659 #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 5660 #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 5661 #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 5662 #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 5663 #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 5664 #define mmSCL_HORZ_FILTER_INIT 0x1b4a 5665 #define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a 5666 #define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a 5667 #define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a 5668 #define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a 5669 #define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a 5670 #define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a 5671 #define mmSCL_VERT_FILTER_CONTROL 0x1b4b 5672 #define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b 5673 #define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b 5674 #define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b 5675 #define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b 5676 #define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b 5677 #define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b 5678 #define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c 5679 #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c 5680 #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c 5681 #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c 5682 #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c 5683 #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c 5684 #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c 5685 #define mmSCL_VERT_FILTER_INIT 0x1b4d 5686 #define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d 5687 #define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d 5688 #define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d 5689 #define mmSCL3_SCL_VERT_FILTER_INIT 0x414d 5690 #define mmSCL4_SCL_VERT_FILTER_INIT 0x434d 5691 #define mmSCL5_SCL_VERT_FILTER_INIT 0x454d 5692 #define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e 5693 #define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e 5694 #define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e 5695 #define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e 5696 #define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e 5697 #define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e 5698 #define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e 5699 #define mmSCL_ROUND_OFFSET 0x1b4f 5700 #define mmSCL0_SCL_ROUND_OFFSET 0x1b4f 5701 #define mmSCL1_SCL_ROUND_OFFSET 0x1d4f 5702 #define mmSCL2_SCL_ROUND_OFFSET 0x1f4f 5703 #define mmSCL3_SCL_ROUND_OFFSET 0x414f 5704 #define mmSCL4_SCL_ROUND_OFFSET 0x434f 5705 #define mmSCL5_SCL_ROUND_OFFSET 0x454f 5706 #define mmSCL_UPDATE 0x1b51 5707 #define mmSCL0_SCL_UPDATE 0x1b51 5708 #define mmSCL1_SCL_UPDATE 0x1d51 5709 #define mmSCL2_SCL_UPDATE 0x1f51 5710 #define mmSCL3_SCL_UPDATE 0x4151 5711 #define mmSCL4_SCL_UPDATE 0x4351 5712 #define mmSCL5_SCL_UPDATE 0x4551 5713 #define mmSCL_F_SHARP_CONTROL 0x1b53 5714 #define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 5715 #define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 5716 #define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 5717 #define mmSCL3_SCL_F_SHARP_CONTROL 0x4153 5718 #define mmSCL4_SCL_F_SHARP_CONTROL 0x4353 5719 #define mmSCL5_SCL_F_SHARP_CONTROL 0x4553 5720 #define mmSCL_ALU_CONTROL 0x1b54 5721 #define mmSCL0_SCL_ALU_CONTROL 0x1b54 5722 #define mmSCL1_SCL_ALU_CONTROL 0x1d54 5723 #define mmSCL2_SCL_ALU_CONTROL 0x1f54 5724 #define mmSCL3_SCL_ALU_CONTROL 0x4154 5725 #define mmSCL4_SCL_ALU_CONTROL 0x4354 5726 #define mmSCL5_SCL_ALU_CONTROL 0x4554 5727 #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 5728 #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 5729 #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 5730 #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 5731 #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 5732 #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 5733 #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 5734 #define mmVIEWPORT_START_SECONDARY 0x1b5b 5735 #define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b 5736 #define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b 5737 #define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b 5738 #define mmSCL3_VIEWPORT_START_SECONDARY 0x415b 5739 #define mmSCL4_VIEWPORT_START_SECONDARY 0x435b 5740 #define mmSCL5_VIEWPORT_START_SECONDARY 0x455b 5741 #define mmVIEWPORT_START 0x1b5c 5742 #define mmSCL0_VIEWPORT_START 0x1b5c 5743 #define mmSCL1_VIEWPORT_START 0x1d5c 5744 #define mmSCL2_VIEWPORT_START 0x1f5c 5745 #define mmSCL3_VIEWPORT_START 0x415c 5746 #define mmSCL4_VIEWPORT_START 0x435c 5747 #define mmSCL5_VIEWPORT_START 0x455c 5748 #define mmVIEWPORT_SIZE 0x1b5d 5749 #define mmSCL0_VIEWPORT_SIZE 0x1b5d 5750 #define mmSCL1_VIEWPORT_SIZE 0x1d5d 5751 #define mmSCL2_VIEWPORT_SIZE 0x1f5d 5752 #define mmSCL3_VIEWPORT_SIZE 0x415d 5753 #define mmSCL4_VIEWPORT_SIZE 0x435d 5754 #define mmSCL5_VIEWPORT_SIZE 0x455d 5755 #define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e 5756 #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e 5757 #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e 5758 #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e 5759 #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e 5760 #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e 5761 #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e 5762 #define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f 5763 #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f 5764 #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f 5765 #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f 5766 #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f 5767 #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f 5768 #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f 5769 #define mmSCL_MODE_CHANGE_DET1 0x1b60 5770 #define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 5771 #define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 5772 #define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 5773 #define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 5774 #define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 5775 #define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 5776 #define mmSCL_MODE_CHANGE_DET2 0x1b61 5777 #define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 5778 #define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 5779 #define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 5780 #define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 5781 #define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 5782 #define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 5783 #define mmSCL_MODE_CHANGE_DET3 0x1b62 5784 #define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 5785 #define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 5786 #define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 5787 #define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 5788 #define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 5789 #define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 5790 #define mmSCL_MODE_CHANGE_MASK 0x1b63 5791 #define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 5792 #define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 5793 #define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 5794 #define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 5795 #define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 5796 #define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 5797 #define mmSCL_DEBUG2 0x1b69 5798 #define mmSCL0_SCL_DEBUG2 0x1b69 5799 #define mmSCL1_SCL_DEBUG2 0x1d69 5800 #define mmSCL2_SCL_DEBUG2 0x1f69 5801 #define mmSCL3_SCL_DEBUG2 0x4169 5802 #define mmSCL4_SCL_DEBUG2 0x4369 5803 #define mmSCL5_SCL_DEBUG2 0x4569 5804 #define mmSCL_DEBUG 0x1b6a 5805 #define mmSCL0_SCL_DEBUG 0x1b6a 5806 #define mmSCL1_SCL_DEBUG 0x1d6a 5807 #define mmSCL2_SCL_DEBUG 0x1f6a 5808 #define mmSCL3_SCL_DEBUG 0x416a 5809 #define mmSCL4_SCL_DEBUG 0x436a 5810 #define mmSCL5_SCL_DEBUG 0x456a 5811 #define mmSCL_TEST_DEBUG_INDEX 0x1b6b 5812 #define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b 5813 #define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b 5814 #define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b 5815 #define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b 5816 #define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b 5817 #define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b 5818 #define mmSCL_TEST_DEBUG_DATA 0x1b6c 5819 #define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c 5820 #define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c 5821 #define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c 5822 #define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c 5823 #define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c 5824 #define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c 5825 #define mmSCLV_COEF_RAM_SELECT 0x4670 5826 #define mmSCLV_COEF_RAM_TAP_DATA 0x4671 5827 #define mmSCLV_MODE 0x4672 5828 #define mmSCLV_TAP_CONTROL 0x4673 5829 #define mmSCLV_CONTROL 0x4674 5830 #define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 5831 #define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 5832 #define mmSCLV_HORZ_FILTER_CONTROL 0x4677 5833 #define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 5834 #define mmSCLV_HORZ_FILTER_INIT 0x4679 5835 #define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a 5836 #define mmSCLV_HORZ_FILTER_INIT_C 0x467b 5837 #define mmSCLV_VERT_FILTER_CONTROL 0x467c 5838 #define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d 5839 #define mmSCLV_VERT_FILTER_INIT 0x467e 5840 #define mmSCLV_VERT_FILTER_INIT_BOT 0x467f 5841 #define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 5842 #define mmSCLV_VERT_FILTER_INIT_C 0x4681 5843 #define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 5844 #define mmSCLV_ROUND_OFFSET 0x4683 5845 #define mmSCLV_UPDATE 0x4684 5846 #define mmSCLV_ALU_CONTROL 0x4685 5847 #define mmSCLV_VIEWPORT_START 0x4686 5848 #define mmSCLV_VIEWPORT_START_SECONDARY 0x4687 5849 #define mmSCLV_VIEWPORT_SIZE 0x4688 5850 #define mmSCLV_VIEWPORT_START_C 0x4689 5851 #define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a 5852 #define mmSCLV_VIEWPORT_SIZE_C 0x468b 5853 #define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c 5854 #define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d 5855 #define mmSCLV_MODE_CHANGE_DET1 0x468e 5856 #define mmSCLV_MODE_CHANGE_DET2 0x468f 5857 #define mmSCLV_MODE_CHANGE_DET3 0x4690 5858 #define mmSCLV_MODE_CHANGE_MASK 0x4691 5859 #define mmSCLV_HORZ_FILTER_INIT_BOT 0x4692 5860 #define mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693 5861 #define mmSCLV_DEBUG2 0x4694 5862 #define mmSCLV_DEBUG 0x4695 5863 #define mmSCLV_TEST_DEBUG_INDEX 0x4696 5864 #define mmSCLV_TEST_DEBUG_DATA 0x4697 5865 #define mmCOL_MAN_UPDATE 0x46a4 5866 #define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 5867 #define mmINPUT_CSC_C11_C12_A 0x46a6 5868 #define mmINPUT_CSC_C13_C14_A 0x46a7 5869 #define mmINPUT_CSC_C21_C22_A 0x46a8 5870 #define mmINPUT_CSC_C23_C24_A 0x46a9 5871 #define mmINPUT_CSC_C31_C32_A 0x46aa 5872 #define mmINPUT_CSC_C33_C34_A 0x46ab 5873 #define mmINPUT_CSC_C11_C12_B 0x46ac 5874 #define mmINPUT_CSC_C13_C14_B 0x46ad 5875 #define mmINPUT_CSC_C21_C22_B 0x46ae 5876 #define mmINPUT_CSC_C23_C24_B 0x46af 5877 #define mmINPUT_CSC_C31_C32_B 0x46b0 5878 #define mmINPUT_CSC_C33_C34_B 0x46b1 5879 #define mmPRESCALE_CONTROL 0x46b2 5880 #define mmPRESCALE_VALUES_R 0x46b3 5881 #define mmPRESCALE_VALUES_G 0x46b4 5882 #define mmPRESCALE_VALUES_B 0x46b5 5883 #define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 5884 #define mmOUTPUT_CSC_C11_C12_A 0x46b7 5885 #define mmOUTPUT_CSC_C13_C14_A 0x46b8 5886 #define mmOUTPUT_CSC_C21_C22_A 0x46b9 5887 #define mmOUTPUT_CSC_C23_C24_A 0x46ba 5888 #define mmOUTPUT_CSC_C31_C32_A 0x46bb 5889 #define mmOUTPUT_CSC_C33_C34_A 0x46bc 5890 #define mmOUTPUT_CSC_C11_C12_B 0x46bd 5891 #define mmOUTPUT_CSC_C13_C14_B 0x46be 5892 #define mmOUTPUT_CSC_C21_C22_B 0x46bf 5893 #define mmOUTPUT_CSC_C23_C24_B 0x46c0 5894 #define mmOUTPUT_CSC_C31_C32_B 0x46c1 5895 #define mmOUTPUT_CSC_C33_C34_B 0x46c2 5896 #define mmDENORM_CLAMP_CONTROL 0x46c3 5897 #define mmDENORM_CLAMP_RANGE_R_CR 0x46c4 5898 #define mmDENORM_CLAMP_RANGE_G_Y 0x46c5 5899 #define mmDENORM_CLAMP_RANGE_B_CB 0x46c6 5900 #define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 5901 #define mmGAMMA_CORR_CONTROL 0x46c8 5902 #define mmGAMMA_CORR_LUT_INDEX 0x46c9 5903 #define mmGAMMA_CORR_LUT_DATA 0x46ca 5904 #define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb 5905 #define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc 5906 #define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd 5907 #define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce 5908 #define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf 5909 #define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 5910 #define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 5911 #define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 5912 #define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 5913 #define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 5914 #define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 5915 #define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 5916 #define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 5917 #define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 5918 #define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 5919 #define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da 5920 #define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db 5921 #define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc 5922 #define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd 5923 #define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de 5924 #define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df 5925 #define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 5926 #define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 5927 #define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 5928 #define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 5929 #define mmPACK_FIFO_ERROR 0x46e4 5930 #define mmOUTPUT_FIFO_ERROR 0x46e5 5931 #define mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6 5932 #define mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7 5933 #define mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 5934 #define mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9 5935 #define mmINPUT_GAMMA_LUT_30_COLOR 0x46ea 5936 #define mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb 5937 #define mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec 5938 #define mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed 5939 #define mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee 5940 #define mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef 5941 #define mmCOL_MAN_DEBUG_CONTROL 0x46f0 5942 #define mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1 5943 #define mmCOL_MAN_TEST_DEBUG_DATA 0x46f3 5944 #define mmUNP_GRPH_ENABLE 0x4600 5945 #define mmUNP_GRPH_CONTROL 0x4601 5946 #define mmUNP_GRPH_CONTROL_C 0x4602 5947 #define mmUNP_GRPH_CONTROL_EXP 0x4603 5948 #define mmUNP_GRPH_SWAP_CNTL 0x4605 5949 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 5950 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 5951 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 5952 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 5953 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a 5954 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b 5955 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c 5956 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d 5957 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e 5958 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f 5959 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 5960 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 5961 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 5962 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 5963 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 5964 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 5965 #define mmUNP_GRPH_PITCH_L 0x4616 5966 #define mmUNP_GRPH_PITCH_C 0x4617 5967 #define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 5968 #define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 5969 #define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a 5970 #define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b 5971 #define mmUNP_GRPH_X_START_L 0x461c 5972 #define mmUNP_GRPH_X_START_C 0x461d 5973 #define mmUNP_GRPH_Y_START_L 0x461e 5974 #define mmUNP_GRPH_Y_START_C 0x461f 5975 #define mmUNP_GRPH_X_END_L 0x4620 5976 #define mmUNP_GRPH_X_END_C 0x4621 5977 #define mmUNP_GRPH_Y_END_L 0x4622 5978 #define mmUNP_GRPH_Y_END_C 0x4623 5979 #define mmUNP_GRPH_UPDATE 0x4624 5980 #define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a 5981 #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 5982 #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 5983 #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 5984 #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 5985 #define mmUNP_DVMM_PTE_CONTROL 0x4629 5986 #define mmUNP_DVMM_PTE_CONTROL_C 0x4604 5987 #define mmUNP_DVMM_PTE_ARB_CONTROL 0x462a 5988 #define mmUNP_DVMM_PTE_ARB_CONTROL_C 0x462d 5989 #define mmUNP_GRPH_INTERRUPT_STATUS 0x462b 5990 #define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c 5991 #define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e 5992 #define mmUNP_FLIP_CONTROL 0x462f 5993 #define mmUNP_CRC_CONTROL 0x4630 5994 #define mmUNP_CRC_MASK 0x4631 5995 #define mmUNP_CRC_CURRENT 0x4632 5996 #define mmUNP_CRC_LAST 0x4633 5997 #define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 5998 #define mmUNP_HW_ROTATION 0x4635 5999 #define mmUNP_DEBUG 0x4636 6000 #define mmUNP_DEBUG2 0x4637 6001 #define mmUNP_DVMM_DEBUG 0x463b 6002 #define mmUNP_TEST_DEBUG_INDEX 0x4638 6003 #define mmUNP_TEST_DEBUG_DATA 0x4639 6004 #define mmGENMO_WT 0xf0 6005 #define mmGENMO_RD 0xf3 6006 #define mmGENENB 0xf0 6007 #define mmGENFC_WT 0xee 6008 #define mmVGA0_GENFC_WT 0xee 6009 #define mmVGA1_GENFC_WT 0xf6 6010 #define mmGENFC_RD 0xf2 6011 #define mmGENS0 0xf0 6012 #define mmGENS1 0xee 6013 #define mmVGA0_GENS1 0xee 6014 #define mmVGA1_GENS1 0xf6 6015 #define mmDAC_DATA 0xf2 6016 #define mmDAC_MASK 0xf1 6017 #define mmDAC_R_INDEX 0xf1 6018 #define mmDAC_W_INDEX 0xf2 6019 #define mmSEQ8_IDX 0xf1 6020 #define mmSEQ8_DATA 0xf1 6021 #define ixSEQ00 0x0 6022 #define ixSEQ01 0x1 6023 #define ixSEQ02 0x2 6024 #define ixSEQ03 0x3 6025 #define ixSEQ04 0x4 6026 #define mmCRTC8_IDX 0xed 6027 #define mmVGA0_CRTC8_IDX 0xed 6028 #define mmVGA1_CRTC8_IDX 0xf5 6029 #define mmCRTC8_DATA 0xed 6030 #define mmVGA0_CRTC8_DATA 0xed 6031 #define mmVGA1_CRTC8_DATA 0xf5 6032 #define ixCRT00 0x0 6033 #define ixCRT01 0x1 6034 #define ixCRT02 0x2 6035 #define ixCRT03 0x3 6036 #define ixCRT04 0x4 6037 #define ixCRT05 0x5 6038 #define ixCRT06 0x6 6039 #define ixCRT07 0x7 6040 #define ixCRT08 0x8 6041 #define ixCRT09 0x9 6042 #define ixCRT0A 0xa 6043 #define ixCRT0B 0xb 6044 #define ixCRT0C 0xc 6045 #define ixCRT0D 0xd 6046 #define ixCRT0E 0xe 6047 #define ixCRT0F 0xf 6048 #define ixCRT10 0x10 6049 #define ixCRT11 0x11 6050 #define ixCRT12 0x12 6051 #define ixCRT13 0x13 6052 #define ixCRT14 0x14 6053 #define ixCRT15 0x15 6054 #define ixCRT16 0x16 6055 #define ixCRT17 0x17 6056 #define ixCRT18 0x18 6057 #define ixCRT1E 0x1e 6058 #define ixCRT1F 0x1f 6059 #define ixCRT22 0x22 6060 #define mmGRPH8_IDX 0xf3 6061 #define mmGRPH8_DATA 0xf3 6062 #define ixGRA00 0x0 6063 #define ixGRA01 0x1 6064 #define ixGRA02 0x2 6065 #define ixGRA03 0x3 6066 #define ixGRA04 0x4 6067 #define ixGRA05 0x5 6068 #define ixGRA06 0x6 6069 #define ixGRA07 0x7 6070 #define ixGRA08 0x8 6071 #define mmATTRX 0xf0 6072 #define mmATTRDW 0xf0 6073 #define mmATTRDR 0xf0 6074 #define ixATTR00 0x0 6075 #define ixATTR01 0x1 6076 #define ixATTR02 0x2 6077 #define ixATTR03 0x3 6078 #define ixATTR04 0x4 6079 #define ixATTR05 0x5 6080 #define ixATTR06 0x6 6081 #define ixATTR07 0x7 6082 #define ixATTR08 0x8 6083 #define ixATTR09 0x9 6084 #define ixATTR0A 0xa 6085 #define ixATTR0B 0xb 6086 #define ixATTR0C 0xc 6087 #define ixATTR0D 0xd 6088 #define ixATTR0E 0xe 6089 #define ixATTR0F 0xf 6090 #define ixATTR10 0x10 6091 #define ixATTR11 0x11 6092 #define ixATTR12 0x12 6093 #define ixATTR13 0x13 6094 #define ixATTR14 0x14 6095 #define mmVGA_RENDER_CONTROL 0xc0 6096 #define mmVGA_SOURCE_SELECT 0xfc 6097 #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 6098 #define mmVGA_MODE_CONTROL 0xc2 6099 #define mmVGA_SURFACE_PITCH_SELECT 0xc3 6100 #define mmVGA_MEMORY_BASE_ADDRESS 0xc4 6101 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 6102 #define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 6103 #define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 6104 #define mmVGA_HDP_CONTROL 0xca 6105 #define mmVGA_CACHE_CONTROL 0xcb 6106 #define mmD1VGA_CONTROL 0xcc 6107 #define mmD2VGA_CONTROL 0xce 6108 #define mmD3VGA_CONTROL 0xf8 6109 #define mmD4VGA_CONTROL 0xf9 6110 #define mmD5VGA_CONTROL 0xfa 6111 #define mmD6VGA_CONTROL 0xfb 6112 #define mmVGA_HW_DEBUG 0xcf 6113 #define mmVGA_STATUS 0xd0 6114 #define mmVGA_INTERRUPT_CONTROL 0xd1 6115 #define mmVGA_STATUS_CLEAR 0xd2 6116 #define mmVGA_INTERRUPT_STATUS 0xd3 6117 #define mmVGA_MAIN_CONTROL 0xd4 6118 #define mmVGA_TEST_CONTROL 0xd5 6119 #define mmVGA_DEBUG_READBACK_INDEX 0xd6 6120 #define mmVGA_DEBUG_READBACK_DATA 0xd7 6121 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 6122 #define mmVGA_MEM_READ_PAGE_ADDR 0x13 6123 #define mmVGA_TEST_DEBUG_INDEX 0xc5 6124 #define mmVGA_TEST_DEBUG_DATA 0xc7 6125 #define ixVGADCC_DBG_DCCIF_C 0x7e 6126 #define mmBPHYC_DAC_MACRO_CNTL 0x48b9 6127 #define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba 6128 #define mmPLL_REF_DIV 0x1700 6129 #define mmBPHYC_PLL0_PLL_REF_DIV 0x1700 6130 #define mmBPHYC_PLL1_PLL_REF_DIV 0x172a 6131 #define mmBPHYC_PLL2_PLL_REF_DIV 0x1754 6132 #define mmPLL_FB_DIV 0x1701 6133 #define mmBPHYC_PLL0_PLL_FB_DIV 0x1701 6134 #define mmBPHYC_PLL1_PLL_FB_DIV 0x172b 6135 #define mmBPHYC_PLL2_PLL_FB_DIV 0x1755 6136 #define mmPLL_POST_DIV 0x1702 6137 #define mmBPHYC_PLL0_PLL_POST_DIV 0x1702 6138 #define mmBPHYC_PLL1_PLL_POST_DIV 0x172c 6139 #define mmBPHYC_PLL2_PLL_POST_DIV 0x1756 6140 #define mmPLL_SS_AMOUNT_DSFRAC 0x1703 6141 #define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 6142 #define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d 6143 #define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 6144 #define mmPLL_SS_CNTL 0x1704 6145 #define mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 6146 #define mmBPHYC_PLL1_PLL_SS_CNTL 0x172e 6147 #define mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 6148 #define mmPLL_DS_CNTL 0x1705 6149 #define mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 6150 #define mmBPHYC_PLL1_PLL_DS_CNTL 0x172f 6151 #define mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 6152 #define mmPLL_IDCLK_CNTL 0x1706 6153 #define mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 6154 #define mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 6155 #define mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a 6156 #define mmPLL_CNTL 0x1707 6157 #define mmBPHYC_PLL0_PLL_CNTL 0x1707 6158 #define mmBPHYC_PLL1_PLL_CNTL 0x1731 6159 #define mmBPHYC_PLL2_PLL_CNTL 0x175b 6160 #define mmPLL_ANALOG 0x1708 6161 #define mmBPHYC_PLL0_PLL_ANALOG 0x1708 6162 #define mmBPHYC_PLL1_PLL_ANALOG 0x1732 6163 #define mmBPHYC_PLL2_PLL_ANALOG 0x175c 6164 #define mmPLL_VREG_CNTL 0x1709 6165 #define mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 6166 #define mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 6167 #define mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d 6168 #define mmPLL_UNLOCK_DETECT_CNTL 0x170a 6169 #define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a 6170 #define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 6171 #define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e 6172 #define mmPLL_DEBUG_CNTL 0x170b 6173 #define mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b 6174 #define mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 6175 #define mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f 6176 #define mmPLL_UPDATE_LOCK 0x170c 6177 #define mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c 6178 #define mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 6179 #define mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 6180 #define mmPLL_UPDATE_CNTL 0x170d 6181 #define mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d 6182 #define mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 6183 #define mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 6184 #define mmPLL_XOR_LOCK 0x1710 6185 #define mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 6186 #define mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a 6187 #define mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 6188 #define mmPLL_ANALOG_CNTL 0x1711 6189 #define mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 6190 #define mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b 6191 #define mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 6192 #define mmVGA25_PPLL_REF_DIV 0x1712 6193 #define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 6194 #define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c 6195 #define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 6196 #define mmVGA28_PPLL_REF_DIV 0x1713 6197 #define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 6198 #define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d 6199 #define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 6200 #define mmVGA41_PPLL_REF_DIV 0x1714 6201 #define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 6202 #define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e 6203 #define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 6204 #define mmVGA25_PPLL_FB_DIV 0x1715 6205 #define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 6206 #define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f 6207 #define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 6208 #define mmVGA28_PPLL_FB_DIV 0x1716 6209 #define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 6210 #define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 6211 #define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a 6212 #define mmVGA41_PPLL_FB_DIV 0x1717 6213 #define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 6214 #define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 6215 #define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b 6216 #define mmVGA25_PPLL_POST_DIV 0x1718 6217 #define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 6218 #define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 6219 #define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c 6220 #define mmVGA28_PPLL_POST_DIV 0x1719 6221 #define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 6222 #define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 6223 #define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d 6224 #define mmVGA41_PPLL_POST_DIV 0x171a 6225 #define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a 6226 #define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 6227 #define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e 6228 #define mmVGA25_PPLL_ANALOG 0x171b 6229 #define mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b 6230 #define mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 6231 #define mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f 6232 #define mmVGA28_PPLL_ANALOG 0x171c 6233 #define mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c 6234 #define mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 6235 #define mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 6236 #define mmVGA41_PPLL_ANALOG 0x171d 6237 #define mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d 6238 #define mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 6239 #define mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 6240 #define mmDISPPLL_BG_CNTL 0x171e 6241 #define mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e 6242 #define mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 6243 #define mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 6244 #define mmPPLL_DIV_UPDATE_DEBUG 0x171f 6245 #define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f 6246 #define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 6247 #define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 6248 #define mmPPLL_STATUS_DEBUG 0x1720 6249 #define mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 6250 #define mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a 6251 #define mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 6252 #define mmPPLL_DEBUG_MUX_CNTL 0x1721 6253 #define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 6254 #define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b 6255 #define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 6256 #define mmPPLL_SPARE0 0x1722 6257 #define mmBPHYC_PLL0_PPLL_SPARE0 0x1722 6258 #define mmBPHYC_PLL1_PPLL_SPARE0 0x174c 6259 #define mmBPHYC_PLL2_PPLL_SPARE0 0x1776 6260 #define mmPPLL_SPARE1 0x1723 6261 #define mmBPHYC_PLL0_PPLL_SPARE1 0x1723 6262 #define mmBPHYC_PLL1_PPLL_SPARE1 0x174d 6263 #define mmBPHYC_PLL2_PPLL_SPARE1 0x1777 6264 #define mmUNIPHY_TX_CONTROL1 0x48c0 6265 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 6266 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 6267 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 6268 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 6269 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 6270 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 6271 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 6272 #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 0x49c0 6273 #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 0x49e0 6274 #define mmUNIPHY_TX_CONTROL2 0x48c1 6275 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 6276 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 6277 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 6278 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 6279 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 6280 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 6281 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 6282 #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 0x49c1 6283 #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 0x49e1 6284 #define mmUNIPHY_TX_CONTROL3 0x48c2 6285 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 6286 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 6287 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 6288 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 6289 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 6290 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 6291 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 6292 #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 0x49c2 6293 #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 0x49e2 6294 #define mmUNIPHY_TX_CONTROL4 0x48c3 6295 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 6296 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 6297 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 6298 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 6299 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 6300 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 6301 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 6302 #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 0x49c3 6303 #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 0x49e3 6304 #define mmUNIPHY_POWER_CONTROL 0x48c4 6305 #define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 6306 #define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 6307 #define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 6308 #define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 6309 #define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 6310 #define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 6311 #define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 6312 #define mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL 0x49c4 6313 #define mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL 0x49e4 6314 #define mmUNIPHY_PLL_FBDIV 0x48c5 6315 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 6316 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 6317 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 6318 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 6319 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 6320 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 6321 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 6322 #define mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV 0x49c5 6323 #define mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV 0x49e5 6324 #define mmUNIPHY_PLL_CONTROL1 0x48c6 6325 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 6326 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 6327 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 6328 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 6329 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 6330 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 6331 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 6332 #define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 0x49c6 6333 #define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 0x49e6 6334 #define mmUNIPHY_PLL_CONTROL2 0x48c7 6335 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 6336 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 6337 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 6338 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 6339 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 6340 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 6341 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 6342 #define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 0x49c7 6343 #define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 0x49e7 6344 #define mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 6345 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 6346 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 6347 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 6348 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 6349 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 6350 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 6351 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 6352 #define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE 0x49c8 6353 #define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE 0x49e8 6354 #define mmUNIPHY_PLL_SS_CNTL 0x48c9 6355 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 6356 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 6357 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 6358 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 6359 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 6360 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 6361 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 6362 #define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL 0x49c9 6363 #define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL 0x49e9 6364 #define mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca 6365 #define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca 6366 #define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea 6367 #define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a 6368 #define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a 6369 #define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a 6370 #define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a 6371 #define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a 6372 #define mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION 0x49ca 6373 #define mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION 0x49ea 6374 #define mmUNIPHY_REG_TEST_OUTPUT 0x48cb 6375 #define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb 6376 #define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb 6377 #define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b 6378 #define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b 6379 #define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b 6380 #define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b 6381 #define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b 6382 #define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT 0x49cb 6383 #define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT 0x49eb 6384 #define mmUNIPHY_ANG_BIST_CNTL 0x48cc 6385 #define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc 6386 #define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec 6387 #define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c 6388 #define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c 6389 #define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c 6390 #define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c 6391 #define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c 6392 #define mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL 0x49cc 6393 #define mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL 0x49ec 6394 #define mmUNIPHY_REG_TEST_OUTPUT2 0x48cd 6395 #define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd 6396 #define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed 6397 #define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d 6398 #define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d 6399 #define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d 6400 #define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d 6401 #define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d 6402 #define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 0x49cd 6403 #define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 0x49ed 6404 #define mmUNIPHY_TMDP_REG0 0x48ce 6405 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce 6406 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee 6407 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e 6408 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e 6409 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e 6410 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e 6411 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e 6412 #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 0x49ce 6413 #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 0x49ee 6414 #define mmUNIPHY_TMDP_REG1 0x48cf 6415 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf 6416 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef 6417 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f 6418 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f 6419 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f 6420 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f 6421 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f 6422 #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 0x49cf 6423 #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 0x49ef 6424 #define mmUNIPHY_TMDP_REG2 0x48d0 6425 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 6426 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 6427 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 6428 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 6429 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 6430 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 6431 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 6432 #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 0x49d0 6433 #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 0x49f0 6434 #define mmUNIPHY_TMDP_REG3 0x48d1 6435 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 6436 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 6437 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 6438 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 6439 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 6440 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 6441 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 6442 #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 0x49d1 6443 #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 0x49f1 6444 #define mmUNIPHY_TMDP_REG4 0x48d2 6445 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 6446 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 6447 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 6448 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 6449 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 6450 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 6451 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 6452 #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 0x49d2 6453 #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 0x49f2 6454 #define mmUNIPHY_TMDP_REG5 0x48d3 6455 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 6456 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 6457 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 6458 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 6459 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 6460 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 6461 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 6462 #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 0x49d3 6463 #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 0x49f3 6464 #define mmUNIPHY_TMDP_REG6 0x48d4 6465 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 6466 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 6467 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 6468 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 6469 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 6470 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 6471 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 6472 #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 0x49d4 6473 #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 0x49f4 6474 #define mmUNIPHY_TPG_CONTROL 0x48d5 6475 #define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 6476 #define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 6477 #define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 6478 #define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 6479 #define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 6480 #define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 6481 #define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 6482 #define mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL 0x49d5 6483 #define mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL 0x49f5 6484 #define mmUNIPHY_TPG_SEED 0x48d6 6485 #define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 6486 #define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 6487 #define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 6488 #define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 6489 #define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 6490 #define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 6491 #define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 6492 #define mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED 0x49d6 6493 #define mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED 0x49f6 6494 #define mmUNIPHY_DEBUG 0x48d7 6495 #define mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 6496 #define mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 6497 #define mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 6498 #define mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 6499 #define mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 6500 #define mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 6501 #define mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 6502 #define mmBPHYC_UNIPHY7_UNIPHY_DEBUG 0x49d7 6503 #define mmBPHYC_UNIPHY8_UNIPHY_DEBUG 0x49f7 6504 #define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 6505 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 6506 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 6507 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 6508 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 6509 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 6510 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 6511 #define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 6512 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 6513 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 6514 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 6515 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 6516 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 6517 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 6518 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 6519 #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 6520 #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 6521 #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 6522 #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 6523 #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 6524 #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 6525 #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 6526 #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 6527 #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 6528 #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 6529 #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 6530 #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 6531 #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 6532 #define mmDPG_PIPE_DPM_CONTROL 0x1b34 6533 #define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 6534 #define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 6535 #define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 6536 #define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 6537 #define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 6538 #define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 6539 #define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 6540 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 6541 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 6542 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 6543 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 6544 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 6545 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 6546 #define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 6547 #define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 6548 #define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 6549 #define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 6550 #define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 6551 #define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 6552 #define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 6553 #define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 6554 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 6555 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 6556 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 6557 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 6558 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 6559 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 6560 #define mmDPG_REPEATER_PROGRAM 0x1b3a 6561 #define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a 6562 #define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a 6563 #define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a 6564 #define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a 6565 #define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a 6566 #define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a 6567 #define mmDPG_HW_DEBUG_A 0x1b3b 6568 #define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b 6569 #define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b 6570 #define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b 6571 #define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b 6572 #define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b 6573 #define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b 6574 #define mmDPG_HW_DEBUG_B 0x1b3c 6575 #define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c 6576 #define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c 6577 #define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c 6578 #define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c 6579 #define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c 6580 #define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c 6581 #define mmDPG_HW_DEBUG_11 0x1b3d 6582 #define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d 6583 #define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d 6584 #define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d 6585 #define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d 6586 #define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d 6587 #define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d 6588 #define mmDPG_CHK_PRE_PROC_CNTL 0x1b3e 6589 #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e 6590 #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e 6591 #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e 6592 #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e 6593 #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e 6594 #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e 6595 #define mmDPG_TEST_DEBUG_INDEX 0x1b38 6596 #define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 6597 #define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 6598 #define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 6599 #define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 6600 #define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 6601 #define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 6602 #define mmDPG_TEST_DEBUG_DATA 0x1b39 6603 #define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 6604 #define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 6605 #define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 6606 #define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 6607 #define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 6608 #define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 6609 #define mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 6610 #define mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d 6611 #define mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 6612 #define mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e 6613 #define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732 6614 #define mmDPGV1_WATERMARK_MASK_CONTROL 0x473f 6615 #define mmDPGV0_PIPE_URGENCY_CONTROL 0x4733 6616 #define mmDPGV1_PIPE_URGENCY_CONTROL 0x4740 6617 #define mmDPGV0_PIPE_DPM_CONTROL 0x4734 6618 #define mmDPGV1_PIPE_DPM_CONTROL 0x4741 6619 #define mmDPGV0_PIPE_STUTTER_CONTROL 0x4735 6620 #define mmDPGV1_PIPE_STUTTER_CONTROL 0x4742 6621 #define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 6622 #define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 6623 #define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 6624 #define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 6625 #define mmDPGV0_REPEATER_PROGRAM 0x4738 6626 #define mmDPGV1_REPEATER_PROGRAM 0x4745 6627 #define mmDPGV0_HW_DEBUG_A 0x4739 6628 #define mmDPGV1_HW_DEBUG_A 0x4746 6629 #define mmDPGV0_HW_DEBUG_B 0x473a 6630 #define mmDPGV1_HW_DEBUG_B 0x4747 6631 #define mmDPGV0_HW_DEBUG_11 0x473b 6632 #define mmDPGV1_HW_DEBUG_11 0x4748 6633 #define mmDPGV0_CHK_PRE_PROC_CNTL 0x473c 6634 #define mmDPGV1_CHK_PRE_PROC_CNTL 0x4749 6635 #define mmDPGV_TEST_DEBUG_INDEX 0x474e 6636 #define mmDPGV_TEST_DEBUG_DATA 0x474f 6637 #define ixDPGV0_DEBUG00_DMIFARB 0x1 6638 #define ixDPGV1_DEBUG00_DMIFARB 0x6a 6639 #define ixDPGV0_DEBUG01_DMIFARB 0x2 6640 #define ixDPGV1_DEBUG01_DMIFARB 0x6b 6641 #define ixDPGV0_DEBUG02_DMIFARB 0x3 6642 #define ixDPGV1_DEBUG02_DMIFARB 0x6c 6643 #define ixDPGV0_DEBUG03_DMIFARB 0x4 6644 #define ixDPGV1_DEBUG03_DMIFARB 0x6d 6645 #define ixDPGV0_DEBUG04_DMIFARB 0x5 6646 #define ixDPGV1_DEBUG04_DMIFARB 0x6e 6647 #define ixDPGV0_DEBUG00 0x6 6648 #define ixDPGV1_DEBUG00 0x6f 6649 #define ixDPGV0_DEBUG01 0x7 6650 #define ixDPGV1_DEBUG01 0x70 6651 #define ixDPGV0_DEBUG02 0x8 6652 #define ixDPGV1_DEBUG02 0x71 6653 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 6654 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 6655 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 6656 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 6657 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 6658 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 6659 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 6660 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 6661 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 6662 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 6663 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 6664 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 6665 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 6666 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 6667 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 6668 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 6669 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 6670 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 6671 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 6672 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a 6673 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b 6674 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c 6675 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d 6676 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e 6677 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f 6678 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 6679 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 6680 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 6681 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 6682 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 6683 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 6684 #define mmAZALIA_F0_CODEC_DEBUG 0x1836 6685 #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 6686 #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 6687 #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 6688 #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a 6689 #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b 6690 #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c 6691 #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d 6692 #define mmGLOBAL_CAPABILITIES 0x0 6693 #define mmMINOR_VERSION 0x0 6694 #define mmMAJOR_VERSION 0x0 6695 #define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 6696 #define mmINPUT_PAYLOAD_CAPABILITY 0x1 6697 #define mmGLOBAL_CONTROL 0x2 6698 #define mmWAKE_ENABLE 0x3 6699 #define mmSTATE_CHANGE_STATUS 0x3 6700 #define mmGLOBAL_STATUS 0x4 6701 #define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 6702 #define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 6703 #define mmINTERRUPT_CONTROL 0x8 6704 #define mmINTERRUPT_STATUS 0x9 6705 #define mmWALL_CLOCK_COUNTER 0xc 6706 #define mmSTREAM_SYNCHRONIZATION 0xe 6707 #define mmCORB_LOWER_BASE_ADDRESS 0x10 6708 #define mmCORB_UPPER_BASE_ADDRESS 0x11 6709 #define mmCORB_WRITE_POINTER 0x12 6710 #define mmCORB_READ_POINTER 0x12 6711 #define mmCORB_CONTROL 0x13 6712 #define mmCORB_STATUS 0x13 6713 #define mmCORB_SIZE 0x13 6714 #define mmRIRB_LOWER_BASE_ADDRESS 0x14 6715 #define mmRIRB_UPPER_BASE_ADDRESS 0x15 6716 #define mmRIRB_WRITE_POINTER 0x16 6717 #define mmRESPONSE_INTERRUPT_COUNT 0x16 6718 #define mmRIRB_CONTROL 0x17 6719 #define mmRIRB_STATUS 0x17 6720 #define mmRIRB_SIZE 0x17 6721 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 6722 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 6723 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 6724 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 6725 #define mmIMMEDIATE_COMMAND_STATUS 0x1a 6726 #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c 6727 #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d 6728 #define mmWALL_CLOCK_COUNTER_ALIAS 0x80c 6729 #define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 6730 #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 6731 #define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 6732 #define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 6733 #define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 6734 #define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 6735 #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 6736 #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 6737 #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 6738 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 6739 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 6740 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 6741 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 6742 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 6743 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 6744 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 6745 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 6746 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 6747 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 6748 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 6749 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 6750 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 6751 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 6752 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 6753 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 6754 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 6755 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 6756 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 6757 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 6758 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 6759 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 6760 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 6761 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 6762 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 6763 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 6764 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 6765 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 6766 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 6767 #define ixAUDIO_DESCRIPTOR0 0x1 6768 #define ixAUDIO_DESCRIPTOR1 0x2 6769 #define ixAUDIO_DESCRIPTOR2 0x3 6770 #define ixAUDIO_DESCRIPTOR3 0x4 6771 #define ixAUDIO_DESCRIPTOR4 0x5 6772 #define ixAUDIO_DESCRIPTOR5 0x6 6773 #define ixAUDIO_DESCRIPTOR6 0x7 6774 #define ixAUDIO_DESCRIPTOR7 0x8 6775 #define ixAUDIO_DESCRIPTOR8 0x9 6776 #define ixAUDIO_DESCRIPTOR9 0xa 6777 #define ixAUDIO_DESCRIPTOR10 0xb 6778 #define ixAUDIO_DESCRIPTOR11 0xc 6779 #define ixAUDIO_DESCRIPTOR12 0xd 6780 #define ixAUDIO_DESCRIPTOR13 0xe 6781 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 6782 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 6783 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 6784 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 6785 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 6786 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 6787 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 6788 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 6789 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 6790 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 6791 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 6792 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 6793 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 6794 #define ixSINK_DESCRIPTION0 0x5 6795 #define ixSINK_DESCRIPTION1 0x6 6796 #define ixSINK_DESCRIPTION2 0x7 6797 #define ixSINK_DESCRIPTION3 0x8 6798 #define ixSINK_DESCRIPTION4 0x9 6799 #define ixSINK_DESCRIPTION5 0xa 6800 #define ixSINK_DESCRIPTION6 0xb 6801 #define ixSINK_DESCRIPTION7 0xc 6802 #define ixSINK_DESCRIPTION8 0xd 6803 #define ixSINK_DESCRIPTION9 0xe 6804 #define ixSINK_DESCRIPTION10 0xf 6805 #define ixSINK_DESCRIPTION11 0x10 6806 #define ixSINK_DESCRIPTION12 0x11 6807 #define ixSINK_DESCRIPTION13 0x12 6808 #define ixSINK_DESCRIPTION14 0x13 6809 #define ixSINK_DESCRIPTION15 0x14 6810 #define ixSINK_DESCRIPTION16 0x15 6811 #define ixSINK_DESCRIPTION17 0x16 6812 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 6813 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 6814 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 6815 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 6816 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 6817 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 6818 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 6819 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 6820 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 6821 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 6822 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 6823 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 6824 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 6825 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 6826 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 6827 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 6828 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 6829 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 6830 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 6831 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 6832 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 6833 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 6834 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 6835 #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 6836 #define mmAZALIA_AUDIO_DTO 0x17e5 6837 #define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 6838 #define mmAZALIA_SCLK_CONTROL 0x17e7 6839 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 6840 #define mmAZALIA_DATA_DMA_CONTROL 0x17e9 6841 #define mmAZALIA_BDL_DMA_CONTROL 0x17ea 6842 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb 6843 #define mmAZALIA_CORB_DMA_CONTROL 0x17ec 6844 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 6845 #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 6846 #define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 6847 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 6848 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 6849 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 6850 #define mmAZALIA_CONTROLLER_DEBUG 0x17f9 6851 #define mmAZALIA_MEM_PWR_CTRL 0x1810 6852 #define mmAZALIA_MEM_PWR_STATUS 0x1811 6853 #define mmDCI_PG_DEBUG_CONFIG 0x1812 6854 #define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb 6855 #define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc 6856 #define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd 6857 #define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe 6858 #define mmAZALIA_INPUT_CRC0_RESULT 0x17ff 6859 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 6860 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 6861 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 6862 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 6863 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 6864 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 6865 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 6866 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 6867 #define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 6868 #define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 6869 #define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 6870 #define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 6871 #define mmAZALIA_INPUT_CRC1_RESULT 0x1804 6872 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 6873 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 6874 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 6875 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 6876 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 6877 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 6878 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 6879 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 6880 #define mmAZALIA_CRC0_CONTROL0 0x1805 6881 #define mmAZALIA_CRC0_CONTROL1 0x1806 6882 #define mmAZALIA_CRC0_CONTROL2 0x1807 6883 #define mmAZALIA_CRC0_CONTROL3 0x1808 6884 #define mmAZALIA_CRC0_RESULT 0x1809 6885 #define ixAZALIA_CRC0_CHANNEL0 0x0 6886 #define ixAZALIA_CRC0_CHANNEL1 0x1 6887 #define ixAZALIA_CRC0_CHANNEL2 0x2 6888 #define ixAZALIA_CRC0_CHANNEL3 0x3 6889 #define ixAZALIA_CRC0_CHANNEL4 0x4 6890 #define ixAZALIA_CRC0_CHANNEL5 0x5 6891 #define ixAZALIA_CRC0_CHANNEL6 0x6 6892 #define ixAZALIA_CRC0_CHANNEL7 0x7 6893 #define mmAZALIA_CRC1_CONTROL0 0x180a 6894 #define mmAZALIA_CRC1_CONTROL1 0x180b 6895 #define mmAZALIA_CRC1_CONTROL2 0x180c 6896 #define mmAZALIA_CRC1_CONTROL3 0x180d 6897 #define mmAZALIA_CRC1_RESULT 0x180e 6898 #define ixAZALIA_CRC1_CHANNEL0 0x0 6899 #define ixAZALIA_CRC1_CHANNEL1 0x1 6900 #define ixAZALIA_CRC1_CHANNEL2 0x2 6901 #define ixAZALIA_CRC1_CHANNEL3 0x3 6902 #define ixAZALIA_CRC1_CHANNEL4 0x4 6903 #define ixAZALIA_CRC1_CHANNEL5 0x5 6904 #define ixAZALIA_CRC1_CHANNEL6 0x6 6905 #define ixAZALIA_CRC1_CHANNEL7 0x7 6906 #define mmAZ_TEST_DEBUG_INDEX 0x181f 6907 #define mmAZ_TEST_DEBUG_DATA 0x1820 6908 #define mmAZALIA_STREAM_INDEX 0x1780 6909 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 6910 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 6911 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 6912 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 6913 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 6914 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a 6915 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c 6916 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e 6917 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 6918 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 6919 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 6920 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 6921 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 6922 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca 6923 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc 6924 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce 6925 #define mmAZALIA_STREAM_DATA 0x1781 6926 #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 6927 #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 6928 #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 6929 #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 6930 #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 6931 #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b 6932 #define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d 6933 #define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f 6934 #define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 6935 #define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 6936 #define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 6937 #define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 6938 #define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 6939 #define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb 6940 #define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd 6941 #define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf 6942 #define ixAZALIA_FIFO_SIZE_CONTROL 0x0 6943 #define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 6944 #define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 6945 #define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 6946 #define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 6947 #define ixAZALIA_STREAM_DEBUG 0x5 6948 #define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 6949 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 6950 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac 6951 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 6952 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 6953 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 6954 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc 6955 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 6956 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 6957 #define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 6958 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 6959 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad 6960 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 6961 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 6962 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 6963 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd 6964 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 6965 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 6966 #define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 6967 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 6968 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 6969 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 6970 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 6971 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 6972 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 6973 #define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 6974 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 6975 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 6976 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa 6977 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc 6978 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd 6979 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe 6980 #define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 6981 #define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 6982 #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 6983 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 6984 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 6985 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 6986 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 6987 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 6988 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a 6989 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b 6990 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c 6991 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d 6992 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e 6993 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f 6994 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 6995 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 6996 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 6997 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 6998 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 6999 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 7000 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 7001 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 7002 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 7003 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 7004 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 7005 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a 7006 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b 7007 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c 7008 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d 7009 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e 7010 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f 7011 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 7012 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 7013 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 7014 #define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 7015 #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 7016 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 7017 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 7018 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a 7019 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b 7020 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c 7021 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d 7022 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e 7023 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f 7024 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 7025 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 7026 #define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 7027 #define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 7028 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 7029 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 7030 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 7031 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 7032 #define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 7033 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 7034 #define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a 7035 #define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b 7036 #define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c 7037 #define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d 7038 #define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e 7039 #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 7040 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 7041 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 7042 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc 7043 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 7044 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 7045 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 7046 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec 7047 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 7048 #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 7049 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 7050 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 7051 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd 7052 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 7053 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 7054 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 7055 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed 7056 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 7057 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 7058 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 7059 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 7060 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 7061 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 7062 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 7063 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 7064 #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 7065 #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 7066 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 7067 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 7068 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 7069 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 7070 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 7071 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 7072 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 7073 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 7074 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 7075 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 7076 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 7077 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 7078 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 7079 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 7080 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 7081 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 7082 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 7083 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 7084 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 7085 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 7086 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 7087 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 7088 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 7089 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 7090 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 7091 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 7092 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 7093 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 7094 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 7095 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 7096 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 7097 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 7098 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 7099 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 7100 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 7101 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 7102 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 7103 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 7104 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 7105 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 7106 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 7107 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 7108 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 7109 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 7110 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 7111 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 7112 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 7113 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 7114 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 7115 #define mmBLND_CONTROL 0x1b6d 7116 #define mmBLND0_BLND_CONTROL 0x1b6d 7117 #define mmBLND1_BLND_CONTROL 0x1d6d 7118 #define mmBLND2_BLND_CONTROL 0x1f6d 7119 #define mmBLND3_BLND_CONTROL 0x416d 7120 #define mmBLND4_BLND_CONTROL 0x436d 7121 #define mmBLND5_BLND_CONTROL 0x456d 7122 #define mmBLND_SM_CONTROL2 0x1b6e 7123 #define mmBLND0_BLND_SM_CONTROL2 0x1b6e 7124 #define mmBLND1_BLND_SM_CONTROL2 0x1d6e 7125 #define mmBLND2_BLND_SM_CONTROL2 0x1f6e 7126 #define mmBLND3_BLND_SM_CONTROL2 0x416e 7127 #define mmBLND4_BLND_SM_CONTROL2 0x436e 7128 #define mmBLND5_BLND_SM_CONTROL2 0x456e 7129 #define mmBLND_CONTROL2 0x1b6f 7130 #define mmBLND0_BLND_CONTROL2 0x1b6f 7131 #define mmBLND1_BLND_CONTROL2 0x1d6f 7132 #define mmBLND2_BLND_CONTROL2 0x1f6f 7133 #define mmBLND3_BLND_CONTROL2 0x416f 7134 #define mmBLND4_BLND_CONTROL2 0x436f 7135 #define mmBLND5_BLND_CONTROL2 0x456f 7136 #define mmBLND_UPDATE 0x1b70 7137 #define mmBLND0_BLND_UPDATE 0x1b70 7138 #define mmBLND1_BLND_UPDATE 0x1d70 7139 #define mmBLND2_BLND_UPDATE 0x1f70 7140 #define mmBLND3_BLND_UPDATE 0x4170 7141 #define mmBLND4_BLND_UPDATE 0x4370 7142 #define mmBLND5_BLND_UPDATE 0x4570 7143 #define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 7144 #define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 7145 #define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 7146 #define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 7147 #define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 7148 #define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 7149 #define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 7150 #define mmBLND_V_UPDATE_LOCK 0x1b73 7151 #define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 7152 #define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 7153 #define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 7154 #define mmBLND3_BLND_V_UPDATE_LOCK 0x4173 7155 #define mmBLND4_BLND_V_UPDATE_LOCK 0x4373 7156 #define mmBLND5_BLND_V_UPDATE_LOCK 0x4573 7157 #define mmBLND_REG_UPDATE_STATUS 0x1b77 7158 #define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 7159 #define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 7160 #define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 7161 #define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 7162 #define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 7163 #define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 7164 #define mmBLND_DEBUG 0x1b74 7165 #define mmBLND0_BLND_DEBUG 0x1b74 7166 #define mmBLND1_BLND_DEBUG 0x1d74 7167 #define mmBLND2_BLND_DEBUG 0x1f74 7168 #define mmBLND3_BLND_DEBUG 0x4174 7169 #define mmBLND4_BLND_DEBUG 0x4374 7170 #define mmBLND5_BLND_DEBUG 0x4574 7171 #define mmBLND_TEST_DEBUG_INDEX 0x1b75 7172 #define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 7173 #define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 7174 #define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 7175 #define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 7176 #define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 7177 #define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 7178 #define mmBLND_TEST_DEBUG_DATA 0x1b76 7179 #define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 7180 #define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 7181 #define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 7182 #define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 7183 #define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 7184 #define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 7185 #define mmWB_ENABLE 0x5e18 7186 #define mmWB_EC_CONFIG 0x5e19 7187 #define mmCNV_MODE 0x5e1a 7188 #define mmCNV_WINDOW_START 0x5e1b 7189 #define mmCNV_WINDOW_SIZE 0x5e1c 7190 #define mmCNV_UPDATE 0x5e1d 7191 #define mmCNV_SOURCE_SIZE 0x5e1e 7192 #define mmCNV_CSC_CONTROL 0x5e1f 7193 #define mmCNV_CSC_C11_C12 0x5e20 7194 #define mmCNV_CSC_C13_C14 0x5e21 7195 #define mmCNV_CSC_C21_C22 0x5e22 7196 #define mmCNV_CSC_C23_C24 0x5e23 7197 #define mmCNV_CSC_C31_C32 0x5e24 7198 #define mmCNV_CSC_C33_C34 0x5e25 7199 #define mmCNV_CSC_ROUND_OFFSET_R 0x5e26 7200 #define mmCNV_CSC_ROUND_OFFSET_G 0x5e27 7201 #define mmCNV_CSC_ROUND_OFFSET_B 0x5e28 7202 #define mmCNV_CSC_CLAMP_R 0x5e29 7203 #define mmCNV_CSC_CLAMP_G 0x5e2a 7204 #define mmCNV_CSC_CLAMP_B 0x5e2b 7205 #define mmCNV_TEST_CNTL 0x5e2c 7206 #define mmCNV_TEST_CRC_RED 0x5e2d 7207 #define mmCNV_TEST_CRC_GREEN 0x5e2e 7208 #define mmCNV_TEST_CRC_BLUE 0x5e2f 7209 #define mmWB_DEBUG_CTRL 0x5e30 7210 #define mmWB_DBG_MODE 0x5e31 7211 #define mmWB_HW_DEBUG 0x5e32 7212 #define mmCNV_INPUT_SELECT 0x5e33 7213 #define mmWB_SOFT_RESET 0x5e36 7214 #define mmCNV_TEST_DEBUG_INDEX 0x5e34 7215 #define mmCNV_TEST_DEBUG_DATA 0x5e35 7216 #define mmDCFE_CLOCK_CONTROL 0x1b00 7217 #define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 7218 #define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 7219 #define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 7220 #define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 7221 #define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 7222 #define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 7223 #define mmDCFE_SOFT_RESET 0x1b01 7224 #define mmDCFE0_DCFE_SOFT_RESET 0x1b01 7225 #define mmDCFE1_DCFE_SOFT_RESET 0x1d01 7226 #define mmDCFE2_DCFE_SOFT_RESET 0x1f01 7227 #define mmDCFE3_DCFE_SOFT_RESET 0x4101 7228 #define mmDCFE4_DCFE_SOFT_RESET 0x4301 7229 #define mmDCFE5_DCFE_SOFT_RESET 0x4501 7230 #define mmDCFE_DBG_CONFIG 0x1b02 7231 #define mmDCFE0_DCFE_DBG_CONFIG 0x1b02 7232 #define mmDCFE1_DCFE_DBG_CONFIG 0x1d02 7233 #define mmDCFE2_DCFE_DBG_CONFIG 0x1f02 7234 #define mmDCFE3_DCFE_DBG_CONFIG 0x4102 7235 #define mmDCFE4_DCFE_DBG_CONFIG 0x4302 7236 #define mmDCFE5_DCFE_DBG_CONFIG 0x4502 7237 #define mmDCFE_MEM_PWR_CTRL 0x1b03 7238 #define mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03 7239 #define mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03 7240 #define mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03 7241 #define mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103 7242 #define mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303 7243 #define mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503 7244 #define mmDCFE_MEM_PWR_CTRL2 0x1b04 7245 #define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04 7246 #define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04 7247 #define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04 7248 #define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104 7249 #define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304 7250 #define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504 7251 #define mmDCFE_MEM_PWR_STATUS 0x1b05 7252 #define mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05 7253 #define mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05 7254 #define mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05 7255 #define mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105 7256 #define mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305 7257 #define mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505 7258 #define mmDCFE_MISC 0x1b06 7259 #define mmDCFE0_DCFE_MISC 0x1b06 7260 #define mmDCFE1_DCFE_MISC 0x1d06 7261 #define mmDCFE2_DCFE_MISC 0x1f06 7262 #define mmDCFE3_DCFE_MISC 0x4106 7263 #define mmDCFE4_DCFE_MISC 0x4306 7264 #define mmDCFE5_DCFE_MISC 0x4506 7265 #define mmDCFEV_CLOCK_CONTROL 0x46f4 7266 #define mmDCFEV_SOFT_RESET 0x46f5 7267 #define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 7268 #define mmDCFEV_DBG_CONFIG 0x46f7 7269 #define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 7270 #define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 7271 #define mmDCFEV_MEM_PWR_CTRL 0x46fa 7272 #define mmDCFEV_MEM_PWR_CTRL2 0x46fb 7273 #define mmDCFEV_MEM_PWR_STATUS 0x46fc 7274 #define mmDCFEV_DMIFV_DEBUG 0x46fd 7275 #define mmDCFEV_MISC 0x46fe 7276 #define mmDC_HPD_INT_STATUS 0x1898 7277 #define mmHPD0_DC_HPD_INT_STATUS 0x1898 7278 #define mmHPD1_DC_HPD_INT_STATUS 0x18a0 7279 #define mmHPD2_DC_HPD_INT_STATUS 0x18a8 7280 #define mmHPD3_DC_HPD_INT_STATUS 0x18b0 7281 #define mmHPD4_DC_HPD_INT_STATUS 0x18b8 7282 #define mmHPD5_DC_HPD_INT_STATUS 0x18c0 7283 #define mmDC_HPD_INT_CONTROL 0x1899 7284 #define mmHPD0_DC_HPD_INT_CONTROL 0x1899 7285 #define mmHPD1_DC_HPD_INT_CONTROL 0x18a1 7286 #define mmHPD2_DC_HPD_INT_CONTROL 0x18a9 7287 #define mmHPD3_DC_HPD_INT_CONTROL 0x18b1 7288 #define mmHPD4_DC_HPD_INT_CONTROL 0x18b9 7289 #define mmHPD5_DC_HPD_INT_CONTROL 0x18c1 7290 #define mmDC_HPD_CONTROL 0x189a 7291 #define mmHPD0_DC_HPD_CONTROL 0x189a 7292 #define mmHPD1_DC_HPD_CONTROL 0x18a2 7293 #define mmHPD2_DC_HPD_CONTROL 0x18aa 7294 #define mmHPD3_DC_HPD_CONTROL 0x18b2 7295 #define mmHPD4_DC_HPD_CONTROL 0x18ba 7296 #define mmHPD5_DC_HPD_CONTROL 0x18c2 7297 #define mmDC_HPD_FAST_TRAIN_CNTL 0x189b 7298 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b 7299 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 7300 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab 7301 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 7302 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb 7303 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 7304 #define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c 7305 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c 7306 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 7307 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac 7308 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 7309 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc 7310 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 7311 #define mmDCO_SCRATCH0 0x184e 7312 #define mmDCO_SCRATCH1 0x184f 7313 #define mmDCO_SCRATCH2 0x1850 7314 #define mmDCO_SCRATCH3 0x1851 7315 #define mmDCO_SCRATCH4 0x1852 7316 #define mmDCO_SCRATCH5 0x1853 7317 #define mmDCO_SCRATCH6 0x1854 7318 #define mmDCO_SCRATCH7 0x1855 7319 #define mmDCE_VCE_CONTROL 0x1856 7320 #define mmDISP_INTERRUPT_STATUS 0x1857 7321 #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 7322 #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 7323 #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a 7324 #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b 7325 #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c 7326 #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d 7327 #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e 7328 #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f 7329 #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 7330 #define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875 7331 #define mmDCO_MEM_PWR_STATUS 0x1861 7332 #define mmDCO_MEM_PWR_STATUS1 0x1874 7333 #define mmDCO_MEM_PWR_CTRL 0x1862 7334 #define mmDCO_MEM_PWR_CTRL2 0x1863 7335 #define mmDCO_CLK_CNTL 0x1864 7336 #define mmDCO_CLK_CNTL2 0x1876 7337 #define mmDCO_CLK_CNTL3 0x1877 7338 #define mmDPDBG_CNTL 0x1866 7339 #define mmDPDBG_INTERRUPT 0x1867 7340 #define mmDCO_POWER_MANAGEMENT_CNTL 0x1868 7341 #define mmDCO_SOFT_RESET 0x1871 7342 #define mmDIG_SOFT_RESET 0x1872 7343 #define mmDIG_SOFT_RESET_2 0x186a 7344 #define mmDCO_STEREOSYNC_SEL 0x186e 7345 #define mmDCO_TEST_DEBUG_INDEX 0x186f 7346 #define mmDCO_TEST_DEBUG_DATA 0x1870 7347 #define mmDC_I2C_CONTROL 0x16d4 7348 #define mmDC_I2C_ARBITRATION 0x16d5 7349 #define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 7350 #define mmDC_I2C_SW_STATUS 0x16d7 7351 #define mmDC_I2C_DDC1_HW_STATUS 0x16d8 7352 #define mmDC_I2C_DDC2_HW_STATUS 0x16d9 7353 #define mmDC_I2C_DDC3_HW_STATUS 0x16da 7354 #define mmDC_I2C_DDC4_HW_STATUS 0x16db 7355 #define mmDC_I2C_DDC5_HW_STATUS 0x16dc 7356 #define mmDC_I2C_DDC6_HW_STATUS 0x16dd 7357 #define mmDC_I2C_DDC1_SPEED 0x16de 7358 #define mmDC_I2C_DDC1_SETUP 0x16df 7359 #define mmDC_I2C_DDC2_SPEED 0x16e0 7360 #define mmDC_I2C_DDC2_SETUP 0x16e1 7361 #define mmDC_I2C_DDC3_SPEED 0x16e2 7362 #define mmDC_I2C_DDC3_SETUP 0x16e3 7363 #define mmDC_I2C_DDC4_SPEED 0x16e4 7364 #define mmDC_I2C_DDC4_SETUP 0x16e5 7365 #define mmDC_I2C_DDC5_SPEED 0x16e6 7366 #define mmDC_I2C_DDC5_SETUP 0x16e7 7367 #define mmDC_I2C_DDC6_SPEED 0x16e8 7368 #define mmDC_I2C_DDC6_SETUP 0x16e9 7369 #define mmDC_I2C_TRANSACTION0 0x16ea 7370 #define mmDC_I2C_TRANSACTION1 0x16eb 7371 #define mmDC_I2C_TRANSACTION2 0x16ec 7372 #define mmDC_I2C_TRANSACTION3 0x16ed 7373 #define mmDC_I2C_DATA 0x16ee 7374 #define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef 7375 #define mmDC_I2C_DDCVGA_SPEED 0x16f0 7376 #define mmDC_I2C_DDCVGA_SETUP 0x16f1 7377 #define mmDC_I2C_EDID_DETECT_CTRL 0x16f2 7378 #define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 7379 #define mmGENERIC_I2C_CONTROL 0x16f4 7380 #define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 7381 #define mmGENERIC_I2C_STATUS 0x16f6 7382 #define mmGENERIC_I2C_SPEED 0x16f7 7383 #define mmGENERIC_I2C_SETUP 0x16f8 7384 #define mmGENERIC_I2C_TRANSACTION 0x16f9 7385 #define mmGENERIC_I2C_DATA 0x16fa 7386 #define mmGENERIC_I2C_PIN_SELECTION 0x16fb 7387 #define mmGENERIC_I2C_PIN_DEBUG 0x16fc 7388 #define mmBLNDV_CONTROL 0x476d 7389 #define mmBLNDV_SM_CONTROL2 0x476e 7390 #define mmBLNDV_CONTROL2 0x476f 7391 #define mmBLNDV_UPDATE 0x4770 7392 #define mmBLNDV_UNDERFLOW_INTERRUPT 0x4771 7393 #define mmBLNDV_V_UPDATE_LOCK 0x4773 7394 #define mmBLNDV_REG_UPDATE_STATUS 0x4777 7395 #define mmBLNDV_DEBUG 0x4774 7396 #define mmBLNDV_TEST_DEBUG_INDEX 0x4775 7397 #define mmBLNDV_TEST_DEBUG_DATA 0x4776 7398 #define mmCRTCV_H_BLANK_EARLY_NUM 0x477d 7399 #define mmCRTCV_H_TOTAL 0x4780 7400 #define mmCRTCV_H_BLANK_START_END 0x4781 7401 #define mmCRTCV_H_SYNC_A 0x4782 7402 #define mmCRTCV_H_SYNC_A_CNTL 0x4783 7403 #define mmCRTCV_H_SYNC_B 0x4784 7404 #define mmCRTCV_H_SYNC_B_CNTL 0x4785 7405 #define mmCRTCV_VBI_END 0x4786 7406 #define mmCRTCV_V_TOTAL 0x4787 7407 #define mmCRTCV_V_TOTAL_MIN 0x4788 7408 #define mmCRTCV_V_TOTAL_MAX 0x4789 7409 #define mmCRTCV_V_TOTAL_CONTROL 0x478a 7410 #define mmCRTCV_V_TOTAL_INT_STATUS 0x478b 7411 #define mmCRTCV_VSYNC_NOM_INT_STATUS 0x478c 7412 #define mmCRTCV_V_BLANK_START_END 0x478d 7413 #define mmCRTCV_V_SYNC_A 0x478e 7414 #define mmCRTCV_V_SYNC_A_CNTL 0x478f 7415 #define mmCRTCV_V_SYNC_B 0x4790 7416 #define mmCRTCV_V_SYNC_B_CNTL 0x4791 7417 #define mmCRTCV_DTMTEST_CNTL 0x4792 7418 #define mmCRTCV_DTMTEST_STATUS_POSITION 0x4793 7419 #define mmCRTCV_TRIGA_CNTL 0x4794 7420 #define mmCRTCV_TRIGA_MANUAL_TRIG 0x4795 7421 #define mmCRTCV_TRIGB_CNTL 0x4796 7422 #define mmCRTCV_TRIGB_MANUAL_TRIG 0x4797 7423 #define mmCRTCV_FORCE_COUNT_NOW_CNTL 0x4798 7424 #define mmCRTCV_FLOW_CONTROL 0x4799 7425 #define mmCRTCV_STEREO_FORCE_NEXT_EYE 0x479a 7426 #define mmCRTCV_AVSYNC_COUNTER 0x479b 7427 #define mmCRTCV_CONTROL 0x479c 7428 #define mmCRTCV_BLANK_CONTROL 0x479d 7429 #define mmCRTCV_INTERLACE_CONTROL 0x479e 7430 #define mmCRTCV_INTERLACE_STATUS 0x479f 7431 #define mmCRTCV_FIELD_INDICATION_CONTROL 0x47a0 7432 #define mmCRTCV_PIXEL_DATA_READBACK0 0x47a1 7433 #define mmCRTCV_PIXEL_DATA_READBACK1 0x47a2 7434 #define mmCRTCV_STATUS 0x47a3 7435 #define mmCRTCV_STATUS_POSITION 0x47a4 7436 #define mmCRTCV_NOM_VERT_POSITION 0x47a5 7437 #define mmCRTCV_STATUS_FRAME_COUNT 0x47a6 7438 #define mmCRTCV_STATUS_VF_COUNT 0x47a7 7439 #define mmCRTCV_STATUS_HV_COUNT 0x47a8 7440 #define mmCRTCV_COUNT_CONTROL 0x47a9 7441 #define mmCRTCV_COUNT_RESET 0x47aa 7442 #define mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab 7443 #define mmCRTCV_VERT_SYNC_CONTROL 0x47ac 7444 #define mmCRTCV_STEREO_STATUS 0x47ad 7445 #define mmCRTCV_STEREO_CONTROL 0x47ae 7446 #define mmCRTCV_SNAPSHOT_STATUS 0x47af 7447 #define mmCRTCV_SNAPSHOT_CONTROL 0x47b0 7448 #define mmCRTCV_SNAPSHOT_POSITION 0x47b1 7449 #define mmCRTCV_SNAPSHOT_FRAME 0x47b2 7450 #define mmCRTCV_START_LINE_CONTROL 0x47b3 7451 #define mmCRTCV_INTERRUPT_CONTROL 0x47b4 7452 #define mmCRTCV_UPDATE_LOCK 0x47b5 7453 #define mmCRTCV_DOUBLE_BUFFER_CONTROL 0x47b6 7454 #define mmCRTCV_VGA_PARAMETER_CAPTURE_MODE 0x47b7 7455 #define mmCRTCV_TEST_PATTERN_CONTROL 0x47ba 7456 #define mmCRTCV_TEST_PATTERN_PARAMETERS 0x47bb 7457 #define mmCRTCV_TEST_PATTERN_COLOR 0x47bc 7458 #define mmCRTCV_MASTER_UPDATE_LOCK 0x47bd 7459 #define mmCRTCV_MASTER_UPDATE_MODE 0x47be 7460 #define mmCRTCV_MVP_INBAND_CNTL_INSERT 0x47bf 7461 #define mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 7462 #define mmCRTCV_MVP_STATUS 0x47c1 7463 #define mmCRTCV_MASTER_EN 0x47c2 7464 #define mmCRTCV_ALLOW_STOP_OFF_V_CNT 0x47c3 7465 #define mmCRTCV_V_UPDATE_INT_STATUS 0x47c4 7466 #define mmCRTCV_OVERSCAN_COLOR 0x47c8 7467 #define mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9 7468 #define mmCRTCV_BLANK_DATA_COLOR 0x47ca 7469 #define mmCRTCV_BLANK_DATA_COLOR_EXT 0x47cb 7470 #define mmCRTCV_BLACK_COLOR 0x47cc 7471 #define mmCRTCV_BLACK_COLOR_EXT 0x47cd 7472 #define mmCRTCV_VERTICAL_INTERRUPT0_POSITION 0x47ce 7473 #define mmCRTCV_VERTICAL_INTERRUPT0_CONTROL 0x47cf 7474 #define mmCRTCV_VERTICAL_INTERRUPT1_POSITION 0x47d0 7475 #define mmCRTCV_VERTICAL_INTERRUPT1_CONTROL 0x47d1 7476 #define mmCRTCV_VERTICAL_INTERRUPT2_POSITION 0x47d2 7477 #define mmCRTCV_VERTICAL_INTERRUPT2_CONTROL 0x47d3 7478 #define mmCRTCV_CRC_CNTL 0x47d4 7479 #define mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 7480 #define mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 7481 #define mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 7482 #define mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 7483 #define mmCRTCV_CRC0_DATA_RG 0x47d9 7484 #define mmCRTCV_CRC0_DATA_B 0x47da 7485 #define mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db 7486 #define mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc 7487 #define mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd 7488 #define mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de 7489 #define mmCRTCV_CRC1_DATA_RG 0x47df 7490 #define mmCRTCV_CRC1_DATA_B 0x47e0 7491 #define mmCRTCV_STATIC_SCREEN_CONTROL 0x47e7 7492 #define mmCRTCV_3D_STRUCTURE_CONTROL 0x4778 7493 #define mmCRTCV_GSL_VSYNC_GAP 0x4779 7494 #define mmCRTCV_GSL_WINDOW 0x477a 7495 #define mmCRTCV_GSL_CONTROL 0x477b 7496 #define mmCRTCV_TEST_DEBUG_INDEX 0x47c6 7497 #define mmCRTCV_TEST_DEBUG_DATA 0x47c7 7498 #define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 7499 #define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 7500 #define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 7501 #define mmXDMA_INTERRUPT 0x3e3 7502 #define mmXDMA_CLOCK_GATING_CNTL 0x3e4 7503 #define mmXDMA_MEM_POWER_CNTL 0x3e6 7504 #define mmXDMA_IF_BIF_STATUS 0x3e7 7505 #define mmXDMA_PERF_MEAS_STATUS 0x3e8 7506 #define mmXDMA_IF_STATUS 0x3e9 7507 #define mmXDMA_TEST_DEBUG_INDEX 0x3ea 7508 #define mmXDMA_TEST_DEBUG_DATA 0x3eb 7509 #define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 7510 #define mmXDMA_PG_CONTROL 0x3f9 7511 #define mmXDMA_PG_WDATA 0x3fa 7512 #define mmXDMA_PG_STATUS 0x3fb 7513 #define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc 7514 #define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd 7515 #define mmXDMA_MSTR_CNTL 0x3ec 7516 #define mmXDMA_MSTR_STATUS 0x3ed 7517 #define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee 7518 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef 7519 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 7520 #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 7521 #define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 7522 #define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 7523 #define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 7524 #define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 7525 #define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 7526 #define mmXDMA_MSTR_PIPE_CNTL 0x400 7527 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 7528 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 7529 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 7530 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 7531 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 7532 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 7533 #define mmXDMA_MSTR_READ_COMMAND 0x401 7534 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 7535 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 7536 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 7537 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 7538 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 7539 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 7540 #define mmXDMA_MSTR_CHANNEL_DIM 0x402 7541 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 7542 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 7543 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 7544 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 7545 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 7546 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 7547 #define mmXDMA_MSTR_HEIGHT 0x403 7548 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 7549 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 7550 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 7551 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 7552 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 7553 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 7554 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 7555 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 7556 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 7557 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 7558 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 7559 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 7560 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 7561 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 7562 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 7563 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 7564 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 7565 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 7566 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 7567 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 7568 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 7569 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 7570 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 7571 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 7572 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 7573 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 7574 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 7575 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 7576 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 7577 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 7578 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 7579 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 7580 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 7581 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 7582 #define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 7583 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 7584 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 7585 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 7586 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 7587 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 7588 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 7589 #define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 7590 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 7591 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 7592 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 7593 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 7594 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 7595 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 7596 #define mmXDMA_MSTR_CACHE 0x40a 7597 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a 7598 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a 7599 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a 7600 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a 7601 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a 7602 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a 7603 #define mmXDMA_MSTR_CHANNEL_START 0x40b 7604 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b 7605 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b 7606 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b 7607 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b 7608 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b 7609 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b 7610 #define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e 7611 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e 7612 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e 7613 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e 7614 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e 7615 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e 7616 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e 7617 #define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f 7618 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f 7619 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f 7620 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f 7621 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f 7622 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f 7623 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f 7624 #define mmXDMA_SLV_CNTL 0x460 7625 #define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 7626 #define mmXDMA_SLV_SLS_PITCH 0x462 7627 #define mmXDMA_SLV_READ_URGENT_CNTL 0x463 7628 #define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 7629 #define mmXDMA_SLV_WB_RATE_CNTL 0x465 7630 #define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 7631 #define mmXDMA_SLV_READ_LATENCY_AVE 0x467 7632 #define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 7633 #define mmXDMA_SLV_MEM_NACK_STATUS 0x469 7634 #define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a 7635 #define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b 7636 #define mmXDMA_SLV_FLIP_PENDING 0x46c 7637 #define mmXDMA_SLV_CHANNEL_CNTL 0x470 7638 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 7639 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 7640 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 7641 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 7642 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 7643 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 7644 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 7645 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 7646 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 7647 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 7648 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 7649 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 7650 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 7651 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 7652 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 7653 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a 7654 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 7655 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a 7656 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 7657 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a 7658 7659 #endif /* DCE_11_0_D_H */ 7660
Indexes created Sun Sep 28 07:09:56 GMT 2025