1 /* $NetBSD: vce_2_0_d.h,v 1.3 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * VCE_2_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef VCE_2_0_D_H 27 #define VCE_2_0_D_H 28 29 #define mmVCE_STATUS 0x8001 30 #define mmVCE_VCPU_CNTL 0x8005 31 #define mmVCE_VCPU_CACHE_OFFSET0 0x8009 32 #define mmVCE_VCPU_CACHE_SIZE0 0x800a 33 #define mmVCE_VCPU_CACHE_OFFSET1 0x800b 34 #define mmVCE_VCPU_CACHE_SIZE1 0x800c 35 #define mmVCE_VCPU_CACHE_OFFSET2 0x800d 36 #define mmVCE_VCPU_CACHE_SIZE2 0x800e 37 #define mmVCE_SOFT_RESET 0x8048 38 #define mmVCE_RB_BASE_LO2 0x805b 39 #define mmVCE_RB_BASE_HI2 0x805c 40 #define mmVCE_RB_SIZE2 0x805d 41 #define mmVCE_RB_RPTR2 0x805e 42 #define mmVCE_RB_WPTR2 0x805f 43 #define mmVCE_RB_BASE_LO 0x8060 44 #define mmVCE_RB_BASE_HI 0x8061 45 #define mmVCE_RB_SIZE 0x8062 46 #define mmVCE_RB_RPTR 0x8063 47 #define mmVCE_RB_WPTR 0x8064 48 #define mmVCE_RB_ARB_CTRL 0x809f 49 #define mmVCE_CLOCK_GATING_A 0x80be 50 #define mmVCE_CLOCK_GATING_B 0x80bf 51 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8390 52 #define mmVCE_CGTT_CLK_OVERRIDE 0x81e8 53 #define mmVCE_UENC_CLOCK_GATING 0x81ef 54 #define mmVCE_UENC_REG_CLOCK_GATING 0x81f0 55 #define mmVCE_SYS_INT_EN 0x84c0 56 #define mmVCE_SYS_INT_STATUS 0x84c1 57 #define mmVCE_SYS_INT_ACK 0x84c1 58 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8517 59 #define mmVCE_LMI_CTRL2 0x851d 60 #define mmVCE_LMI_SWAP_CNTL3 0x851e 61 #define mmVCE_LMI_CTRL 0x8526 62 #define mmVCE_LMI_STATUS 0x8527 63 #define mmVCE_LMI_VM_CTRL 0x8528 64 #define mmVCE_LMI_SWAP_CNTL 0x852d 65 #define mmVCE_LMI_SWAP_CNTL1 0x852e 66 #define mmVCE_LMI_SWAP_CNTL2 0x8533 67 #define mmVCE_LMI_MISC_CTRL 0x8535 68 #define mmVCE_LMI_CACHE_CTRL 0x853d 69 70 #endif /* VCE_2_0_D_H */ 71
Indexes created Wed Oct 01 13:09:50 GMT 2025