| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| priv.h | 14 u32 (*mmio)(struct nvkm_devinit *, u32); member in struct:nvkm_devinit_func
|
| nouveau_nvkm_subdev_devinit_gt215.c | 111 u32 *mmio = gt215_devinit_mmio_part; local in function:gt215_devinit_mmio
128 while (mmio[0]) {
129 if (addr >= mmio[0] && addr <= mmio[1]) {
130 u32 part = (addr / mmio[2]) & 7;
137 mmio += 3;
148 .mmio = gt215_devinit_mmio,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| mmio.c | 1 /* $NetBSD: mmio.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */
39 __KERNEL_RCSID(0, "$NetBSD: mmio.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $");
45 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
98 * intel_vgpu_emulate_mmio_read - emulate MMIO read
162 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
170 * intel_vgpu_emulate_mmio_write - emulate MMIO write
226 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
235 * intel_vgpu_reset_mmio - reset virtual MMIO space
243 void *mmio = gvt->firmware.mmio; local in function:intel_vgpu_reset_mmio
[all...] |
| mmio_context.c | 203 struct engine_mmio *mmio; local in function:restore_context_mmio_for_inhibit
220 for (mmio = gvt->engine_mmio_list.mmio;
221 i915_mmio_reg_valid(mmio->reg); mmio++) {
222 if (mmio->ring_id != ring_id ||
223 !mmio->in_context)
226 *cs++ = i915_mmio_reg_offset(mmio->reg);
227 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
228 (mmio->mask << 16)
479 struct engine_mmio *mmio; local in function:switch_mmio
586 struct engine_mmio *mmio; local in function:intel_gvt_init_engine_mmio_context
[all...] |
| scheduler.c | 124 u32 mmio = flex_mmio[i]; local in function:sr_oa_regs
126 reg_state[state_offset] = mmio;
270 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
|
| gvt.h | 40 #include "mmio.h"
190 struct intel_vgpu_mmio mmio; member in struct:intel_vgpu
249 /* Special MMIO blocks. */
288 void *mmio; member in struct:intel_gvt_firmware
317 struct intel_gvt_mmio mmio; member in struct:intel_gvt
337 struct engine_mmio *mmio; member in struct:intel_gvt::__anon1940818c0408
446 Explicitly seperate use for typed MMIO reg or real offset.*/
448 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
450 (*(u32 *)(vgpu->mmio.vreg + (offset)))
452 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))
[all...] |
| /src/sys/external/bsd/drm/dist/shared-core/ |
| sis_drv.h | 54 #define SIS_BASE (dev_priv->mmio)
59 drm_local_map_t *mmio; member in struct:drm_sis_private
|
| r128_drv.h | 119 drm_local_map_t *mmio; member in struct:drm_r128_private
393 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
394 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
395 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
396 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
|
| savage_drv.h | 155 drm_local_map_t *mmio; member in struct:drm_savage_private
231 * inside the MMIO region */
236 * MMIO registers
486 * access to MMIO
488 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
489 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
|
| mach64_drv.h | 79 drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */
107 drm_local_map_t *mmio; member in struct:drm_mach64_private
491 #define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) )
492 #define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) )
|
| mga_drv.h | 111 * \name MMIO region parameters.
113 * \sa drm_mga_private_t::mmio
116 u32 mmio_base; /**< Bus address of base of MMIO. */
117 u32 mmio_size; /**< Size of the MMIO region. */
142 drm_local_map_t *mmio; member in struct:drm_mga_private
200 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
217 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
218 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
219 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
220 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)
[all...] |
| radeon_drv.h | 347 drm_local_map_t *mmio; member in struct:drm_radeon_private
1866 DRM_WRITE32( dev_priv->mmio, (reg), (val) ); \
1868 DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, (reg) ); \
1869 DRM_WRITE32( dev_priv->mmio, RADEON_MM_DATA, (val) ); \
1872 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1873 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
|
| /src/sys/external/bsd/drm2/dist/drm/sis/ |
| sis_drv.h | 53 #define SIS_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
54 #define SIS_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
57 drm_local_map_t *mmio; member in struct:drm_sis_private
|
| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| intel_uncore.c | 197 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset); local in function:live_forcewake_ops
205 fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio,
310 pr_err("Unclaimed mmio read to register 0x%04x\n",
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| ctxgf100.h | 11 struct gf100_gr_mmio *mmio; member in struct:gf100_grctx
31 /* mmio context data */
|
| gf100.h | 183 const struct gf100_gr_pack *mmio; member in struct:gf100_gr_func
263 struct nvkm_memory *mmio; member in struct:gf100_gr_chan
|
| nouveau_nvkm_engine_gr_gf100.c | 373 nvkm_memory_unref(&chan->mmio);
391 struct gf100_gr_mmio *mmio = gr->mmio_list; local in function:gf100_gr_chan_new
404 /* allocate memory for a "mmio list" buffer that's used by the HUB
409 false, &chan->mmio);
417 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
422 /* allocate buffers referenced by mmio list */
446 /* finally, fill in the mmio list and point the context at it */
447 nvkm_kmap(chan->mmio);
448 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
449 u32 addr = mmio->addr
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/via/ |
| via_drv.h | 85 drm_local_map_t *mmio; member in struct:drm_via_private
139 /* VIA MMIO register access */
142 return DRM_READ32(dev_priv->mmio, reg);
148 DRM_WRITE32(dev_priv->mmio, reg, val);
154 DRM_WRITE8(dev_priv->mmio, reg, val);
162 tmp = DRM_READ8(dev_priv->mmio, reg);
164 DRM_WRITE8(dev_priv->mmio, reg, tmp);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gpu_error.c | 1161 i915_reg_t mmio; local in function:engine_record_registers
1169 mmio = RENDER_HWS_PGA_GEN7;
1172 mmio = BLT_HWS_PGA_GEN7;
1175 mmio = BSD_HWS_PGA_GEN7;
1178 mmio = VEBOX_HWS_PGA_GEN7;
1182 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1185 mmio = RING_HWS_PGA(engine->mmio_base);
1188 ee->hws = intel_uncore_read(engine->uncore, mmio);
|
| i915_perf.c | 1589 * "This MMIO must be set before the OATAILPTR
1644 * "This MMIO must be set before the OATAILPTR
2152 u32 mmio = i915_mmio_reg_offset(reg); local in function:oa_config_flex_reg
2164 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2183 /* The MMIO offsets for Flex EU registers aren't contiguous */
2484 /* The MMIO offsets for Flex EU registers aren't contiguous */
2927 * This can be achieved by programming MMIO registers as
4059 #define REG_EQUAL(addr, mmio) \
4060 ((addr) == i915_mmio_reg_offset(mmio))
|
| /src/sys/external/bsd/drm2/dist/drm/r128/ |
| r128_drv.h | 131 drm_local_map_t *mmio; member in struct:drm_r128_private
409 #define R128_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
410 #define R128_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
411 #define R128_READ8(reg) readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
412 #define R128_WRITE8(reg, val) writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
|
| /src/sys/external/bsd/drm2/dist/drm/savage/ |
| savage_drv.h | 163 drm_local_map_t *mmio; member in struct:drm_savage_private
236 * inside the MMIO region */
241 * MMIO registers
491 * access to MMIO
494 readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
496 writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
|
| /src/sys/external/bsd/drm2/dist/drm/mga/ |
| mga_drv.h | 128 * \name MMIO region parameters.
130 * \sa drm_mga_private_t::mmio
133 resource_size_t mmio_base; /**< Bus address of base of MMIO. */
134 resource_size_t mmio_size; /**< Size of the MMIO region. */
159 drm_local_map_t *mmio; member in struct:drm_mga_private
218 readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
220 readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
222 writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
224 writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
|
