| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/ |
| mt8167.dtsi | 129 mmsys: mmsys@14000000 { label
130 compatible = "mediatek,mt8167-mmsys", "syscon";
138 clocks = <&mmsys CLK_MM_SMI_COMMON>,
139 <&mmsys CLK_MM_SMI_COMMON>;
148 clocks = <&mmsys CLK_MM_SMI_LARB0>,
149 <&mmsys CLK_MM_SMI_LARB0>;
|
| mt6779.dtsi | 251 mmsys: syscon@14000000 { label
252 compatible = "mediatek,mt6779-mmsys", "syscon";
|
| mt6797.dtsi | 449 mmsys: syscon@14000000 { label
450 compatible = "mediatek,mt6797-mmsys", "syscon";
|
| mt2712e.dtsi | 985 mmsys: syscon@14000000 { label
986 compatible = "mediatek,mt2712-mmsys", "syscon";
997 clocks = <&mmsys CLK_MM_SMI_LARB0>,
998 <&mmsys CLK_MM_SMI_LARB0>;
1006 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1007 <&mmsys CLK_MM_SMI_COMMON>;
1017 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1018 <&mmsys CLK_MM_SMI_LARB4>;
1028 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1029 <&mmsys CLK_MM_SMI_LARB5>
[all...] |
| mt8183.dtsi | 476 <&mmsys CLK_MM_SMI_COMMON>,
477 <&mmsys CLK_MM_SMI_LARB0>,
478 <&mmsys CLK_MM_SMI_LARB1>,
479 <&mmsys CLK_MM_GALS_COMM0>,
480 <&mmsys CLK_MM_GALS_COMM1>,
481 <&mmsys CLK_MM_GALS_CCU2MM>,
482 <&mmsys CLK_MM_GALS_IPU12MM>,
483 <&mmsys CLK_MM_GALS_IMG2MM>,
484 <&mmsys CLK_MM_GALS_CAM2MM>,
485 <&mmsys CLK_MM_GALS_IPU2MM>
1226 mmsys: syscon@14000000 { label
[all...] |
| mt8173.dtsi | 992 mmsys: syscon@14000000 { label
993 compatible = "mediatek,mt8173-mmsys", "syscon";
1008 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1009 <&mmsys CLK_MM_MUTEX_32K>;
1019 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1020 <&mmsys CLK_MM_MUTEX_32K>;
1029 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1036 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1043 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1050 clocks = <&mmsys CLK_MM_MDP_WDMA>
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| mt7623n.dtsi | 51 mmsys: syscon@14000000 { label
52 compatible = "mediatek,mt7623-mmsys",
53 "mediatek,mt2701-mmsys",
65 clocks = <&mmsys CLK_MM_SMI_LARB0>,
66 <&mmsys CLK_MM_SMI_LARB0>;
134 <&mmsys CLK_MM_SMI_COMMON>,
145 clocks = <&mmsys CLK_MM_DISP_OVL>;
155 clocks = <&mmsys CLK_MM_DISP_RDMA>;
165 clocks = <&mmsys CLK_MM_DISP_WDMA>;
175 clocks = <&mmsys CLK_MM_MDP_BLS_26M>
[all...] |
| mt2701.dtsi | 194 <&mmsys CLK_MM_SMI_COMMON>,
515 mmsys: syscon@14000000 { label
516 compatible = "mediatek,mt2701-mmsys", "syscon";
525 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
535 clocks = <&mmsys CLK_MM_SMI_LARB0>,
536 <&mmsys CLK_MM_SMI_LARB0>;
|
