| /src/sys/arch/arm/amlogic/ |
| meson_clk_mpll.c | 45 struct meson_clk_mpll *mpll = &clk->u.mpll; local in function:meson_clk_mpll_get_rate
63 val = CLK_READ(sc, mpll->sdm.reg);
64 sdm = __SHIFTOUT(val, mpll->sdm.mask);
66 val = CLK_READ(sc, mpll->n2.reg);
67 n2 = __SHIFTOUT(val, mpll->n2.mask);
82 struct meson_clk_mpll *mpll = &clk->u.mpll; local in function:meson_clk_mpll_get_parent
86 return mpll->parent;
|
| meson_clk.h | 298 * MPLL clocks
320 .u.mpll.parent = (_parent), \
321 .u.mpll.sdm = _sdm, \
322 .u.mpll.sdm_enable = _sdm_enable, \
323 .u.mpll.n2 = _n2, \
324 .u.mpll.ssen = _ssen, \
325 .u.mpll.flags = (_flags), \
342 struct meson_clk_mpll mpll; member in union:meson_clk_clk::__anon83605c73010a
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| mstar-v7.dtsi | 9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
142 mpll: mpll@206000 { label in label:soc
143 compatible = "mstar,msc313-mpll";
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_clocks.c | 77 struct radeon_pll *mpll = &rdev->clock.mpll; local in function:radeon_legacy_get_memory_clock
83 fb_div *= mpll->reference_freq;
117 struct radeon_pll *mpll = &rdev->clock.mpll; local in function:radeon_read_clocks_OF
155 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
156 spll->reference_div = mpll->reference_div =
192 struct radeon_pll *mpll = &rdev->clock.mpll; local in function:radeon_get_clock_info
224 if (mpll->reference_div < 2
[all...] |
| radeon_combios.c | 745 struct radeon_pll *mpll = &rdev->clock.mpll; local in function:radeon_combios_get_clock_info
786 mpll->reference_freq = RBIOS16(pll_info + 0x26);
787 mpll->reference_div = RBIOS16(pll_info + 0x28);
788 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
789 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
792 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
793 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
796 mpll->pll_in_min = 40;
797 mpll->pll_in_max = 500
[all...] |
| radeon_atombios.c | 1144 struct radeon_pll *mpll = &rdev->clock.mpll; local in function:radeon_atom_get_clock_info
1223 mpll->reference_freq =
1226 mpll->reference_freq =
1228 mpll->reference_div = 0;
1230 mpll->pll_out_min =
1232 mpll->pll_out_max =
1236 if (mpll->pll_out_min == 0) {
1238 mpll->pll_out_min = 64800;
1240 mpll->pll_out_min = 20000
[all...] |
| radeon.h | 284 struct radeon_pll mpll; member in struct:radeon_clock
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/ |
| sharkl3.dtsi | 91 mpll: mpll { label in label:soc.anlg_phy_g4_regs
92 compatible = "sprd,sc9863a-mpll";
|
| /src/sys/arch/mips/ingenic/ |
| apbus.c | 129 uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv; local in function:apbus_attach
141 /* assuming we're using MPLL */
142 mpll = readreg(JZ_CPMPCR);
143 m = (mpll & JZ_PLLM_M) >> JZ_PLLM_S;
144 n = (mpll & JZ_PLLN_M) >> JZ_PLLN_S;
145 p = (mpll & JZ_PLLP_M) >> JZ_PLLP_S;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atomfirmware.c | 351 struct amdgpu_pll *mpll = &adev->clock.mpll; local in function:amdgpu_atomfirmware_get_clock_info
411 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
413 mpll->reference_div = 0;
414 mpll->min_post_div = 1;
415 mpll->max_post_div = 1;
416 mpll->min_ref_div = 2;
417 mpll->max_ref_div = 0xff;
418 mpll->min_feedback_div = 4;
419 mpll->max_feedback_div = 0xff
[all...] |
| amdgpu_atombios.c | 578 struct amdgpu_pll *mpll = &adev->clock.mpll; local in function:amdgpu_atombios_get_clock_info
650 mpll->reference_freq =
652 mpll->reference_div = 0;
654 mpll->pll_out_min =
656 mpll->pll_out_max =
660 if (mpll->pll_out_min == 0)
661 mpll->pll_out_min = 64800;
663 mpll->pll_in_min =
665 mpll->pll_in_max
[all...] |
| amdgpu.h | 343 struct amdgpu_pll mpll; member in struct:amdgpu_clock
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_nv04.c | 293 bool mpll = Preg == 0x4020; local in function:setPLL_double_lowregs
296 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
311 if (mpll) {
327 Pval |= mpll ? 1 << 12 : 1 << 8;
331 if (mpll) {
345 if (mpll) {
354 if (mpll) {
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramnv50.c | 231 struct nvbios_pll mpll; local in function:nv50_ram_calc
333 ret = nvbios_pll_parse(bios, 0x004008, &mpll);
334 mpll.vco2.max_freq = 0;
336 ret = nv04_pll_calc(subdev, &mpll, freq,
354 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16);
|
