1 /* $NetBSD: kfd_mqd_manager_v9.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016-2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: kfd_mqd_manager_v9.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $"); 28 29 #include <linux/printk.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include "kfd_priv.h" 33 #include "kfd_mqd_manager.h" 34 #include "v9_structs.h" 35 #include "gc/gc_9_0_offset.h" 36 #include "gc/gc_9_0_sh_mask.h" 37 #include "sdma0/sdma0_4_0_sh_mask.h" 38 #include "amdgpu_amdkfd.h" 39 40 static inline struct v9_mqd *get_mqd(void *mqd) 41 { 42 return (struct v9_mqd *)mqd; 43 } 44 45 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 46 { 47 return (struct v9_sdma_mqd *)mqd; 48 } 49 50 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 51 struct queue_properties *q) 52 { 53 struct v9_mqd *m; 54 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 55 56 if (q->cu_mask_count == 0) 57 return; 58 59 mqd_symmetrically_map_cu_mask(mm, 60 q->cu_mask, q->cu_mask_count, se_mask); 61 62 m = get_mqd(mqd); 63 m->compute_static_thread_mgmt_se0 = se_mask[0]; 64 m->compute_static_thread_mgmt_se1 = se_mask[1]; 65 m->compute_static_thread_mgmt_se2 = se_mask[2]; 66 m->compute_static_thread_mgmt_se3 = se_mask[3]; 67 m->compute_static_thread_mgmt_se4 = se_mask[4]; 68 m->compute_static_thread_mgmt_se5 = se_mask[5]; 69 m->compute_static_thread_mgmt_se6 = se_mask[6]; 70 m->compute_static_thread_mgmt_se7 = se_mask[7]; 71 72 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 73 m->compute_static_thread_mgmt_se0, 74 m->compute_static_thread_mgmt_se1, 75 m->compute_static_thread_mgmt_se2, 76 m->compute_static_thread_mgmt_se3, 77 m->compute_static_thread_mgmt_se4, 78 m->compute_static_thread_mgmt_se5, 79 m->compute_static_thread_mgmt_se6, 80 m->compute_static_thread_mgmt_se7); 81 } 82 83 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 84 { 85 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 86 m->cp_hqd_queue_priority = q->priority; 87 } 88 89 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 90 struct queue_properties *q) 91 { 92 int retval; 93 struct kfd_mem_obj *mqd_mem_obj = NULL; 94 95 /* From V9, for CWSR, the control stack is located on the next page 96 * boundary after the mqd, we will use the gtt allocation function 97 * instead of sub-allocation function. 98 */ 99 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 100 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 101 if (!mqd_mem_obj) 102 return NULL; 103 retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd, 104 ALIGN(q->ctl_stack_size, PAGE_SIZE) + 105 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE), 106 &(mqd_mem_obj->gtt_mem), 107 &(mqd_mem_obj->gpu_addr), 108 (void *)&(mqd_mem_obj->cpu_ptr), true); 109 } else { 110 retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd), 111 &mqd_mem_obj); 112 } 113 114 if (retval) { 115 kfree(mqd_mem_obj); 116 return NULL; 117 } 118 119 return mqd_mem_obj; 120 121 } 122 123 static void init_mqd(struct mqd_manager *mm, void **mqd, 124 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 125 struct queue_properties *q) 126 { 127 uint64_t addr; 128 struct v9_mqd *m; 129 130 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 131 addr = mqd_mem_obj->gpu_addr; 132 133 memset(m, 0, sizeof(struct v9_mqd)); 134 135 m->header = 0xC0310800; 136 m->compute_pipelinestat_enable = 1; 137 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 138 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 139 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 140 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 141 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 142 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 143 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 144 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 145 146 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 147 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 148 149 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 150 151 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 152 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 153 154 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 155 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 156 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 157 158 if (q->format == KFD_QUEUE_FORMAT_AQL) { 159 m->cp_hqd_aql_control = 160 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 161 } 162 163 if (q->tba_addr) { 164 m->compute_pgm_rsrc2 |= 165 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 166 } 167 168 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { 169 m->cp_hqd_persistent_state |= 170 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 171 m->cp_hqd_ctx_save_base_addr_lo = 172 lower_32_bits(q->ctx_save_restore_area_address); 173 m->cp_hqd_ctx_save_base_addr_hi = 174 upper_32_bits(q->ctx_save_restore_area_address); 175 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 176 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 177 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 178 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 179 } 180 181 *mqd = m; 182 if (gart_addr) 183 *gart_addr = addr; 184 mm->update_mqd(mm, m, q); 185 } 186 187 static int load_mqd(struct mqd_manager *mm, void *mqd, 188 uint32_t pipe_id, uint32_t queue_id, 189 struct queue_properties *p, struct mm_struct *mms) 190 { 191 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 192 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 193 194 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 195 (uint32_t __user *)p->write_ptr, 196 wptr_shift, 0, mms); 197 } 198 199 static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, 200 uint32_t pipe_id, uint32_t queue_id, 201 struct queue_properties *p, struct mm_struct *mms) 202 { 203 return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->kgd, mqd, pipe_id, 204 queue_id, p->doorbell_off); 205 } 206 207 static void update_mqd(struct mqd_manager *mm, void *mqd, 208 struct queue_properties *q) 209 { 210 struct v9_mqd *m; 211 212 m = get_mqd(mqd); 213 214 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 215 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 216 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 217 218 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 219 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 220 221 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 222 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 223 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 224 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 225 226 m->cp_hqd_pq_doorbell_control = 227 q->doorbell_off << 228 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 229 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 230 m->cp_hqd_pq_doorbell_control); 231 232 m->cp_hqd_ib_control = 233 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 234 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 235 236 /* 237 * HW does not clamp this field correctly. Maximum EOP queue size 238 * is constrained by per-SE EOP done signal count, which is 8-bit. 239 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 240 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 241 * is safe, giving a maximum field value of 0xA. 242 */ 243 m->cp_hqd_eop_control = min(0xA, 244 order_base_2(q->eop_ring_buffer_size / 4) - 1); 245 m->cp_hqd_eop_base_addr_lo = 246 lower_32_bits(q->eop_ring_buffer_address >> 8); 247 m->cp_hqd_eop_base_addr_hi = 248 upper_32_bits(q->eop_ring_buffer_address >> 8); 249 250 m->cp_hqd_iq_timer = 0; 251 252 m->cp_hqd_vmid = q->vmid; 253 254 if (q->format == KFD_QUEUE_FORMAT_AQL) { 255 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 256 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 257 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 258 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 259 m->cp_hqd_pq_doorbell_control |= 1 << 260 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 261 } 262 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) 263 m->cp_hqd_ctx_save_control = 0; 264 265 update_cu_mask(mm, mqd, q); 266 set_priority(m, q); 267 268 q->is_active = QUEUE_IS_ACTIVE(*q); 269 } 270 271 272 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 273 enum kfd_preempt_type type, 274 unsigned int timeout, uint32_t pipe_id, 275 uint32_t queue_id) 276 { 277 return mm->dev->kfd2kgd->hqd_destroy 278 (mm->dev->kgd, mqd, type, timeout, 279 pipe_id, queue_id); 280 } 281 282 static void free_mqd(struct mqd_manager *mm, void *mqd, 283 struct kfd_mem_obj *mqd_mem_obj) 284 { 285 struct kfd_dev *kfd = mm->dev; 286 287 if (mqd_mem_obj->gtt_mem) { 288 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, mqd_mem_obj->gtt_mem); 289 kfree(mqd_mem_obj); 290 } else { 291 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 292 } 293 } 294 295 static bool is_occupied(struct mqd_manager *mm, void *mqd, 296 uint64_t queue_address, uint32_t pipe_id, 297 uint32_t queue_id) 298 { 299 return mm->dev->kfd2kgd->hqd_is_occupied( 300 mm->dev->kgd, queue_address, 301 pipe_id, queue_id); 302 } 303 304 static int get_wave_state(struct mqd_manager *mm, void *mqd, 305 void __user *ctl_stack, 306 u32 *ctl_stack_used_size, 307 u32 *save_area_used_size) 308 { 309 struct v9_mqd *m; 310 311 /* Control stack is located one page after MQD. */ 312 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 313 314 m = get_mqd(mqd); 315 316 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 317 m->cp_hqd_cntl_stack_offset; 318 *save_area_used_size = m->cp_hqd_wg_state_offset - 319 m->cp_hqd_cntl_stack_size; 320 321 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) 322 return -EFAULT; 323 324 return 0; 325 } 326 327 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 328 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 329 struct queue_properties *q) 330 { 331 struct v9_mqd *m; 332 333 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 334 335 m = get_mqd(*mqd); 336 337 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 338 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 339 } 340 341 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 342 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 343 struct queue_properties *q) 344 { 345 struct v9_sdma_mqd *m; 346 347 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 348 349 memset(m, 0, sizeof(struct v9_sdma_mqd)); 350 351 *mqd = m; 352 if (gart_addr) 353 *gart_addr = mqd_mem_obj->gpu_addr; 354 355 mm->update_mqd(mm, m, q); 356 } 357 358 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 359 uint32_t pipe_id, uint32_t queue_id, 360 struct queue_properties *p, struct mm_struct *mms) 361 { 362 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 363 (uint32_t __user *)p->write_ptr, 364 mms); 365 } 366 367 #define SDMA_RLC_DUMMY_DEFAULT 0xf 368 369 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 370 struct queue_properties *q) 371 { 372 struct v9_sdma_mqd *m; 373 374 m = get_sdma_mqd(mqd); 375 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 376 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 377 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 378 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 379 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 380 381 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 382 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 383 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 384 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 385 m->sdmax_rlcx_doorbell_offset = 386 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 387 388 m->sdma_engine_id = q->sdma_engine_id; 389 m->sdma_queue_id = q->sdma_queue_id; 390 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 391 392 q->is_active = QUEUE_IS_ACTIVE(*q); 393 } 394 395 /* 396 * * preempt type here is ignored because there is only one way 397 * * to preempt sdma queue 398 */ 399 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 400 enum kfd_preempt_type type, 401 unsigned int timeout, uint32_t pipe_id, 402 uint32_t queue_id) 403 { 404 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 405 } 406 407 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 408 uint64_t queue_address, uint32_t pipe_id, 409 uint32_t queue_id) 410 { 411 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 412 } 413 414 #if defined(CONFIG_DEBUG_FS) 415 416 static int debugfs_show_mqd(struct seq_file *m, void *data) 417 { 418 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 419 data, sizeof(struct v9_mqd), false); 420 return 0; 421 } 422 423 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 424 { 425 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 426 data, sizeof(struct v9_sdma_mqd), false); 427 return 0; 428 } 429 430 #endif 431 432 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 433 struct kfd_dev *dev) 434 { 435 struct mqd_manager *mqd; 436 437 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 438 return NULL; 439 440 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 441 if (!mqd) 442 return NULL; 443 444 mqd->dev = dev; 445 446 switch (type) { 447 case KFD_MQD_TYPE_CP: 448 mqd->allocate_mqd = allocate_mqd; 449 mqd->init_mqd = init_mqd; 450 mqd->free_mqd = free_mqd; 451 mqd->load_mqd = load_mqd; 452 mqd->update_mqd = update_mqd; 453 mqd->destroy_mqd = destroy_mqd; 454 mqd->is_occupied = is_occupied; 455 mqd->get_wave_state = get_wave_state; 456 mqd->mqd_size = sizeof(struct v9_mqd); 457 #if defined(CONFIG_DEBUG_FS) 458 mqd->debugfs_show_mqd = debugfs_show_mqd; 459 #endif 460 break; 461 case KFD_MQD_TYPE_HIQ: 462 mqd->allocate_mqd = allocate_hiq_mqd; 463 mqd->init_mqd = init_mqd_hiq; 464 mqd->free_mqd = free_mqd_hiq_sdma; 465 mqd->load_mqd = hiq_load_mqd_kiq; 466 mqd->update_mqd = update_mqd; 467 mqd->destroy_mqd = destroy_mqd; 468 mqd->is_occupied = is_occupied; 469 mqd->mqd_size = sizeof(struct v9_mqd); 470 #if defined(CONFIG_DEBUG_FS) 471 mqd->debugfs_show_mqd = debugfs_show_mqd; 472 #endif 473 break; 474 case KFD_MQD_TYPE_DIQ: 475 mqd->allocate_mqd = allocate_mqd; 476 mqd->init_mqd = init_mqd_hiq; 477 mqd->free_mqd = free_mqd; 478 mqd->load_mqd = load_mqd; 479 mqd->update_mqd = update_mqd; 480 mqd->destroy_mqd = destroy_mqd; 481 mqd->is_occupied = is_occupied; 482 mqd->mqd_size = sizeof(struct v9_mqd); 483 #if defined(CONFIG_DEBUG_FS) 484 mqd->debugfs_show_mqd = debugfs_show_mqd; 485 #endif 486 break; 487 case KFD_MQD_TYPE_SDMA: 488 mqd->allocate_mqd = allocate_sdma_mqd; 489 mqd->init_mqd = init_mqd_sdma; 490 mqd->free_mqd = free_mqd_hiq_sdma; 491 mqd->load_mqd = load_mqd_sdma; 492 mqd->update_mqd = update_mqd_sdma; 493 mqd->destroy_mqd = destroy_mqd_sdma; 494 mqd->is_occupied = is_occupied_sdma; 495 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 496 #if defined(CONFIG_DEBUG_FS) 497 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 498 #endif 499 break; 500 default: 501 kfree(mqd); 502 return NULL; 503 } 504 505 return mqd; 506 } 507
Indexes created Sat Sep 20 22:09:52 GMT 2025